Semiconductor module

Soyano , et al. September 4, 2

Patent Grant D827593

U.S. patent number D827,593 [Application Number D/632,135] was granted by the patent office on 2018-09-04 for semiconductor module. This patent grant is currently assigned to Fuji Electric Co., Ltd. The grantee listed for this patent is Fuji Electric Co., Ltd. Invention is credited to Keiichi Higuchi, Takahiro Koyama, Shin Soyano, Yoshikazu Takamiya.


United States Patent D827,593
Soyano ,   et al. September 4, 2018

Semiconductor module

Claims

CLAIM The ornamental design for a semiconductor module, as shown and described.
Inventors: Soyano; Shin (Tokyo, JP), Takamiya; Yoshikazu (Tokyo, JP), Higuchi; Keiichi (Tokyo, JP), Koyama; Takahiro (Tokyo, JP)
Applicant:
Name City State Country Type

Fuji Electric Co., Ltd

Kawasaki-shi OT

N/A

JP
Assignee: Fuji Electric Co., Ltd (Kawasaki-Shi, JP)
Appl. No.: D/632,135
Filed: January 5, 2018

Related U.S. Patent Documents

Application Number Filing Date Patent Number Issue Date
29580736 Oct 12, 2016 D814433
29528214 Dec 20, 2016 D774479

Foreign Application Priority Data

Nov 28, 2014 [JP] D2014-026634
Nov 28, 2014 [JP] D2014-026635
Nov 28, 2014 [JP] D2014-026636
Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182 ;257/678,684,690,691 ;361/679.01,713,728,736,760,761,772,775,783,820 ;174/250,253 ;438/15,25,26,51,55,63,64,106 ;D8/349,364,381 ;D23/265,259,262

References Cited [Referenced By]

U.S. Patent Documents
4517585 May 1985 Ridout
D339277 September 1993 Snider
5347160 September 1994 Sutrina
D357671 April 1995 Terasawa et al.
D357672 April 1995 Terasawa et al.
D360619 July 1995 Terasawa et al.
D367249 February 1996 Ott
5505546 April 1996 Okude
D371139 June 1996 Waskiewicz
D389808 January 1998 Yamada et al.
D396450 July 1998 Nishiura et al.
D420688 February 2000 Ichihara
D441726 May 2001 Sofue et al.
6521983 February 2003 Yoshimatsu et al.
D476959 July 2003 Yamada et al.
D587662 March 2009 Soutome et al.
D589012 March 2009 Soyano et al.
D606951 December 2009 Soyano et al.
7768118 August 2010 Yoshida
D653633 February 2012 Soyano
D653634 February 2012 Soyano
D686174 July 2013 Soyano
D689446 September 2013 Soyano
D704670 May 2014 Chen et al.
D704671 May 2014 Chen et al.
D705184 May 2014 Takahashi et al.
D706232 June 2014 Nakamura
D710317 August 2014 Chen et al.
D710318 August 2014 Chen et al.
D710319 August 2014 Chen et al.
D712853 September 2014 Nakamura
D721048 January 2015 Nakamura
D721340 January 2015 Nakamura
D724554 March 2015 Motohashi et al.
D748595 February 2016 Bertalan et al.
D754084 April 2016 Kawase
D759604 June 2016 Yoneyama et al.
D762185 July 2016 Muehlensiep et al.
D762597 August 2016 Bertalan et al.
D766851 September 2016 Yoneyama et al.
D767516 September 2016 Yoneyama et al.
D772184 November 2016 Soyano et al.
D773412 December 2016 Yoneyama et al.
D773413 December 2016 Yoneyama et al.
D774479 December 2016 Soyano et al.
D775091 December 2016 Edenharter et al.
D775593 January 2017 Edenharter et al.
D776071 January 2017 Edenharter et al.
D779921 February 2017 Del Rossa
D779922 February 2017 Del Rossa
D779923 February 2017 Del Rossa
D785577 May 2017 Kawase
D799439 October 2017 Hayashiguchi
D805485 December 2017 Kawase
D810036 February 2018 Sawayanagi
D810706 February 2018 Soyano
D814431 April 2018 Matsumoto
D814433 April 2018 Soyano
2001/0038143 November 2001 Sonobe et al.
2010/0149774 June 2010 Matsumoto et al.
2011/0044012 February 2011 Matsumoto
2011/0047997 March 2011 Goplen
2016/0273440 September 2016 Eadie

Other References

US. Appl. No. 29/580,738, filed Oct. 12, 2016. cited by applicant.

Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Young Basile Hanlon & MacFarlane, P.C.

Description



FIG. 1 is a front view of a semiconductor module showing our new design.

FIG. 2 is a rear view of the semiconductor module of FIG. 1.

FIG. 3 is a left side view of the semiconductor module of FIG. 1.

FIG. 4 is a right side view of the semiconductor module of FIG. 1.

FIG. 5 is a top view of the semiconductor module of FIG. 1.

FIG. 6 is a bottom view of the semiconductor module of FIG. 1.

FIG. 7 is a front, right, and bottom perspective view of the semiconductor module of FIG. 1; and,

FIG. 8 is a rear, left, and top perspective view of the semiconductor module of FIG. 1.

The broken lines shown in the drawing views of FIGS. 1-8 form no part of the claimed design.

* * * * *


uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed