U.S. patent number D827,593 [Application Number D/632,135] was granted by the patent office on 2018-09-04 for semiconductor module.
This patent grant is currently assigned to Fuji Electric Co., Ltd. The grantee listed for this patent is Fuji Electric Co., Ltd. Invention is credited to Keiichi Higuchi, Takahiro Koyama, Shin Soyano, Yoshikazu Takamiya.
United States Patent |
D827,593 |
Soyano , et al. |
September 4, 2018 |
Semiconductor module
Claims
CLAIM The ornamental design for a semiconductor module, as shown
and described.
Inventors: |
Soyano; Shin (Tokyo,
JP), Takamiya; Yoshikazu (Tokyo, JP),
Higuchi; Keiichi (Tokyo, JP), Koyama; Takahiro
(Tokyo, JP) |
Applicant: |
Name |
City |
State |
Country |
Type |
Fuji Electric Co., Ltd |
Kawasaki-shi OT |
N/A |
JP |
|
|
Assignee: |
Fuji Electric Co., Ltd
(Kawasaki-Shi, JP)
|
Appl.
No.: |
D/632,135 |
Filed: |
January 5, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
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29580736 |
Oct 12, 2016 |
D814433 |
|
|
|
29528214 |
Dec 20, 2016 |
D774479 |
|
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Foreign Application Priority Data
|
|
|
|
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Nov 28, 2014 [JP] |
|
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D2014-026634 |
Nov 28, 2014 [JP] |
|
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D2014-026635 |
Nov 28, 2014 [JP] |
|
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D2014-026636 |
|
Current U.S.
Class: |
D13/182 |
Current International
Class: |
1303 |
Field of
Search: |
;D13/182
;257/678,684,690,691
;361/679.01,713,728,736,760,761,772,775,783,820 ;174/250,253
;438/15,25,26,51,55,63,64,106 ;D8/349,364,381 ;D23/265,259,262 |
References Cited
[Referenced By]
U.S. Patent Documents
Other References
US. Appl. No. 29/580,738, filed Oct. 12, 2016. cited by
applicant.
|
Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Young Basile Hanlon &
MacFarlane, P.C.
Description
FIG. 1 is a front view of a semiconductor module showing our new
design.
FIG. 2 is a rear view of the semiconductor module of FIG. 1.
FIG. 3 is a left side view of the semiconductor module of FIG.
1.
FIG. 4 is a right side view of the semiconductor module of FIG.
1.
FIG. 5 is a top view of the semiconductor module of FIG. 1.
FIG. 6 is a bottom view of the semiconductor module of FIG. 1.
FIG. 7 is a front, right, and bottom perspective view of the
semiconductor module of FIG. 1; and,
FIG. 8 is a rear, left, and top perspective view of the
semiconductor module of FIG. 1.
The broken lines shown in the drawing views of FIGS. 1-8 form no
part of the claimed design.
* * * * *