U.S. patent number D721,340 [Application Number D/458,667] was granted by the patent office on 2015-01-20 for semiconductor module.
This patent grant is currently assigned to Fuji Electric Co., Ltd.. The grantee listed for this patent is Fuji Electric Co., Ltd.. Invention is credited to Hideyo Nakamura.
United States Patent |
D721,340 |
Nakamura |
January 20, 2015 |
Semiconductor module
Claims
CLAIM The ornamental design for a semiconductor module, as shown
and described.
Inventors: |
Nakamura; Hideyo (Kawasaki,
JP) |
Applicant: |
Name |
City |
State |
Country |
Type |
Fuji Electric Co., Ltd. |
Kawasaki |
N/A |
JP |
|
|
Assignee: |
Fuji Electric Co., Ltd.
(Kawasaki-shi, Kanagawa, JP)
|
Appl.
No.: |
D/458,667 |
Filed: |
June 21, 2013 |
Foreign Application Priority Data
|
|
|
|
|
Dec 21, 2012 [JP] |
|
|
D2012-031249 |
|
Current U.S.
Class: |
D13/182 |
Current International
Class: |
1303 |
Field of
Search: |
;D13/110,182
;257/678,684,690,691
;361/679.01,713,728,736,760,761,772,775,783,820 ;174/250,253
;438/15,25,26,51,55,63,64,106 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Young Basile Hanlon &
MacFarlane P.C.
Description
FIG. 1 is a front view of a semiconductor module showing my new
design;
FIG. 2 is a rear view thereof;
FIG. 3 is a left side view thereof;
FIG. 4 is a right side view thereof;
FIG. 5 is a top plan view thereof;
FIG. 6 is a bottom plan view thereof;
FIG. 7 is a perspective view thereof; and,
FIG. 8 is a cross-sectional view thereof taken along line 8-8 of
FIG. 5.
The ornamental design of the present disclosure is a semiconductor
module on which power semiconductor elements and the like may be
mounted. A plurality of pin-shaped terminals protrudes from the top
surface. Each end in a longitudinal direction includes a mounting
hole.
* * * * *