U.S. patent number D548,203 [Application Number D/264,892] was granted by the patent office on 2007-08-07 for semiconductor.
This patent grant is currently assigned to Kabushiki Kaisha Toshiba. Invention is credited to Ichiro Takahashi.
United States Patent |
D548,203 |
Takahashi |
August 7, 2007 |
Semiconductor
Claims
CLAIM The ornamental design for a semiconductor, as shown and
described.
Inventors: |
Takahashi; Ichiro (Suginami-ku,
JP) |
Assignee: |
Kabushiki Kaisha Toshiba
(JP)
|
Appl.
No.: |
D/264,892 |
Filed: |
August 22, 2006 |
Foreign Application Priority Data
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Apr 17, 2006 [JP] |
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2006-009885 |
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Current U.S.
Class: |
D13/182 |
Current International
Class: |
1303 |
Field of
Search: |
;D13/133,146-147,149,154,182,184 ;174/250,253 ;257/666,694,696,820
;381/760 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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D801093 |
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Nov 1990 |
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JP |
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D946124 |
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Feb 1996 |
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JP |
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D982886 |
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Jun 1997 |
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JP |
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D106269 |
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Sep 2005 |
|
TW |
|
Primary Examiner: Bui; Daniel
Attorney, Agent or Firm: Banner & Witcoff, Ltd.
Description
FIG. 1 is a bottom, front and left side perspective view of a
semiconductor showing my new design,
FIG. 2 is a front elevational view thereof,
FIG. 3 is a rear elevational view thereof,
FIG. 4 is a right side elevational view thereof,
FIG. 5 is a right side elevational view thereof,
FIG. 6 is a top plan view thereof; and,
FIG. 7 is a bottom plan view thereof.
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