Semiconductor device

Majumdar , et al. December 1, 1

Patent Grant D401912

U.S. patent number D401,912 [Application Number D/055,038] was granted by the patent office on 1998-12-01 for semiconductor device. This patent grant is currently assigned to Mitsubishi Denki Kabushiki Kaisha. Invention is credited to Tooru Iwagami, Hisashi Kawafuji, Gorab Majumdar, Satoshi Mori, Sukehisa Noda, Yoshio Takagi.


United States Patent D401,912
Majumdar ,   et al. December 1, 1998

Semiconductor device

Claims

The ornamental design for a semiconductor device, as shown and described.
Inventors: Majumdar; Gorab (Tokyo, JP), Mori; Satoshi (Tokyo, JP), Noda; Sukehisa (Tokyo, JP), Iwagami; Tooru (Tokyo, JP), Takagi; Yoshio (Tokyo, JP), Kawafuji; Hisashi (Tokyo, JP)
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Appl. No.: D/055,038
Filed: May 28, 1996

Foreign Application Priority Data

Nov 27, 1995 [JP] 7-35816
Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182 ;174/16.3,52.2,52.4 ;257/670,676,686,688,690-692,696,703,787 ;437/217

References Cited [Referenced By]

U.S. Patent Documents
D288922 March 1987 Olla
D357901 May 1995 Horman
3762039 October 1973 Douglass et al.
4012766 March 1977 Phillips et al.
5095360 March 1992 Kizaki et al.
Foreign Patent Documents
5-15449 Feb 1993 JP
7-250485 Sep 1995 JP

Other References

Toshiba GTR Module 1989, p. 26. .
Mitsubishi '85 M53200P Series, 1985..

Primary Examiner: Asch; Jeffrey
Assistant Examiner: Matta; Cathron B.
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.

Description



FIG. 1 is a top, front and right side perspective view of semiconductor device showing our new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a top plan view thereof;

FIG. 4 is a bottom plan view thereof;

FIG. 5 is a rear elevational view thereof; and,

FIG. 6 is a right side view thereo, the left side being a mirror image of the side shown.

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