Elastic membrane for semiconductor wafer polishing

Description

FIG. 1 is a bottom perspective view of an elastic membrane for semiconductor wafer polishing showing our new design;

FIG. 2 is a top perspective view thereof;

FIG. 3 is a bottom view thereof;

FIG. 4 is a top view thereof;

FIG. 5 is a front view thereof, rear view being identical;

FIG. 6 is a right-side view thereof, left-side view being identical;

FIG. 7 is a cross-sectional view taken along line 7-7 of FIG. 4; and,

FIG. 8 is an enlarged portion view labeled FIG. 8 in FIG. 7.

The portions of the elastic membrane shown in even broken lines form no part of the claimed design. The dashed-dot lines in the drawings represent the boundary lines of the claimed design. The box labeled FIG. 8 shown in even broken lines in FIG. 7 defines the enlarged portion view of FIG. 8.

Claims

CLAIM The ornamental design for an elastic membrane for semiconductor wafer polishing, as shown and described.

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Inventors:	Yamaki; Satoru (Tokyo, JP), Fukushima; Makoto (Tokyo, JP), Namiki; Keisuke (Tokyo, JP), Nabeya; Osamu (Tokyo, JP), Togashi; Shingo (Tokyo, JP), Owada; Tomoko (Tokyo, JP), Kishimoto; Masahiko (Tokyo, JP)
Applicant:	Name City State Country Type EBARA CORPORATION Tokyo N/A JP
Assignee:	EBARA CORPORATION (Tokyo, JP)
Appl. No.:	D/672,852
Filed:	December 10, 2018

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	29606998	Jun 9, 2017	D839224

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Foreign Application Priority Data

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Dec 12, 2016 [JP]			2016-026913
Dec 12, 2016 [JP]			2016-026914
Dec 12, 2016 [JP]			2016-026915

Current U.S. Class:	D13/182
Current International Class:	1303
Field of Search:	;D13/182 ;451/66,288,289

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References Cited [Referenced By]

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U.S. Patent Documents

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Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Pearne & Gordon LLP

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