U.S. patent number D813,180 [Application Number D/580,339] was granted by the patent office on 2018-03-20 for elastic membrane for semiconductor wafer polishing apparatus.
This patent grant is currently assigned to EBARA CORPORATION. The grantee listed for this patent is EBARA CORPORATION. Invention is credited to Makoto Fukushima, Osamu Nabeya, Keisuke Namiki, Shingo Togashi, Satoru Yamaki, Hozumi Yasuda.
United States Patent |
D813,180 |
Fukushima , et al. |
March 20, 2018 |
Elastic membrane for semiconductor wafer polishing apparatus
Claims
CLAIM The ornamental design for an elastic membrane for
semiconductor wafer polishing apparatus, as shown and described.
Inventors: |
Fukushima; Makoto (Tokyo,
JP), Yasuda; Hozumi (Tokyo, JP), Namiki;
Keisuke (Tokyo, JP), Nabeya; Osamu (Tokyo,
JP), Togashi; Shingo (Tokyo, JP), Yamaki;
Satoru (Tokyo, JP) |
Applicant: |
Name |
City |
State |
Country |
Type |
EBARA CORPORATION |
Tokyo |
N/A |
JP |
|
|
Assignee: |
EBARA CORPORATION (Tokyo,
JP)
|
Appl.
No.: |
D/580,339 |
Filed: |
October 7, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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29472346 |
Nov 12, 2013 |
D769200 |
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Foreign Application Priority Data
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May 15, 2013 [JP] |
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2013-10672 |
May 15, 2013 [JP] |
|
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2013-10673 |
May 15, 2013 [JP] |
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2013-10674 |
May 15, 2013 [JP] |
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2013-10675 |
May 15, 2013 [JP] |
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2013-10676 |
May 15, 2013 [JP] |
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2013-10677 |
May 15, 2013 [JP] |
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2013-10678 |
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Current U.S.
Class: |
D13/182 |
Current International
Class: |
1303 |
Field of
Search: |
;D13/182
;451/66,288,289 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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301348233 |
|
Sep 2010 |
|
CN |
|
301445758 |
|
Jan 2011 |
|
CN |
|
D 138225 |
|
Dec 2010 |
|
TW |
|
D 139857 |
|
Apr 2011 |
|
TW |
|
D 146491 |
|
Apr 2012 |
|
TW |
|
Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Pearne & Gordon LLP
Description
FIG. 1 is a top plan view of a first embodiment of an elastic
membrane for semiconductor wafer polishing apparatus showing our
new design;
FIG. 2 is a bottom plan view thereof;
FIG. 3 is a front side view thereof;
FIG. 4 is a right side view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a cross sectional view taken along section line 6-6 in
FIG. 1;
FIG. 7 is an enlarged perspective view of a portion labeled FIG. 7
in FIG. 1;
FIG. 8 is an opposite side view of FIG. 7;
FIG. 9 is a top plan view of a second embodiment of an elastic
membrane for semiconductor wafer polishing apparatus showing our
new design;
FIG. 10 is a bottom plan view thereof;
FIG. 11 is a front side view thereof;
FIG. 12 is a right side view thereof;
FIG. 13 is a left side view thereof;
FIG. 14 is a cross sectional view taken along section line 14-14 in
FIG. 9;
FIG. 15 is an enlarged perspective view of a portion labeled FIG.
15 in FIG. 9; and,
FIG. 16 is an opposite side view of FIG. 15.
The broken lines shown in the drawings represent portions of the
elastic membrane for semiconductor wafer polishing apparatus that
form no part of the claimed design. The dashed-dot-dashed lines
represent the boundary lines of the claimed design.
All surfaces not shown form no part of the claimed design.
* * * * *