Elastic membrane for semiconductor wafer polishing apparatus

Fukushima , et al. October 18, 2

Patent Grant D769200

U.S. patent number D769,200 [Application Number D/472,346] was granted by the patent office on 2016-10-18 for elastic membrane for semiconductor wafer polishing apparatus. This patent grant is currently assigned to EBARA CORPORATION. The grantee listed for this patent is EBARA CORPORATION. Invention is credited to Makoto Fukushima, Osamu Nabeya, Keisuke Namiki, Shingo Togashi, Satoru Yamaki, Hozumi Yasuda.


United States Patent D769,200
Fukushima ,   et al. October 18, 2016

Elastic membrane for semiconductor wafer polishing apparatus

Claims

CLAIM The ornamental design for an elastic membrane for semiconductor wafer polishing apparatus, as shown and described.
Inventors: Fukushima; Makoto (Tokyo, JP), Yasuda; Hozumi (Tokyo, JP), Namiki; Keisuke (Tokyo, JP), Nabeya; Osamu (Tokyo, JP), Togashi; Shingo (Tokyo, JP), Yamaki; Satoru (Toyko, JP)
Applicant:
Name City State Country Type

EBARA CORPORATION

Tokyo

N/A

JP
Assignee: EBARA CORPORATION (Tokyo, JP)
Appl. No.: D/472,346
Filed: November 12, 2013

Foreign Application Priority Data

May 15, 2013 [JP] 2013-10672
May 15, 2013 [JP] 2013-10673
May 15, 2013 [JP] 2013-10674
May 15, 2013 [JP] 2013-10675
May 15, 2013 [JP] 2013-10676
May 15, 2013 [JP] 2013-10677
May 15, 2013 [JP] 2013-10678
Current U.S. Class: D13/182
Current International Class: 1303
Field of Search: ;D13/182 ;451/66,288,289

References Cited [Referenced By]

U.S. Patent Documents
6659850 December 2003 Korovin
7357699 April 2008 Togawa
7402098 July 2008 Severson
D616390 May 2010 Sato
D633452 March 2011 Namiki et al.
D634719 March 2011 Yasuda et al.
D649126 November 2011 Takahashi
D684551 June 2013 Nguyen
8469776 June 2013 Zuniga
D686175 July 2013 Gurary
D686582 July 2013 Krishnan
D687790 August 2013 Krishnan
D687791 August 2013 Krishnan
D711330 August 2014 Fukushima et al.
8859070 October 2014 Yasuda
D729753 May 2015 Fukushima et al.
2001/0029158 October 2001 Sasaki
2004/0175951 September 2004 Chen
2008/0070479 March 2008 Nabeya
2009/0068934 March 2009 Hong
2009/0068935 March 2009 Torii
2009/0111362 April 2009 Nabeya
2009/0247057 October 2009 Kobayashi
2013/0316628 November 2013 Jang
Foreign Patent Documents
301348233 Sep 2010 CN
301445758 Jan 2011 CN
D 138225 Dec 2010 TW
D 139857 Apr 2011 TW
D 146491 Apr 2012 TW
Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Pearne & Gordon LLP

Description



FIG. 1 is a top perspective view a first embodiment of an elastic membrane for semiconductor wafer polishing apparatus showing our new design;

FIG. 2 is a bottom perspective view thereof;

FIG. 3 is a top plan view thereof;

FIG. 4 is a bottom plan view thereof;

FIG. 5 is a side view thereof, with the apparatus being radially symmetrical about a vertical axis;

FIG. 6 is a cross sectional view taken along section line 6-6 in FIG. 3;

FIG. 7 is an enlarged portion view taken along line 7-7 in FIG. 6;

FIG. 8 is a top perspective view a second embodiment of an elastic membrane for semiconductor wafer polishing apparatus showing our new design;

FIG. 9 is a bottom perspective view thereof;

FIG. 10 is a top plan view thereof;

FIG. 11 is a bottom plan view thereof;

FIG. 12 is a side view thereof, with the apparatus being radially symmetrical about a vertical axis;

FIG. 13 is a cross sectional view taken along section line 13-13 in FIG. 10;

FIG. 14 is an enlarged portion view taken along line 14-14 in FIG. 13;

FIG. 15 is a top perspective view a third embodiment of an elastic membrane for semiconductor wafer polishing apparatus showing our new design;

FIG. 16 is a bottom perspective view thereof;

FIG. 17 is a top plan view thereof;

FIG. 18 is a bottom plan view thereof;

FIG. 19 is a side view thereof, the apparatus being radially symmetrical about a vertical axis;

FIG. 20 is a cross sectional view taken along section line 20-20 in FIG. 17;

FIG. 21 is an enlarged portion view taken along line 21-21 in FIG. 20;

FIG. 22 is a top perspective view a fourth embodiment of an elastic membrane for semiconductor wafer polishing apparatus showing our new design;

FIG. 23 is a bottom perspective view thereof;

FIG. 24 is a top plan view thereof;

FIG. 25 is a bottom plan view thereof;

FIG. 26 is a side view thereof, the apparatus being radially symmetrical about a vertical axis;

FIG. 27 is a cross sectional view taken along line 27-27 in FIG. 24; and,

FIG. 28 is an enlarged portion view taken along line 28-28 in FIG. 27.

The broken lines shown in the drawings represent portions of the elastic membrane for semiconductor wafer polishing apparatus that form no part of the claimed design.

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