Semiconductor device

Description

FIG. 1 is a front, top and right side perspective view of a semiconductor device showing our new design;

FIG. 2 is a rear, top, and left side perspective view thereof;

FIG. 3 is a front elevational view thereof;

FIG. 4 is a rear elevational view thereof;

FIG. 5 is a left side elevational view thereof;

FIG. 6 is a right side elevational view thereof;

FIG. 7 is a top plan view thereof;

FIG. 8 is a bottom plan view thereof;

FIG. 9 is a front, top and right side perspective view thereof, shown in a used condition attached to a mount shown in broken lines; and,

FIG. 10 is another front elevational view thereof, attached to a mount shown in broken lines.

The broken lines shown in the drawings represent portions of the semiconductor device that form no part of the claimed design.

Claims

CLAIM The ornamental design for a semiconductor device, as shown and described.

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Inventors:	Kawase; Tatsuya (Tokyo, JP), Miyamoto; Noboru (Tokyo, JP), Ishihara; Mikio (Tokyo, JP)
Applicant:	Name City State Country Type Mitsubishi Electric Corporation Chiyoda-ku, Tokyo N/A JP
Assignee:	Mitsubishi Electric Corporation (Tokyo, JP)
Appl. No.:	D/503,992
Filed:	October 1, 2014

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Related U.S. Patent Documents

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	Application Number	Filing Date	Patent Number	Issue Date
	29464434	Aug 16, 2013	D719537

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Foreign Application Priority Data

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May 8, 2013 [JP]			2013-010099
May 8, 2013 [JP]			2013-010100
May 8, 2013 [JP]			2013-010101
May 8, 2013 [JP]			2013-010102
May 8, 2013 [JP]			2013-010103
May 8, 2013 [JP]			2013-010104

Current U.S. Class:	D13/182
Current International Class:	1303
Field of Search:	;D13/182

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References Cited [Referenced By]

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Foreign Patent Documents

	1411477		Apr 2011		JP
	1411478		Apr 2011		JP

Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Sughrue Mion, PLLC Turner; Richard C.