Semi-conductor mounting substrate

Description

FIG. 1 is a top perspective view of a semi-conductor mounting substrate showing our new design;

FIG. 2 is a bottom perspective view thereof;

FIG. 3 is a right side elevational view thereof;

FIG. 4 is a left side elevational view thereof;

FIG. 5 is a rear elevational view thereof; and

FIG. 6 is a front elevational view thereof.

Claims

The ornamental design for a semi-conductor mounting substrate, as shown.

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Inventors:	Hasegawa; Terutomi (Ogaki-City, Gifu pref., JP), Goto; Nobumichi (Seki City Gifu Pref, JP)
[*] Notice:	The portion of the term of this patent subsequent to May 14, 2005 has been disclaimed.
Appl. No.:	07/140,433
Filed:	January 4, 1988

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Foreign Application Priority Data

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Jul 4, 1987 [JP]			62-27274

Current U.S. Class:	D13/182
Field of Search:	;D13/12,20,99 ;361/401,403,404,405 ;357/70,72,74,80 ;174/52.4 ;437/209

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References Cited [Referenced By]

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U.S. Patent Documents

4288841	September 1981	Gogal
4338621	July 1982	Braun
4437141	March 1984	Prokop
4458291	July 1984	Yanagisawa et al.
4513355	April 1985	Shroeder et al.
4677526	June 1987	Muehling et al.
4698663	October 1987	Sugimoto et al.

Foreign Patent Documents

	0048945		Mar 1983		JP
	0150353		Jul 1986		JP
	0271863		Dec 1986		JP
	0035653		Feb 1987		JP

Other References

Disc Controller Pictured on p. 190, Electronic Design, 10-16-86. . NCR IC Package Pictured on p. 7, Electronic Design, 10-16-86. . CMOS Chip Pictured on p. 131, Electronics, 8-7-86. . Fujitsu Substrate Pictured on p. 7, Electronics, 2-24-86..

Primary Examiner: Lucas; Susan J.
Assistant Examiner: Sincavage; Joel
Attorney, Agent or Firm: Lorusso & Loud