U.S. patent number D810,706 [Application Number D/580,738] was granted by the patent office on 2018-02-20 for semiconductor module.
This patent grant is currently assigned to Fuji Electric Co., Ltd. The grantee listed for this patent is Fuji Electric Co., Ltd. Invention is credited to Ryo Maruyama, Shin Soyano, Yoshikazu Takamiya, Toru Yamada.
United States Patent |
D810,706 |
Soyano , et al. |
February 20, 2018 |
Semiconductor module
Claims
CLAIM The ornamental design for a semiconductor module, as shown
and described.
Inventors: |
Soyano; Shin (Tokyo,
JP), Takamiya; Yoshikazu (Tokyo, JP),
Yamada; Toru (Tokyo, JP), Maruyama; Ryo (Tokyo,
JP) |
Applicant: |
Name |
City |
State |
Country |
Type |
Fuji Electric Co., Ltd |
Kawasaki-shi, Kanagawa |
N/A |
JP |
|
|
Assignee: |
Fuji Electric Co., Ltd
(Kawasaki-shi, JP)
|
Appl.
No.: |
D/580,738 |
Filed: |
October 12, 2016 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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29531129 |
Jun 23, 2015 |
D772184 |
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Foreign Application Priority Data
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Dec 24, 2014 [JP] |
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D2014-028804 |
Dec 24, 2014 [JP] |
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D2014-028805 |
Dec 24, 2014 [JP] |
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D2014-028806 |
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Current U.S.
Class: |
D13/182 |
Current International
Class: |
1303 |
Field of
Search: |
;D13/182
;257/678,684,690,691
;361/679.01,713,728,736,760,761,772,775,783,820 ;174/250,253
;438/15,25,26,51,55,63,64,106 |
References Cited
[Referenced By]
U.S. Patent Documents
Other References
US. Appl. No. 29/580,736, filed Oct. 12, 2016. cited by
applicant.
|
Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Young Basile Hanlon &
MacFarlane, P.C.
Description
FIG. 1 is a front view of a semiconductor module showing our new
design;
FIG. 2 is a rear view thereof;
FIG. 3 is a left side view thereof;
FIG. 4 is a right side view thereof;
FIG. 5 is a top view thereof;
FIG. 6 is a bottom view thereof;
FIG. 7 is a front, right, and bottom perspective view thereof;
FIG. 8 is a rear, left and top perspective view thereof; and,
FIG. 9 is a cross sectional view taken along line 9-9 of FIG.
1.
The ornamental design of the present disclosure is a semiconductor
module on which power semiconductor elements and the like may be
mounted. Plate shaped terminals are provided on the left side and
right side. A plurality of post shaped pins extend from a rear
surface. The cross-sections of the post shaped pins are rhombic. A
hole penetrates from a front surface to the rear surface at each of
four corners of the semiconductor module.
* * * * *