U.S. patent application number 13/366067 was filed with the patent office on 2012-05-31 for method for manufacturing a semiconductor structure, and a corresponding semiconductor structure.
Invention is credited to Simon Armbruster, Hubert Benzel, Paul Farber, Ando Feyh, Matthias Illing, Silvia Kronmueller, Franz Laermer, Gerhard Lammel, Ralf Reichenbach, Christoph Schelling.
Application Number | 20120132925 13/366067 |
Document ID | / |
Family ID | 37983457 |
Filed Date | 2012-05-31 |
United States Patent
Application |
20120132925 |
Kind Code |
A1 |
Lammel; Gerhard ; et
al. |
May 31, 2012 |
METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE, AND A
CORRESPONDING SEMICONDUCTOR STRUCTURE
Abstract
A method for manufacturing a semiconductor structure is provided
which includes the following steps: a crystalline semiconductor
substrate (1) is supplied; a porous region (10) is provided
adjacent to a surface (OF) of the semiconductor substrate (1); a
dopant (12) is introduced into the porous region (10) from the
surface (OF); and the porous region (10) is thermally
recrystallized into a crystalline doping region (10') of the
semiconductor substrate (1) whose doping type and/or doping
concentration and/or doping distribution are/is different from
those or that of the semiconductor substrate (1). A corresponding
semiconductor structure is likewise provided.
Inventors: |
Lammel; Gerhard; (Tuebingen,
DE) ; Benzel; Hubert; (Pliezhausen, DE) ;
Illing; Matthias; (Palo Alto, CA) ; Laermer;
Franz; (Weil Der Stadt, DE) ; Kronmueller;
Silvia; (Schwaikheim, DE) ; Farber; Paul;
(Stuttgart, DE) ; Armbruster; Simon; (Gomaringen,
DE) ; Reichenbach; Ralf; (Esslingen, DE) ;
Schelling; Christoph; (Stuttgart, DE) ; Feyh;
Ando; (Tamm, DE) |
Family ID: |
37983457 |
Appl. No.: |
13/366067 |
Filed: |
February 3, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12282842 |
Mar 2, 2009 |
8148234 |
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PCT/EP2007/052227 |
Mar 9, 2007 |
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13366067 |
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Current U.S.
Class: |
257/77 ;
257/E29.104 |
Current CPC
Class: |
H01L 21/02378 20130101;
H01L 21/324 20130101; H01L 21/223 20130101; H01L 21/02381 20130101;
H01L 21/02532 20130101; H01L 21/225 20130101; H01L 21/02658
20130101; H01L 21/02667 20130101; H01L 21/228 20130101 |
Class at
Publication: |
257/77 ;
257/E29.104 |
International
Class: |
H01L 29/24 20060101
H01L029/24 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 21, 2006 |
DE |
102006012857.5 |
Claims
1-11. (canceled)
12. A semiconductor structure, comprising: a crystalline
semiconductor substrate; and a crystalline doping region in the
form of a trough adjacent to a surface of the semiconductor
substrate, wherein at least one of a doping type, a doping
concentration, and a doping distribution of the crystalline doping
region is different from that of the semiconductor substrate, and
wherein the doping distribution is substantially homogeneous across
an entire depth of the doping region.
13. The semiconductor structure of claim 12, wherein the
semiconductor substrate is made of at least one of silicon and
silicon carbide.
14. The semiconductor structure of claim 13, wherein a dopant is
distributed throughout an entire volume of the crystalline doping
region.
15. The semiconductor structure of claim 13, wherein the doping
region is saturated.
16. The semiconductor structure of claim 13, wherein the doping
region is monocrystalline.
17. The semiconductor structure of claim 12, wherein a depth of the
crystalline doping region is at least 50 .mu.m from the
surface.
18. The semiconductor structure of claim 17, wherein the
semiconductor substrate is made of at least one of silicon and
silicon carbide.
19. The semiconductor structure of claim 17, wherein a dopant is
distributed throughout an entire volume of the crystalline doping
region.
20. The semiconductor structure of claim 17, wherein the doping
region is saturated.
21. The semiconductor structure of claim 17, wherein the doping
region is monocrystalline.
22. The semiconductor structure of claim 12, wherein a dopant is
distributed throughout an entire volume of the crystalline doping
region.
23. The semiconductor structure of claim 12, wherein the doping
region is saturated.
24. The semiconductor structure of claim 12, wherein the doping
region is monocrystalline.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a divisional application of U.S.
patent application Ser. No. 12/282,842 filed on Mar. 2, 2009, which
is a national phase application based on international application
PCT/EP2007/052227 filed on Mar. 9, 2007, and claims priority to
German Patent Application No. DE 10 2006 012 857.5, filed on Mar.
21, 2006, all of which are hereby incorporated by reference in
their entireties.
BACKGROUND INFORMATION
[0002] The present invention relates to a method for manufacturing
a semiconductor structure, and a corresponding semiconductor
structure.
[0003] In the broader sense, the present invention relates to a
modification in the material properties of a semiconductor
substrate made, for example, of silicon or silicon carbide,
beginning from a surface of the semiconductor substrate.
Modifications of this type may involve, for example, the setting of
a certain conductivity or conductivity type (p or n doping).
[0004] Although it is applicable, in principle, to numerous other
micromechanical or microelectronic semiconductor structures, the
present invention and its underlying object are explained on the
basis of micromechanical pressure sensors.
[0005] FIG. 3 shows a schematic cross-sectional view of a known
semiconductor structure. In FIG. 3, reference numeral 1 designates
a semiconductor substrate made of silicon, for example of the
p-type, and reference numeral 5 designates a doping region on
surface OF of semiconductor substrate 1, for example of the n-type,
which has a depth t' of 10 .mu.m.
[0006] Doping regions 5 of this type are usually achieved by
diffusing foreign atoms into semiconductor substrate 1 from surface
OF. In the case of a silicon semiconductor substrate 1, a source of
dopants is deposited for this purpose onto the wafer surface (e.g.,
phosphorus glass for p doping or boron glass for n doping) and
subsequently thermally driven in at a high temperature, i.e., the
dopants are excited for the purpose of diffusion into silicon
substrate 1 from surface OF. Alternatively, the dopants are also
implantable into the wafer surface in a layer having an original
thickness of typically 1 .mu.m to 2 .mu.m, this layer being
subsequently thermally diffused deeper into silicon semiconductor
substrate 1.
[0007] Diffusion processes of this type are generally limited to a
relatively thin layer thickness from surface OF of semiconductor
substrate 1, since foreign substances such as dopant atoms diffuse
only slowly into silicon, even at very high temperatures, and
therefore in practice are able to achieve depths of only typically
20 .mu.m to 25 .mu.m in silicon, at least within economically
justifiable diffusion times. Foreign atoms, such as antimony (Sb)
or germanium (Ge), etc., exist which diffuse only extraordinarily
slowly, due to their large atom diameter, so that not even the
specified limit of typically 20 .mu.m to 25 .mu.m in silicon is
achievable using these foreign atoms, but instead the diffusion
depths within justifiable times remain substantially below this
level. In the case of silicon carbide, a complicating factor is
that diffusion itself takes place extremely slowly even at very
high temperatures of 1,400.degree. C. The silicon carbide lattice
is a substantial diffusion barrier, which greatly blocks a
penetration of foreign atoms and limits diffusion processes to a
penetration depth of just a few micrometers.
[0008] In micromechanical applications, in particular, however,
thicker layers of, for example, silicon or silicon carbide having
modified layer properties, for example a modified conductivity
type, are frequently required, so that the aforementioned limits of
thermal diffusion processes in the bulk material are problematic.
Examples may include thick monocrystalline, n-type silicon layers
having a thickness of, for example, 100 .mu.m to 200 .mu.m on a
p-type semiconductor substrate, such as those advantageously used
for high-pressure sensors in silicon in connection with an
electrochemical etch stop from p-type to n-type silicon. This also
applies to the manufacture of thick silicon bending beam structures
using an electrochemical etch stop from the back and, in plasma
trench techniques, from the front, as well as to the manufacture of
thin silicon films having a thickness of 100 .mu.m to 200 .mu.m and
desired doping by electrochemical etching or anodizing up to a p-n
junction. The same applies to silicon carbide in the case of
media-resistant, high-temperature-compatible sensors as well as the
manufacture of silicon carbide films using known smart cut methods
via doping-selective electrochemical anodizing or etching
methods.
[0009] Methods for manufacturing porous regions in silicon
semiconductor substrates are known from DE 100 32 579 A1 and DE 10
2004 036 032 A1.
[0010] The object of the present invention, therefore, is to
provide a method for manufacturing a semiconductor structure and a
corresponding semiconductor structure which, from the
process-engineering point of view, enable simple manufacturing of
deep doping regions in a semiconductor substrate.
SUMMARY OF THE INVENTION
[0011] The method according to the present invention for
manufacturing a semiconductor structure according to Claim 1 and
the corresponding semiconductor structure according to Claim 11
have the advantage that they enable the manufacture of thick layers
of crystalline semiconductor material having modified properties by
introducing foreign atoms or foreign substances. Alternatively, the
layers may also be given a polycrystalline structure. On the one
hand, modified layers may thus be manufactured in a thickness which
would otherwise not be economical to manufacture in such a great
layer thickness. On the other hand, foreign atoms are introducible
which diffuse only very slowly and therefore may not be introduced
in a practical manner into layers, for example antimony or
germanium or other atoms having a large atom radius.
[0012] Modified layers may also be manufactured, for example in
silicon carbide, where the diffusion-inhibiting base material SiC
would otherwise make layer modification impossible or nearly
impossible. It is therefore possible to modify materials in this
manner across great layer thicknesses which would otherwise not be
modifiable or dopable using methods according to the related art,
due to their material properties.
[0013] In addition, the method described above may be used to
achieve entirely new material properties by introducing large
quantities of foreign atoms, which would otherwise not be
introducible in such high doses.
[0014] The subclaims describe advantageous refinements of and
improvements on the particular subject matter of the present
invention.
[0015] The idea underlying the present invention is to create a
porous region adjacent to a surface of a semiconductor substrate,
in which a dopant may be introduced, after which the porous region
is thermally recrystallized.
[0016] To provide the porous region, the method suitably uses
electrochemical anodizing. For example, porous silicon or porous
silicon carbide is nanoporously or mesoporously producible by
selecting corresponding anodizing conditions, essentially current
density and hydrofluoric acid concentration.
[0017] Using electrochemical anodizing, it is possible to
unproblematically manufacture thick porous layers having a vertical
dimension of, for example, 100 .mu.m to 300 .mu.m. This skeleton of
nanoscale or mesoscale silicon or silicon carbide may subsequently
be provided with foreign atoms in full thickness.
[0018] For this purpose, the dopants may be supplied in the form of
a carrier gas (e.g., boroethane, arsine, phosphine, etc.), which
penetrates the structure. Alternatively, a glass such as boron
glass or phosphorus glass may be deposited on the surface or a
precursor dissolved in liquid may be used to saturate the porous
structure. Organic and anorganic compounds of boron, phosphorus
(e.g., trimethylphosphite, phosphorus pentaxyde), arsenic (vinyl
arsine), antimony, germanium (tetraethyl germanium), aluminum,
iron, lead, etc., or their soluble salts (e.g., chlorides, iodides,
bromides, etc.), which are soluble in liquids having a low surface
tension, such as alcohols or water or alcohol/water mixtures or
other organic solvents, may be used as the precursor. In a
preferred specific embodiment, the dopants are supplied in the form
of a carrier gas, the gas homogeneously penetrating the porous
region at a high temperature of, for example, 900.degree. C., and
the foreign atoms simultaneously diffusing from the gas phase into
the nanostructure. In this exemplary embodiment, the thermal
treatment for deposition and the thermal treatment for driving in
the dopant occur at the same time.
[0019] It is particularly advantageous to dissolve doping atoms in
supercritical CO.sub.2, since this substance has no surface tension
and therefore is able to particularly easily penetrate and
functionalize nanostructures or mesostructures, i.e., coat them
with foreign atoms. It may be suitable to add so-called co-solvents
to supercritical CO.sub.2 for the purpose of using solvatization to
dissolve foreign substances which do not easily dissolve in
CO.sub.2. As mentioned above, the advantage of the supercritical
state is the fact that every point in the depth of the porous
material is effortlessly reachable, and the foreign substances may
be transported and deposited everywhere in approximately the same
concentration. In the preferred specific embodiment, the porous
region may be saturated using a solution of foreign atoms in a
liquid, in particular in supercritical CO.sub.2, at room
temperature, whereupon a temperature step immediately takes place
at 900.degree. C. for driving in and a further temperature step at
950.degree. C. for recrystallization and driving in.
[0020] The step for thermally driving in the foreign atoms is
preferably carried out separately at a temperature at which
structural rearrangement is not yet able to take place. At a
temperature of, for example, 900.degree. C., foreign atoms diffuse
into the delicate nanostructures throughout the entire volume of
the porous structure in silicon and penetrate these structures
nearly homogeneously. The stability of the nanostructure is
additionally supported by the fact that natural oxides on the
structure surface additionally stabilize the latter and prevent
thermal rearrangement. In the case of silicon, such oxides decay
only at temperatures above 950.degree. C. and, in the case of
silicon carbide, only above 1,200.degree. C.
[0021] In the recrystallization step, the porous region is
thermally collapsed at high temperatures, for example above
950.degree. C. in the case of silicon and above 1,200.degree. C. in
the case of silicon carbide, a solid monocrystalline layer in the
sense of bulk material resulting by rearranging the silicon atoms
or silicon carbide. Initially, this rearrangement was still
undesirable for enabling the foreign atoms to reach all parts of
the nanostructure and for avoiding damage to individual regions of
the structure. At these elevated temperatures, the native oxide
layers supporting the nanostructure are now evaporated, which may
be additionally supported by adding hydrogen gas. Without the
stabilization via the surface oxides, the thermal rearrangement of
the structure may begin quickly and continue until the structure is
completely compressed into a monocrystalline material. This makes
it possible to have foreign atoms penetrate thick layers of silicon
or silicon carbide in a controlled manner, in what is on the whole
an economical overall process using electrochemical anodizing in
connection with one or more relatively short high-temperature
steps.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Exemplary embodiments of the present invention are
illustrated in the drawings and explained in greater detail in the
following description.
[0023] FIGS. 1a through d show schematic cross-sectional views of
the essential manufacturing steps of a method for manufacturing a
semiconductor structure according to a specific embodiment of the
present invention.
[0024] FIG. 2 shows a flow chart for explaining the sequence of the
essential manufacturing steps of the method for manufacturing a
semiconductor structure according to the specific embodiment of the
present invention.
[0025] FIG. 3 shows a schematic cross-sectional view of a known
semiconductor structure. essential manufacturing steps of a method
for manufacturing a semiconductor structure according to a specific
embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0026] In the figures, the same reference numerals designate
identical or functionally identical components.
[0027] FIGS. 1a through d show schematic cross-sectional views of
the essential manufacturing steps of a method for manufacturing a
semiconductor structure according to a specific embodiment of the
present invention, and FIG. 2 shows a flow chart for explaining the
sequence of the essential manufacturing steps of the method for
manufacturing a semiconductor structure according to the specific
embodiment of the present invention.
[0028] In FIG. 1a, reference numeral 1 designates a silicon
semiconductor substrate of the p type having a surface OF.
[0029] According to FIG. 1b, a mask 2 made of silicon nitride is
applied to surface OF (Step S1), and a nanoporous region 10 having
a depth t of 100 .mu.m is subsequently introduced by
electrochemical anodizing (Step S2), this region having a network
of pores 10a which form an interconnected skeleton.
[0030] In a subsequent process step S3, which is illustrated in
FIG. 1c, a glass 12, for example phosphorus glass, is first
introduced into porous region 10 at a temperature of 900.degree.
C., a diffusion of the phosphorus into the skeleton made of
nanoscale silicon simultaneously taking place directly at this
temperature and the phosphorous thus homogeneously penetrating
therein. With reference to FIG. 1d, a temperature step S4 then
takes place at a temperature of more than 950.degree. C.,
rearrangement of the silicon atoms thus resulting in a thermal
recrystallization of porous region 10 into a crystalline doping
region 10' of semiconductor substrate 1, whose doping type, doping
concentration and doping distribution are different from those of
semiconductor substrate 1.
[0031] Although the present invention was described on the basis of
a preferred exemplary embodiment, it is not limited thereto.
[0032] As an alternative to the above exemplary embodiment, the
dopants may be introduced either in the form of a carrier gas or in
the form of a liquid solution which penetrates the porous
structure.
[0033] Although the semiconductor structure in the above example
was formed using the mask made of silicon nitride, it is also
possible to provide an edge doping in the semiconductor substrate
which surrounds the region to be made porous on the sides and
serves as an etch mask. A doping onto the back of the substrate may
also be provided for the anodic process.
[0034] The application stated in the above example for a
micromechanical pressure sensor is provided purely by way of
example and may be modified in any manner.
* * * * *