U.S. patent application number 11/242221 was filed with the patent office on 2006-02-09 for silicon chip carrier with conductive through-vias and method for fabricating same.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to Paul Stephen Andry, Leena Paivikki Buchwalter, Jon Alfred Casey, Yu-Ting Cheng, Daniel Charles Edelstein, Sherif A. Goma, Raymond R. Horton, Gareth Geoffrey Hougham, Michael Wayne Lane, Xiao Hu Liu, Robert K. Montoye, Kenneth Blair Ocheltree, Chirag Suryakant Patel, Edmund Juris Sprogis, Michelle Leigh Steen, Brian Richard Sundlof, Cornelia K. Tsang, George Frederick Walker.
Application Number | 20060027934 11/242221 |
Document ID | / |
Family ID | 34633899 |
Filed Date | 2006-02-09 |
United States Patent
Application |
20060027934 |
Kind Code |
A1 |
Edelstein; Daniel Charles ;
et al. |
February 9, 2006 |
Silicon chip carrier with conductive through-vias and method for
fabricating same
Abstract
A carrier structure and method for fabricating a carrier
structure with through-vias each having a conductive structure with
an effective coefficient of thermal expansion which is less than or
closely matched to that of the substrate, and having an effective
elastic modulus value which is less than or closely matches that of
the substrate. The conductive structure may include concentric via
fill areas having differing materials disposed concentrically
therein, a core of the substrate material surrounded by an annular
ring of conductive material, a core of CTE-matched non-conductive
material surrounded by an annular ring of conductive material, a
conductive via having an inner void with low CTE, or a full fill of
a conductive composite material such as a metal-ceramic paste which
has been sintered or fused.
Inventors: |
Edelstein; Daniel Charles;
(White Plains, NY) ; Andry; Paul Stephen;
(Yorktown Heights, NY) ; Buchwalter; Leena Paivikki;
(Hopewell Junction, NY) ; Casey; Jon Alfred;
(Poughkeepsie, NY) ; Goma; Sherif A.; (Hawthorne,
NY) ; Horton; Raymond R.; (Dover Plains, NY) ;
Hougham; Gareth Geoffrey; (Ossining, NY) ; Lane;
Michael Wayne; (Cortlandt Manor, NY) ; Liu; Xiao
Hu; (Briarcliff Manor, NY) ; Patel; Chirag
Suryakant; (Peekekill, NY) ; Sprogis; Edmund
Juris; (Underhill, VT) ; Steen; Michelle Leigh;
(Danbury, CT) ; Sundlof; Brian Richard; (Verbank,
NY) ; Tsang; Cornelia K.; (Mohegan Lake, NY) ;
Walker; George Frederick; (New York, NY) ; Cheng;
Yu-Ting; (Hsinchu City, TW) ; Ocheltree; Kenneth
Blair; (Ossining, NY) ; Montoye; Robert K.;
(Austin, TX) |
Correspondence
Address: |
NELSON "JACK" STORM;APARTMENT #10
HUBBARD TRAIL
ROSSVILLE
IL
60963
US
|
Assignee: |
International Business Machines
Corporation
|
Family ID: |
34633899 |
Appl. No.: |
11/242221 |
Filed: |
October 3, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10729254 |
Dec 5, 2003 |
|
|
|
11242221 |
Oct 3, 2005 |
|
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|
Current U.S.
Class: |
257/774 ;
257/E21.597; 257/E23.067; 257/E23.075 |
Current CPC
Class: |
H01L 2924/3011 20130101;
H01L 2924/01078 20130101; H01L 2924/15311 20130101; H01L 2924/01019
20130101; H01L 23/49883 20130101; H01L 2224/16 20130101; H01L
2924/01079 20130101; H01L 2924/3025 20130101; H01L 2924/01004
20130101; H01L 23/49827 20130101; H01L 21/486 20130101; H01L
2924/10253 20130101; H01L 2924/00 20130101; H01L 2924/01322
20130101; H01L 2924/09701 20130101; H01L 2924/10253 20130101; H01L
21/76898 20130101 |
Class at
Publication: |
257/774 |
International
Class: |
H01L 23/48 20060101
H01L023/48 |
Claims
1. A semiconductor carrier structure comprising: a semiconductor
substrate comprising a substrate material having a first
coefficient of thermal expansion and a first elastic modulus; at
least one through-via in said semiconductor substrate, wherein each
of said through-vias is filled with a conductive structure having a
second coefficient of thermal expansion which is less than or
substantially the same as the first coefficient of thermal
expansion and a second elastic modulus which is less than or equal
to the first elastic modulus.
2. The semiconductor carrier structure of claim 1 wherein said
conductive structure comprises a metal-ceramic composite.
3. The semiconductor carrier structure of claim 2 wherein said
metal-ceramic composite comprises a metallic conductive material
with a CTE-matched ceramic.
4. The semiconductor carrier structure of claim 3 wherein said
CTE-matched ceramic is selected from the group consisting of
cordierite, silicate-based glasses, glass ceramic, alumina,
mullite, fosterite, sapphire.
5. The semiconductor carrier structure of claim 2 wherein said
metal ceramic composite is formed from a metallic coated powder
suspension.
6. The semiconductor carrier structure of claim 5 wherein said
metallic coated powder suspension is selected from the group
consisting of borosilicate glasses, CSVP, Cu-coated W, Ta, SiC,
SiO2, Ni/Ti alloy, Si, zirconium-tungsten oxide, silver coated W,
Au coated W, Au coated over copper shell over W core, Au/Ti/Cu/W,
Au/Cr/Ni/W, Au/Ti/Ni/Mo, Au/Ti/Cu/Si, and Au/Cr/Cu/ZrW2O8.
7. The semiconductor carrier structure of claim 1 wherein said each
conductive structure comprises a first conductive via material
disposed in annular shape along the sidewalls of said through-via
and having a core structure comprising a second via material.
8. The semiconductor carrier structure of claim 7 wherein said
second via material comprises an insulating material.
9. The semiconductor carrier structure of claim 7 wherein said
second via material comprises a conducting material.
10. The semiconductor carrier structure of claim 7 wherein said
second via material comprises said substrate material.
11. The semiconductor carrier structure of claim 7 wherein said
second via material is selected from the group consisting of
polyimide, thermid, KJ, photosensitive polyimide, SiLK, or other
high-temperature polymer.
12. The semiconductor carrier structure of claim 7 wherein said
second via material comprises a material having a third coefficient
of thermal expansion which is less than or about equal to said
first coefficient of thermal expansion.
13. The semiconductor carrier structure of claim 7 wherein said
second via material comprises silicate glass.
14. The semiconductor carrier structure of claim 7 wherein said
second via material comprises of silica or a silicate glass-filled
high temperature polymer.
15. The semiconductor carrier structure of claim 7 wherein said
second via material comprises a sealed void filled with vacuum or a
gas.
16. The semiconductor carrier structure of claim 2 wherein said
substrate material is selected from the group consisting of
silicon, silicate glass, alumina, mullite, fosterite, sapphire,
gallium arsenide, gallium phosphide, aluminum nitride, glass
ceramic, silicon carbide, beryllium oxide, or a glass
fiber-impregnated high temperature polymer.
17. The semiconductor carrier structure of claim 1 wherein said
conductive structure compress a low CTE metal-core metal
powder.
18. The semiconductor carrier structure of claim 1 wherein said
conductive structure comprises a low CTE insulating-core, metal
coated powder.
19. The semiconductor carrier structure of claim 1 wherein said
conductive structure comprises a mixture of particles having
different core and shell materials.
20. The semiconductor carrier structure of claim 1 wherein the top
surface of said conductive structure comprises one of an
impermeable solid metal or an insulating cap.
21. The semiconductor carrier structure of claim 20 where said
insulating cap includes a spin-applied high-temperature polymer
core.
22. The semiconductor carrier structure of claim 20 where the
insulating cap includes a lamination of high temperature polymer
film.
23. The semiconductor carrier structure of claim 1 further
comprising an insulating layer disposed along the sidewalls of each
of said through-vias between said substrate and said conductive
structure.
24. The semiconductor carrier structure of claim 1 further
comprising an insulating layer on the bottom surface of the
substrate adjacent to said at least one through-via.
25. The semiconductor carrier structure of claim 1 wherein said
second coefficient of thermal expansion is less than about 8
ppm/.degree. C., and wherein said second elastic modulus is less
than or equal to 170 GPa.
26. A method for fabricating a semiconductor carrier structure in a
semiconductor substrate comprising substrate material having a
first coefficient of thermal expansion and first elastic modulus
comprising the steps of: etching a plurality of blind via holes
from the top surface of said semiconductor substrate to a depth
which is less than the thickness of said semiconductor substrate;
providing an insulating layer on the exposed surfaces of said blind
via holes; creating a conductive structure in each of said
plurality of blind via holes, said conductive structure having a
second coefficient of thermal expansion which is less than or
substantially the same as said first coefficient of thermal
expansion and a second elastic modulus which is less than or equal
to the first elastic modulus.
27. The method of claim 26 further comprising creating at least one
of integrated circuits, wiring, and components on at least one of
the top and the bottom surface.
28. The method of claim 26 further comprising electrically
contacting said integrated circuit, wiring, or components to said
through-vias.
29. The method of claim 26 further comprising exposing the bottom
of each of said conductive structures by removing substrate
material from the bottom of said substrate structure and removing
said insulating layer at the bottom of said blind via holes.
30. The method of claim 26 wherein etching of vias is a high-rate
process which includes alternating etching and deposition steps
performed with substrate temperatures between 0.degree. C. and
-100.degree. C. and more preferably -50.degree. C.
31. The method of claim 29 whereby said exposing comprises a
mechanical backside grind and polish process.
32. The method of claim 29 wherein said exposing comprises the
steps of: removing the bulk of the backside silicon by grinding and
polishing; and recessing the silicon surface below the via bottoms
by selective wet etching.
34. The method of claim 33 further comprising passivating the
exposed silicon by conformal insulator deposition.
35. The method of claim 34 further comprising exposing the
conductive surface of the via bottom by CMP.
36. The method of claim 26 further comprising planarizing the top
of said semiconductor carrier structure to remove any conductive
material disposed on the top surface of the substrate.
37. The method of claim 26 wherein said creating a conductive
structure comprises disposing metal-ceramic in said
through-vias.
38. The method of claim 37 wherein said disposing metal-ceramic
comprises the steps of: filling said blind via holes with a highly
loaded metal-ceramic suspension/paste; and heating said structure
to provide continuous conductive networks and impart mechanical
integrity.
39. The method of claim 26 wherein said substrate is silicon and
wherein said providing of an insulating layer comprises exposing
said substrate to passivating to provide insulating material along
the sidewalls of each of said through-vias between said substrate
and said conductive structure.
40. The method of claim 26 wherein said creating a conductive
structure comprises the steps of: providing a core structure
comprising an inner via material; and disposing a conductive via
material in annular shape about said core structure.
41. The method of claim 26 wherein said creating a conductive
structure comprises the steps of: disposing a first conductive via
material in annular shape over said insulated layer, to provide an
annular conductive ring with a remaining inner via volume; and
filling said remaining inner via volume with a second via material
having a coefficient of thermal expansion which is less than said
first coefficient of thermal expansion.
42. The method of claim 26 wherein said etching comprises etching
an annular ring for said blind vias to provide a core structure of
said substrate material and wherein said creating a conductive
structure comprises disposing conductive material in said annular
ring.
43. The method of claim 26 wherein creating a conductive structure
comprises the steps of: disposing a conductive via material in
annular shape along the insulated surfaces of each of said blind
via holes; and burnishing conductive via surface material at the
surface of said blind via holes in conductive contact with said
conductive via material, whereby air/gas/vacuum/ambient is sealed
within said via hole.
44. The semiconductor carrier structure of claim 1 comprising a
plurality of through-vias and further comprising wiring disposed on
at least one of the too and bottom surface of said substrate, said
wiring electrically interconnecting said plurality of
through-vias.
45. The semiconductor carrier structure of claim 44 further
comprising a conductive edge connector located at one end of said
substrate and being in electrical contact with said wiring.
46. The method of claim 29 further comprising depositing wiring on
at least one of the top and bottom surfaces of said substrate in
electrical contact with the conductive structure in each of said
plurality of via holes.
47. The method of claim 46 further comprising providing an edge
connector at one end of said substrate in electrical connection
with said wiring.
48. A ultrahigh density semiconductor package comprising: a
semiconductor substrate, having a first coefficient of thermal
expansion and a first elastic modulus, said semiconductor substrate
comprising: a plurality of through-via wherein each of said
through-vias is filled with a conductive structure having a second
coefficient of thermal expansion which is less than or
substantially the same as the first coefficient of thermal
expansion and a second elastic modulus which is less than or equal
to the first elastic modulus; interconnect wiring disposed on at
least one of the top and bottom surface of said substrate in
electrical connection to said plurality of through-vias; and an
edge connector provided at one end of said substrate in electrical
contact with said wiring.
49. The ultrahigh density package of claim 48 further comprising a
plurality of devices, each device being mounted on at least one of
the top and bottom of said substrate and being connected to some of
said plurality of through-vias.
50. The ultrahigh density package of claim 49 further comprising at
least one thermally conductive material in thermal contact with at
least one of said plurality of devices.
51. The ultrahigh density package of claim 49 further comprising at
least one insulative material disposed about said semiconductor
substrate and said plurality of devices.
52. An ultrahigh density computing node comprising a plurality of
ultrahigh density semiconductor packages, each ultrahigh density
package comprising: a semiconductor substrate, having a first
coefficient of thermal expansion and a first elastic modulus, said
semiconductor substrate comprising: a plurality of through-via
wherein each of said through-vias is filled with a conductive
structure having a second coefficient of thermal expansion which is
less than or substantially the same as the first coefficient of
thermal expansion and a second elastic modulus which is less than
or equal to the first elastic modulus; interconnect wiring disposed
on at least one of the top and bottom surface of said substrate in
electrical connection to said plurality of through-vias; and an
edge connector provided at one end of said substrate in electrical
contact with said wiring; and an electrical connector for
connecting all of said plurality of ultrahigh density packages to a
power source.
53. The computing node of claim 52 further comprising a composite
heat sink structure.
54. The computing node of claim 53 wherein said composite heat sink
structure comprising a plurality of heat spreaders each disposed in
thermal contact with at least one device.
Description
FIELD OF THE INVENTION
[0001] The invention relates generally to a carrier for mounting
and packaging multiple integrated circuit chips; and, more
particularly, to a self-supporting semiconductor or insulator
carrier substrate with conductive through-vias.
BACKGROUND OF THE INVENTION
[0002] A carrier for integrated circuit devices is typically
fabricated of semiconductor, glass, or glass-ceramic material as a
freestanding substrate, chip or wafer having conductive
through-vias. The through-vias are exposed on the top and underside
of the carrier and are insulated from each other. Multiple levels
of carrier material with metallic or semi-metallic vias are often
required to obtain the necessary conductive paths between chips and
other devices mounted with respect to the carrier. The carrier
having through-vias provides chip input/output terminals (I/O),
with the chips typically mounted in the "flip chip" manner, and
other device I/O through the carrier from the surface at which the
chip or device is mounted to the other side of the carrier, which
may include a next level of packaging, a board, or additional
flip-chips mounted on that side of the carrier.
[0003] FIG. 1 provides a representative illustration of a carrier
in accordance with this invention. Carrier 102 comprises a layer
104 of insulative or semiconductive material, for example silicon,
fused silica ("glass", "quartz"), ceramic, or another semiconductor
or insulator. The carrier 102 has multiple through-vias, shown as
105 representatively, which extend from the upper or top surface of
the carrier layer 104 to the bottom surface of the carrier layer
104. The through-vias are filled with a metallic or semi-metallic
conductive via material, shown as conductor 115, to provide
conductive paths through the carrier. Solder bumps, C4s, or the
like, shown as 114, are disposed at the bottom surface of carrier
layer 104 in electrical contact with the conductive via material
115 in order to join the carrier to a next level. At the upper
surface of carrier layer 104, the conductive material 115 in the
through-vias may be placed in electrical contact with additional
multilevel wiring, integrated circuits or associated devices,
optical or optoelectronic elements, microelectromechanical
elements, etc. disposed in layers 106 which are, in turn, connected
to the chip connectors, shown as microjoints 125, of chip 120.
Semiconductor devices may also be embedded in the substrate and
electrically incorporated into the aforementioned integrated
circuits. Should additional multilevel wiring not be needed, the
microjoints of chip 120 can be bonded directly to the conductive
via material 115.
[0004] Problems have arisen in carriers of the prior art due to
limitations in materials, deposition methods, control of
dimensional tolerances, and mechanical stresses encountered during
processing of the materials. Traditional substrate thicknesses are
in the range of 0.5 mm to 20 mm with through-via aspect ratios in
the range of 1:1 to 2:1. Through-vias may be tapered or vertical as
dictated by the forming technology. For instance, vias formed by a
punch technique display a breakout region and laser vias can be
tapered depending upon the aspect ratio. Typical pitches may be 225
.mu.m for glass ceramic or plastic substrates at the present, and
150 .mu.m for ceramic substrates. Depending upon the desired via
density, given the number of chips or other devices to be joined to
the carrier and the number of desired bonding sites, the via
diameters would accordingly range from 25 to 300 .mu.m.
[0005] There is a need to miniaturize such carriers to accommodate
single or multiple flip-chips and micro-components with I/O
densities of from 1,000 to 10,000 per cm.sup.2, with overall
physical dimensions being in the single cm range for length and
width and in the range of a single .mu.m to a few 100 .mu.ms in
thickness. For high speed and low power, the through-vias and
associated connections must present series resistances lower than
several 100 m.OMEGA.s to several tens of m.OMEGA.s, or else signal
risetimes will be degraded. This in turn specifies that
through-vias filled with typical conductive materials be of a
height in the range of a single .mu.m to several hundred .mu.ms
with diameters of several 10's to .about.100 .mu.m.
[0006] As computing performance continues to improve, geometrically
by Moore's Law, at the same time as physical limits to
semiconductor device scaling impede continued improvements of the
integrated device, increasingly higher levels of system integration
are needed. Just as multiple transistors and circuits are
integrated in a monolithic manner for LSI, VLSI, and USLI, it is
desirable to integrate entire computer system blocks on single
chips, for so-called "System-on-a-Chip" (SOC). For example,
multiple CPU cores plus multiple levels of cache memory are now
integrated within a single multiprocessor chip, along with off-chip
memory and other logic units. As SOC integration density demands
increase and speed continues to increase, power densities become
untenable. Current packaging technologies are limited in
interconnect density, I/O density, interconnect bandwidth, and
chip-to-chip spacing required to reach the ultrahigh performance
levels needed, including greater than 10 GHz chip-to-chip
communications with full memory bandwidth for >1000 I/Os per
chip-to-chip edge interconnection. Finally, there is a need for
ultrahigh speed discrete devices and passive components such as
massive decoupling capacitors to address noise and other issues
that are on-chip. It is not possible for current off-chip devices
to respond at the on-chip frequencies needed, due to excessive
distances from the chip, high parasitic impedance, and slow
characteristics of the devices themselves. A carrier package with
conductive through-vias, enabling connection of devices on both
sides of the package, would allow the desired device densities.
[0007] Filling high aspect ratio vias, with a height in the range
of a single .mu.m to several hundred .mu.ms with diameters of
several 10's to .about.100 .mu.m, to provide packages with
through-vias, is challenging. A popular technique for filling blind
vias or through-vias of micro-scale diameters is electroplating of
Cu. However, the hydrodynamics, the ionic concentrations, and the
diffusivities limit the filling of deep blind holes. Authors
Tomisaka et al. (ECTC 2002) did extensive plating optimization and
were still not able to eliminate voids in vias of only 70 .mu.m
deep. Methods for filling large blind holes which are to be opened
later break down or become impractical at such dimensions. The U.S.
Pat. No. 5,998,292 of Black, et al details a method for creating
insulated conductive through-holes in a semiconductor wafer for
3-dimensional wafer joining. Black's method involves etching
so-called blind holes only partially through the semiconductor
substrate, insulating the holes' sidewalls, filling the insulated
holes with metal selected from tungsten, chromium, copper,
aluminum, nickel, indium, gold, and mixtures or alloys thereof,
planarizing the top surface and removing excess metal, and then
grinding away the bottom semiconductor material to expose the
bottom of the filled vias (i.e., to open the blind holes). U.S.
Pat. Nos. 5,646,067 and 5,814,889 and 5,618,752 of Gaul use the
Black approach applied to a silicon carrier layer with tungsten or
polysilicon through vias. Chiu et al. (U.S. Pat. No. 6,593,644)
describe a similar process to create a Si-based chip carrier, with
through-vias filled by Cu, Ni, or Al. The Black method provides
adequate fill of the through-vias (for some of the listed
materials); however, given the materials used, the resulting
structure will experience the mechanical failures described below
with reference to Table 1. Gaul utilizes materials that are more
closely thermally matched, namely W and poly-Si, but would not have
practical deposition methods for multi-10's of pin and would have
vastly differing values for modulus. It is also to be noted that
incorporation of embedded components into present carriers is
difficult due to processing limitations, such as high temperature
sintering conditions for ceramic carriers, as well as limitations
with embedded component material systems.
[0008] At the above-stated diameters, most metals which are
commonly used for integrated circuit interconnect vias generate
unacceptable stress levels on the carrier layer material (e.g., Si
or glass) due to thermal expansion mismatch. In addition, the metal
structures exhibit top surface extrusions, ruptures, or expansions
during and after typical thermal cycling. For carrier substrates
and integrated devices that are comprised of brittle materials,
such as semiconductors, glass, or ceramics, the risk of mechanical
failure by brittle fracture is significant given the thermal
expansion mismatches and the fragility of the carrier materials. In
addition to brittle fracture, interfacial delamination is likely
when employing standard materials and combinations of materials at
the stated dimensions. Table 1 provides a listing of commonly used
materials, namely silicon for substrates, and copper, tungsten, and
nickel for the metal, and their mechanical properties.
TABLE-US-00001 YOUNG'S POISSON MATERIAL MODULUS (GPa) RATIO CTE
(ppm/.degree. C.) Silicon 170 0.28 3 doped 170 0.28 2 polysilicon
Copper 130 0.34 16.5 Tungsten 411 0.28 4.5 Nickel 200 0.31 13.4
[0009] Of the metals commonly used for substrate metallization,
only tungsten (W), with a CTE of .about.5 ppm/.degree. C.
approaches the CTE of silicon (Si). However, the modulus of W is so
high (>400 GPa) compared to that of silicon (.about.170 GPa)
that brittle fracture of the Si and/or delamination of via
sidewalls are likely, given the finite but small thermal expansion
mismatch. Like W, the typical processes used to grow or deposit
poly-Si are only practical for thicknesses up to .about.1 or
several single .mu.m, and often are limited to deposition
temperatures above the maximum temperatures that can be tolerated
by integrated circuit components or wiring on the substrate above
(if these are to be fabricated prior to filling the
through-vias).
[0010] Three potential problems associated with large CTE
mismatches between vias and the Si substrate include delamination
at the via sidewalls (resulting in so-called "rattling vias" that
exhibit compromised conductivity and mechanical stability),
cracking of the Si substrate between vias, and piston-like ruptures
of any overlying or underlying structures or thin films in contact
with the top and bottom surfaces of the vias. The following
reference discusses via cracking issues: "Fiber-End Cracking in
Brittle-Matrix Composites: A Model Study", J. A. Casey, D. R.
Clarke and Y. Fu, in Metal-Ceramic Interfaces, Proceedings of an
International Workshop, ACTA Met, 1990.
[0011] The vertical extrusion due to sidewall stresses is
determined by the thermal expansion mismatch, the modulus, and the
Poisson ratio. The forces resulting from the extrusion and acting
on the overlying or underlying structures or thin films increase
with the modulus of the through-vias. The piston-like failures can
be avoided by minimizing the thermal expansion mismatch, the
Poisson ratio, and the modulus of the through-vias. If a conductive
material has a CTE which is exactly the same as that of the
substrate materials, then the modulus and Poisson ratio of the
conductive material would not be an issue.
[0012] What is needed, therefore, and what is an object of the
present invention is to provide a carrier structure which can be
fabricated at the desired dimensions and which can withstand
thermal cycling experienced during production, joining processing,
and use.
[0013] Another object of the present invention is to provide a
through-via structure including conductive material having a
coefficient of thermal expansion which closely matches the
substrate material, a reduced modulus and a reduced Poisson ratio
in order to minimize the negative effects of thermal mismatch.
[0014] Yet another object of the present invention is to provide a
through-via structure which includes multiple differing materials
having different coefficients of thermal expansion, to result in a
through-via having an effective coefficient of thermal expansion
which most closely matches that of the substrate, to minimize the
negative effects of thermal mismatch.
[0015] Another object of the invention is to provide a through-via
structure which includes multiple differing materials having
different coefficients of thermal expansion, to result in a
through-via having an effective coefficient of thermal expansion
which closely matches that of the substrate material and an
effective modulus which most closely matches that of the substrate,
or which is reduced to be less than that of the substrate, to
reduce mechanical stresses encountered in processing and use.
[0016] Yet another object of the invention is to provide ultrahigh
density multi-chip packaging with through-vias, facilitating the
inclusion of discrete or passive devices, to enable ultrahigh
density system-on-package integration.
[0017] Another object of the invention is to provide ultrahigh
density multi-chip packaging with edge connectors to bring all
wiring out for connection to a carrier or other level of
packaging.
SUMMARY OF THE INVENTION
[0018] The foregoing and other objects are realized by the present
invention which provides a carrier structure and method for
fabricating a carrier structure having through-vias which are
filled with a composite conductive material having a coefficient of
thermal expansion which closely matches that of the substrate and
having a modulus value which matches or is less than that of the
substrate. The composite conductive material may be a conducting
metal, a conducting metal ceramic, a conducting mixture of metals
and ceramics, or a metal with a sealed void.
[0019] One embodiment of the invention includes a structure and
method for fabricating a carrier structure having through-vias
comprising concentric via fill areas each having differing
materials disposed therein, wherein the via structure has an
effective thermal coefficient of expansion and an effective modulus
which are matched more closely to that of the carrier substrate
material.
[0020] In another embodiment, each via structure is patterned as a
annulus about a post "via" of the carrier material. The annulus is
patterned to a depth which is the same as the desired length of the
via and is less than the overall depth of the carrier layer. Upon
filling the annulus with the desired conductive material, the
conductor-lined, carrier-material-filled via is then exposed by
polishing back the surface of the carrier having the base of the
post to expose the conductive ring.
[0021] Using the inventive carrier structure having through-vias
which are filled with a composite conductive material having a
coefficient of thermal expansion which closely matches that of the
substrate, ultrahigh density packages can be provided to enable
ultrahigh density system-on-package integration. The ultrahigh
density package is preferably provided with an integrated edge
connector for connection to a carrier. System-on-chip is realized
when multiple devices are connected to both sides of the ultrahigh
density package.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The invention will now be described in greater detail with
specific reference to the appended drawings wherein:
[0023] FIG. 1 is a side view of the carrier of the instant
invention;
[0024] FIGS. 2A, 2B, 2C, and 2D are perspective views of carriers
having through-vias with matched mechanical properties formed in
accordance with different embodiments of the present invention;
[0025] FIG. 3 is a flow chart of a representative process flow for
fabricating a carrier with through-vias, as shown in FIG. 2A, in
accordance with one embodiment of the present invention;
[0026] FIGS. 4A through 4K illustrate the structures obtained at
each step of processing a carrier with through-vias in accordance
with the process flow of FIG. 3 with further backside
processing;
[0027] FIG. 5 is a flow chart of a representative process flow for
fabricating a carrier with through-vias, as shown in FIG. 2B, in
accordance with a second embodiment of the present invention;
[0028] FIGS. 6A through 6F illustrate the structures obtained at
each step of processing a carrier with through-vias in accordance
with the process flow of FIG. 5;
[0029] FIG. 7 is a flow chart of a representative process flow for
fabricating a carrier with through-vias, as shown in FIG. 2C, in
accordance with another embodiment of the present invention;
[0030] FIGS. 8A through 8E illustrate the structures obtained at
each step of processing a carrier with through-vias in accordance
with the process flow of FIG. 7;
[0031] FIG. 9 is a flow chart of a representative process flow for
fabricating a carrier with through-vias, as shown in FIG. 2D, in
accordance with another embodiment of the present invention;
[0032] FIGS. 10A through 10E illustrate the structures obtained at
each step of processing a carrier with through-vias in accordance
with the process flow of FIG. 9;
[0033] FIGS. 11A through 11C illustrate the formation of a collar
about the top opening of the through-via to facilitate optimal
electrical contact;
[0034] FIGS. 12A through 12C illustrate steps and the resulting
structures for capping the through-vias, and
[0035] FIGS. 13A and 13B provide side and top views of a
system-on-chip mounted on an ultrahigh density package with an
integrated edge connector in accordance with the present invention;
and
[0036] FIGS. 14A and 14B illustrate two arrays of ultrahigh density
packages bearing system-on-chip and edge connectors connected to a
carrier.
DETAILED DESCRIPTION OF THE INVENTION
[0037] The invention addresses the shortcomings of the prior art by
providing metal-ceramic materials, or multiple materials in
through-vias, wherein the materials are chosen to reduce the
negative effects of thermal mismatch by achieving an effective
thermal expansion coefficient and an effective modulus which more
closely matches those of the carrier substrate material. For a
carrier substrate of silicon, which has a CTE of 3 ppm/.degree. C.
and an elastic modulus of 170 GPa, it is preferable to fill the
through-via with a material or a combination of materials that
yield an effective CTE of less than 8 ppm/.degree. C. and an
effective elastic modulus of less than or equal to 170 GPa. FIGS.
2A, 2B, 2C, and 2D are perspective views of carriers having
through-vias with matched mechanical properties formed in
accordance with different embodiments of the present invention.
[0038] FIG. 2A shows a side view of one carrier embodiment 200 of
the invention wherein an annular ring 215 of a first via material,
comprising a desired conductor, is disposed about the periphery of
the via hole in the carrier substrate material 204, lining the
cylinder, with the inner volume of the lined cylinder being filled
with a second via material 210. The second via material is chosen
to have a CTE which is close to the CTE of the carrier substrate
material 204, so that undesirable effects of thermal mismatch will
be minimized while still realizing the desired conductive
properties in the through-via. An additional insulating ring 203 or
liner may be disposed between the annular ring 215 and the carrier
substrate material 204 to act as an additional insulator or
diffusion barrier or both.
[0039] FIG. 3 is a flow chart of a representative process flow for
fabricating a carrier with through-vias, as shown in FIG. 2A, in
accordance with one embodiment of the present invention. The
carrier substrate, made of a semiconductor or insulative material,
silicon for example, is etched at step 300 to form blind vias.
Blind vias are defined as vias which extend to a desired depth into
the carrier substrate layer, which desired depth is less than the
thickness or depth of the initial carrier substrate. The desired
depth is defined as the depth of the cylindrical through-vias which
will result from the process, also defined for most resulting
structures as the desired overall thickness of the end-product
carrier substrate with through-vias. The blind vias are etched into
the silicon, or other carrier material, at step 300, using standard
etching techniques known in the art. A suitable deep etch method is
described in co-pending patent application Ser. No. 10/639,989,
entitled "Deep Filled Vias", which was filed on Aug. 13, 2003
(Docket YOR920030048US1), and is assigned to the present assignee,
the teachings of which are incorporated herein by reference. In the
presently preferred embodiment, the substrate comprises silicon and
the pattern transfer can be accomplished using silicon etching by
fluorine radicals generated in a plasma, as is known in the art.
Deep silicon structures can be patterned using
commercially-available, deep reactive ion etch (RIE) systems such
as the A601E, available from Alcatel. The deep RIE dry etching
method uses time-multiplexed deep etching (TMDE), a variation of
sidewall passivation, wherein etching and deposition cycles are
performed sequentially. During the deposition step, sidewalls are
passivated by a polymer deposited from a plasma, formed from the
deposition precursor. During the subsequent etching cycle, both the
polymer and the silicon are preferentially etched from the bottom
of the trench by ion bombardment. By switching between etching and
deposition cycles, deep, anisotropic structures having vertical
sidewalls can be realized with very high etching rates in silicon
substrates. A backside oxide or metal layer may optionally be used
as a stopping layer for the deep Si etch. If a semiconductor or
other conductive substrate is used, the exposed surfaces of the
cylindrical blind vias must then be insulated at step 302 to avoid
electrical grounding, shorting, or crosstalk through the substrate
of signals that will be carried by the conductive through-vias.
[0040] Insulation of the via sidewalls may be achieved through any
number of standards techniques including, but not limited to,
thermal oxidation in a tube furnace in an oxygen or steam
environment at between 900.degree. C. and 1100.degree. C.,
low-pressure chemical vapor deposition (LPCVD) using TEOS at
temperatures between 700.degree. C. and 900.degree. C., or
plasma-enhanced chemical vapor deposition (PECVD) using silane or
TEOS and oxygen or nitrous oxide, at temperatures between
300.degree. C. and 600.degree. C. Nitrides may be deposited using
silane, ammonia, and nitrogen precursors. The time is determined by
the desired oxide or nitride thickness, such as 0.5-2.0 .mu.m.
Oxide, nitride, or bilayers of the two materials are all used to
insulate the exposed sidewalls and floor of the blind vias. For
insulating substrates such as glass this step may not be necessary;
however, a layer of an insulating material such as Si.sub.3N.sub.4
may still be desired to act as a diffusion barrier.
[0041] Thereafter, at step 304, annular deposition is conducted to
form an annular ring of the desired conductor along the exposed
insulated surfaces of the blind via. The annular deposition may
consist of a PVD barrier layer, a seed layer, and a plated metal,
for example, PVD TaN/Ta/Cu plus plated Cu. The PVD barrier layer
aids in adhesion of the filling metal, as well as protecting it
from corrosion or thermal diffusion into the outlying carrier
substrate material. As noted above, it is preferable not to fill
the entire via with the desired metal, since unacceptable thermal
mismatch will result in breakage or delamination. Therefore, a
controlled deposition is conducted to result in a thin annular ring
of the conductive material.
[0042] At step 306, the remaining volume of the cylindrical blind
via is filled with a second via material, which is either
conducting or insulating, comprising material such as poly-Si,
SiO.sub.2, Si.sub.3N.sub.4, CVD-W, an inorganic oxide (e.g., glass,
ceramic or glass ceramic compounds), a metal ceramic compound such
as Cu-cordierite, or other suitable materials having CTE in the
range of .about.0 to .about.5 ppm/.degree. C., wherein the second
via material has a thermal coefficient of expansion which matches
or more closely approximates the CTE of the carrier substrate
material (e.g., Si). In the example of Cu fill in a 100 .mu.m
diameter Si through-via, it has been calculated that a Cu plating
thickness equal to 1/10 of the via diameter and filled with SiO2
will lead to the desired thermal and conductive properties.
[0043] Fill methods may include PECVD, PVD, plating, spin-on,
sol-gel, bladder fill, or squeegee application with doctor blade.
Some materials such as spin-on, sol-gel, and pastes may require a
subsequent thermal cure and sinter. For example, for a
Cu/Cordierite paste the deposition method used is preferably a
vacuum assisted infiltration technique. A carrier with blind-etched
through-vias is placed within a chamber and a mechanical vacuum is
drawn. The Cu/Cordierite paste is introduced and a squeegee or
doctor blade is used to extrude the paste into the evacuated via
holes. A preferred process incorporates screening from a
pressurized nozzle under vacuum to achieve voidless fill at room
temperature. The filling step is followed by a drying bakeout step
and then removal of residual paste from the top surface. Thereafter
a multistep sintering process is conducted, first under steam
(400.degree. C. to 650.degree. C.) to burn out any organics from
the paste, and then is followed by a higher temperature
(650.degree. C. to 800.degree. C.) sintering step under forming gas
to reduce any oxide in the metal system and assure good
interlinking of the Cu particles.
[0044] After the filling of the remaining volume has been
completed, the structure is planarized back to the top surface of
the carrier substrate at step 308 to remove any materials deposited
thereon. IC circuits and components may be fabricated on the top
surface at some point, with care being taken to make electrical
contact with the conductive annulus of the through-via. It may
additionally be desirable to cap the second via vill material as
detailed below with reference to FIGS. 12A through 12C. Finally,
the bottom surface of the structure is subjected to a grinding and
polishing step at 310 to expose the conductive annular ring
material and second via fill material, resulting in the structure
of FIG. 2A at the desired thickness for the end product carrier
substrate with through-vias.
[0045] FIGS. 4A through 4K illustrate the structures obtained at
each step of processing a carrier with through-vias in accordance
with the process flow of FIG. 3 with further detail regarding the
backside processing. Substrate 404 in FIG. 4A comprises the silicon
substrate having etched blind vias. In FIG. 4B, the blind vias have
been provided with an insulating layer 403, followed by the annular
fill illustrated as 415 in FIG. 4C. The CTE-matched fill material
410 is then provided, overfilling the vias as shown in FIG. 4D.
After planarization of the top surface, and any optional processing
to fabricate IC devices or circuits on the top surface, the
structure of FIG. 4E is then subjected to the grinding and
polishing step at the bottom surface to remove the excess substrate
material and bottom via fill materials (i.e., the insulating layer
403 and metal 415 which line the bottom of the blind vias) to
expose the through vias as shown in FIG. 4G.
[0046] The backside grind and polish is preferably done to within
10-20 .mu.m of the via bottoms, after which they are exposed by
using a wet etch to recess the remaining silicon as shown in FIG.
4H. Care is taken to protect the frontside of the structure (wafer)
from the wet etch chemistry. This can be done through a number of
methods, representatively illustrated as layer 420 in FIG. 4F,
including but not limited to a) a sacrificial protective coating
such as a deposited oxide, nitride, or polyimide spin-on; b) a
protective tape that is impervious to backside wet processing
chemistry; or c) a fixture which creates a seal at the wafer edge
and covers the frontside. The frontside protection is removed after
all backside wet processing is complete. Wet etch of the silicon to
reveal the vias can be done with etches such as potassium hydroxide
(KOH) or tetramethylammonium hydroxide (TMAH). Concentrations of
these chemistries can range from 10-50% by weight. The KOH or TMAH
is typically heated to 50.degree. C.-80.degree. C. which results in
faster etching of the silicon. A timed etch is used to etch the
silicon and recess the surface below the via tops by 5-10 .mu.m.
After etching the carrier material as shown in FIG. 4H, a blanket
layer 423 of oxide, or other insulating material such as polyimide,
is deposited as shown in FIG. 4I. Any remaining oxide cap or
oxide/nitride cap that surrounds the exposed via bottoms is briefly
polished by CMP to expose the conductive material in the via cores
as illustrated in 4J, while leaving the bulk of the thicker
backside wafer insulation in place. The back surface of the silicon
wafer is thus completely insulated except over the conductive
through-vias, so that metal pads or C4s, 425, can be deposited over
the via tips without shorting to the substrate as shown in FIG.
4K.
[0047] The structure of FIG. 2B comprises a substrate 224 in which
the through-via comprises an annular ring of insulating material
223 within which is disposed a conductive via of metal (e.g.,
copper) 225 having a void 220 at its core. The top and bottom
surfaces of the through-via are copper, and copper covers the
insulated sidewalls of the through-via. However, a void filled with
a gas such as air, an inert gas, or N.sub.2, or alternatively a
vacuum, is disposed at the center of the through-via and provides
an effective modulus which is more nearly matched to the substrate
224. The through-via becomes compliant when voided, resulting in a
lower effective modulus and a lower effective Poisson ratio, and
therefore exhibiting lower stresses and forces due to surrounding
structures. The effective Poisson ratio here is defined as the
ratio of out-of-plane displacement to in-plane displacement due to
in-plane stress to reduce mechanical stresses encountered in
processing and use. For a through-via material with high Poisson
ratio of 0.4, the effective Poisson ratio can be reduced to about
0.22 with the introduction of a percolated network of through-voids
with an effective radius of three quarters of the through-via
radius when a through-void of radius of three quarters of the via
radius is introduced in the through-via. Although it does not
change the thermal expansion coefficient, the introduction of a
void or voids reduces the effective modulus and Poisson ratio of
the through-via, resulting in a compliant through-via that exerts
much less stress and force on the surrounding structures. In other
words it behaves on a whole as if it had a much smaller thermal
expansion mismatch with the substrate, thereby reducing piston-like
deviations at the top during thermal cycling.
[0048] FIG. 5 is a flow chart of a representative process flow for
fabricating a carrier with through-vias, as shown in FIG. 2B, in
accordance with a second embodiment of the present invention. At
step 500, blind vias are etched into the substrate, as above, to a
depth which is slightly greater than the desired depth of the
through-vias in the finished product. At step 502, the sidewalls of
the blind vias are insulated (as above), preferably by oxidizing
silicon to form a thin layer of SiO.sub.2 or PECVD oxide or nitride
or both. An annular fill is conducted at step 504 to provide metal
(e.g., PVD TaN/Ta/Cu plus plated Cu to thickness .about. 1/10 to
1/5 of the via diameter) along the exposed insulated surfaces of
the blind via. The top of the via is then capped with metal by
either an overfilling, burnishing, or similar technique. The void
in the center of the via will contain the ambient of the capping
process, typically N2 or a vacuum. Overfilling is achieved by a
PVD, CVD, evaporation, or sputtering process for metal deposition
that will enclose and pinch off the via top. A polishing step may
be needed to restore planarity. In the alternative, burnishing a
conformally-plated blanket copper layer (which partially fills the
through-via) with a blunt-tipped tool can also be used to smear the
ductile copper from the wafer surface into and over the via hole,
thus creating a sealed cavity within the via. The void will not
introduce mechanical stress upon the substrate during subsequent
processing or use. Thereafter, the top of the structure is
planarized at step 508 to remove excess metal at the top surface
and to expose the substrate between the vias. The planarization
step must leave the top via surfaces of metal disposed in the top
surface of the substrate material. Fabrication of IC circuits or
components, etc. on the top surface may be done at some point, as
above. Finally, at step 510, the bottom substrate surfaces are
exposed to the backside processing steps to expose the blind vias
and remove the excess substrate material and insulating layer and
insulate the substrate bottom surface, as above. Care must be taken
at both the top and bottom surfaces to leave metal across the
entire via surface in order to preserve the void within.
[0049] FIGS. 6A through 6F illustrate the structures obtained at
each step of processing a carrier with through-vias in accordance
with the process flow of FIG. 5. At FIG. 6A, the blind vias are
etched in substrate 604. The insulating layer 603 is formed in the
blind vias of the structure in FIG. 6B. Thereafter, the annular
fill is conducted to provide metal 615 along the exposed insulated
surfaces of the vias to yield the structure of FIG. 6C. The sealing
or burnishing step provides additional metal 625 at the top surface
of the vias, in conductive contact with the metal 615 and seals
void 620 within, as shown in FIG. 6D. Planarization is done to
remove the excess metal and expose the substrate 604 and metal vias
at the top surface as shown in FIG. 6E. IC circuits or components
may be fabricated on the top surface, as above. Finally, the bottom
of the structure is exposed to the backside processing steps to
remove the excess substrate material and insulating layer at the
bottom of the vias, while leaving metal at the via bottom, as
illustrated in FIG. 6F.
[0050] The structure of FIG. 2C comprises a substrate 234 in which
the through-vias each comprise an annular ring of insulating
material 233 within which is disposed concentric circles comprising
conductive via metal (e.g., copper) 235, inner insulating ring 236,
and a core post 230 of substrate material. This differs from the
coaxial through-via of the aforementioned Gaul patent in that the
center post here is an insulator or semiconductor and does not
carry the electrical signal. The center post is not contacted by
the IC circuitry on the top or on the bottom of the carrier. The
post is effectively a hollow waveguide, and could even be used for
optical conductance through the Si substrate. The inner core of
substrate material will necessarily be a thermal and modulus match
to the outer substrate material, thereby reducing the mechanical
effects of the overall via structure on the substrate.
[0051] FIG. 7 is a flow chart of a representative process flow for
fabricating a carrier with through-vias, as shown in FIG. 2C, in
accordance with a third embodiment of the present invention. At
step 700, blind vias are etched into the substrate to a depth which
is the desired depth of the through-vias in the finished product.
The vias are etched in a pattern whereby each is an annular via of
thickness .about. 1/10 to .about.1/5 of the via diameter etched
about a post of substrate material which will remain as the core of
the via. At step 702, the sidewalls of the blind vias are
insulated, preferably by oxidizing silicon to form a thin layer of
SiO.sub.2 (see above) on both the outer sidewalls and the post
sidewalls. The annular vias are then overfilled with the desired
conductive material at step 704. Thereafter, the top of the
structure is planarized at step 708 to remove excess metal at the
top surface and to expose the substrate between the annular metal
rings of the vias. IC circuits or components may be fabricated on
top surface, as above. Finally, at step 710, the bottom substrate
surfaces are exposed to the backside processing steps to expose the
blind vias and remove the excess substrate material and insulating
layer.
[0052] FIGS. 8A through 8E illustrate the structures obtained at
each step of processing a carrier with through-vias in accordance
with the process flow of FIG. 7. At FIG. 8A, the annular vias are
etched in substrate 804. The insulating layer 803 is formed on the
sidewalls of the annular vias of the structure in FIG. 8B.
Thereafter, the annular fill is conducted to provide metal 815
along the exposed insulated surfaces of the vias to completely fill
the vias and yield the structure of FIG. 8C. Planarization is done
to remove the excess metal and expose the substrate 804 and annular
metal vias at the top surface as shown in FIG. 8D. IC circuits or
components may be built on top surface, as above, with care taken
to contact the conductive annulus. Finally, the bottom of the
structure is exposed to the backside processing steps to remove the
excess substrate material and insulating layer at the bottom of the
vias, as illustrated in FIG. 8E.
[0053] The structure of FIG. 2D comprises substrate 244 having vias
of metal-ceramic core 245 surrounded by an annular insulating ring
243. The metal-ceramic is chosen to have a coefficient of thermal
expansion which is closely matched to the CTE of the substrate
material, as well as a modulus which is close to that of the
substrate or which is less than that of the substrate, with enough
porosity to decrease the effective modulus and Poisson ratio.
Examples of suitable materials include a copper cordierite
metal-ceramic, surrounded by an SiO.sub.2 or
SiO.sub.2/Si.sub.3N.sub.4 insulating layer in a silicon substrate.
Additional materials of interest would be other low CTE materials,
such as, but not limited to, glass ceramic, beta-Eucryptite,
Enstatite, Fosterite, millite, Zircon, and fused silica. Metals in
addition to copper, such as gold and silver, would be suitable
candidate conductors due to their excellent conductivities.
Additionally, alloys of the above metals as well as solid solution
alloys such as Cu--Ni are of interest.
[0054] Another example of a suitable fill material consists of fine
particles of a low-CTE core material coated with a thin layer of
linking metal such as copper. The low CTE core can consist of a
wide range of materials from low CTE metals or alloys such as
molybdenum, tungsten or Invar to nonmetals such as SiO2, silicon
and silicon carbide. The coating material must consist of a metal
for electrical conductivity, and should be able to form
metallurgical joins at temperatures compatible with other
structures already built on the wafer. Copper is a particularly
desirable material because it is highly conducting and can form
joins by Cu surface diffusion at temperatures considerably below
its melting point. Other metals or alloys are also suitable such as
thin layers of solder.
[0055] Further, heterogeneous mixtures of particles with the same
outer layer (joining metal) but with different cores, could be
utilized to advantage. For instance a mixture of copper coated
tungsten (Cu/W) could be mixed with copper coated SiO2 (Cu/SiO2).
The combination would lower the average CTE compared to Cu/W alone
(which is already low CTE relative to Cu alone) while maintaining
enough Cu/W to ensure outstanding electrical conductivity as well
as ensuring mechanical and electrical connectivity between all
outer shells. In addition there may be advantages in some cases to
mixing particles with dissimilar outer layers. For instance, two
particle types could be coated with metals A and B, where a low
melting AB eutectic could form upon contact and mild heating.
[0056] Calculations suggest that a greater than 2000 Angstrom
coating is desirable for high electrical conductivity if the outer
layer alone were the only contributor to conductivity as would be
the case of Cu coated SiO2. For particles with conducting cores,
the thickness of the Cu outer layer should be as thin as possible
to keep the net CTE low while maintaining good joining
characteristics.
[0057] FIG. 9 is a representative flow chart for fabricating the
structure of FIG. 2D. At step 900 the blind vias are etched into
the substrate. At step 902, an insulating layer is formed along the
exposed surfaces of the blind vias, typically by exposing the
structure to an oxidizing atmosphere or PECVD, etc. as above.
Thereafter, the remaining via volume is filled with the
metal-ceramic. As illustrated, a metal-ceramic paste may be spread
in the insulated vias at step 904, followed by a sintering step to
cure the via fill. To remove excess paste overburden and particle
residue a four stage cleaning method was developed including a
first rinse step, a first coarse wiping step, a second fine wiping
step, and a spin dry step. Details of an apparatus and method for
applying paste into blind vias in a wafer are described in a
separate patent application Ser. No. 10/700,327, entitled "Method
and Apparatus for Filling Vias", (YOR920030196US1), which was filed
on Nov. 3, 2003, the teachings of which are herein incorporated by
reference. A low-temperature bake (between 100.degree. C. and
200.degree. C.) in nitrogen or an inert ambient or vacuum may be
used to drive off volatile components in the paste before high
temperature sintering begins. This low temperature step may be
tailored to allow controlled shrinkage of the paste compound, thus
affording the possibility of using multiple filling steps to
achieve a precise level of fill or a controlled recess. Multistep
sintering between 400.degree. C. and about 900.degree. C. can be
used in a variety of ambients (including nitrogen or steam ending
with forming gas) to achieve complete burnout of any organic
components at lower temperatures, and to achieve complete reduction
of any oxide and good linking of metal particles at higher
temperatures. This will result is a connected network of metal
particles within a porous cordierite/glass phase. Planarization at
step 908 will remove any excess conductive material from the
backside processing at step 910 will expose the through-vias.
[0058] FIGS. 10A through 10E illustrate the structures obtained at
each step of processing a carrier with through-vias in accordance
with the process flow of FIG. 9. At FIG. 10A, the vias are etched
in substrate 1004. The insulating layer 1003 is formed on the
sidewalls of the vias of the structure in FIG. 10B. Thereafter, the
fill is conducted to provide metal-ceramic 1015 along the exposed
insulated surfaces of the vias to completely fill the vias and
yield the structure of FIG. 10C. Planarization is done to remove
the excess metal and expose the substrate 1004 and metal vias at
the top surface as shown in FIG. 10D. IC circuits or components may
be added as above. Special care must be taken to make electrical
contact the top surface of the metal-ceramic filled
through-vias.
[0059] Finally, the bottom of the structure is exposed to grinding
and polishing and etching to remove the excess substrate material
and then adding an insulating layer to the exposed silicon
substrate and subsequently removing the insulator only over the
raised via bottoms by selective polishing, as illustrated in FIG.
10E.
[0060] An effective method for ensuring good electrical contact to
the surface of a partially plated through-via is to etch a shallow,
concentric collar of suitably larger diameter in substrate 1104
around the top of the through-vias as shown in FIGS. 11A-11C. Such
a structure adds a mask step, but greatly enhances the chances of
achieving a good contact to subsequent levels of wiring as long as
the collar depth is set to be no greater than the sidewall plating
thickness. During final planarization, the collar effectively
extends the annulus 1115 of FIG. 11C outward, offering a larger
capture surface on which to drop contact vias, while moving these
contacts further away from the central area of the deep via, filled
with conductive material 1110, where filling is most
challenging.
[0061] The fill material and processing described above may be
tailored to leave the filled vias with an intentionally porous
internal structure and/or with a controlled recess between the
surface of the fill material and the top of the via. An
intentionally porous and/or recessed surface must be effectively
capped and sealed before the via planarization step to enable
subsequent processing of the substrate. A number of metals and
deposition methods can be used to seal effectively seal and cap
such vias, including but not limited to tungsten, tantalum, or
copper. Deposition methods may include sputtering, plasma jet
deposition, thermal or laser-assisted CVD, molten liquid, metal
infiltration via capillary action, or bumping with solder. Cap
thickness may vary between about 0.5 to 10 microns depending on the
size of the surface pores and/or the depth of the recess. In the
case of sputtered or jet-deposited copper, it is particularly
useful to post-anneal the metal at a temperature above 500 C to
assure good pore-sealing prior to final planarization. This anneal
can be achieved using standard oven or hot plate anneals or using
laser assisted localized heating of the cap metal.
[0062] An alternative approach for metal capping of the filled
porous via is the use of insulators. This is particularly practical
with the partially plated vias where the electrical connection
through the carrier is not counting on the via fill. Thus any
number of high temperature (> or .about.400 C) stable insulating
materials including but not limited to silicon dioxide, silicon
nitride, silicon oxynitride, ceramics or high temperature polymers
can be used. The inorganic material may be deposited using
thermally activated or plasma-enhanced CVD, sputtering, or other
such techniques known in the microelectronics field as well as
plasma jet deposition. Co-Pending U.S. patent application Ser. No.
______, filed Oct. 17, 2003, entitled "Silicon Chip Carrier with
Through-Vias Using Laser Assisted CVD of Conductor", provides
deposition teachings, which are herein incorporated by reference.
Photolithography may be used to remove insulator from the field
areas, leaving it only on the via surface to seal pores and/or fill
any recess. Final surface planarization after capping is done using
CMP to expose the partially plated via sidewall top surface, or
planarizing to the level of desired insulator thickness for
electrical connection of the overlying build to the deep via.
[0063] High temperature polymers, including but not limited to
polyimides or photosensitive polyimides (PSPI), may be spin applied
from solution, laminated, or vapor deposited onto the surface of
the substrate 1204, as shown at 1220 of FIGS. 12A-12C, having
through-vias including insulative via liner 1203, conducting
material 1215, and via fill 1210. With appropriate viscosity and
surface tension properties the liquid polyimide precursor may not
significantly penetrate into the porous via, thus largely
preserving the thermal properties of said via. To aid in the
removal of the excess polymer in the field area, the negatively or
positively working PSPI is exposed and developed to remove the
unwanted material, FIG. 12B. A touch-up polish can be applied to
improve further the planarity of the surface. The electrical
connection after insulator capping is done at the partially plated
via sidewalls, or a conductive cap, shown as 1225 in FIG. 12C, can
be deposited to connect electrically the via sidewalls.
[0064] All of the embodiments of the present invention provide
conductive through-vias having effective CTEs and modulus values
which are more closely matched to the CTE and modulus of the
substrate materials than pure metal or metal compound vias. As well
some have reduced Poisson ratios. Optimally, the finished
supporting substrate has a thickness of 300 .mu.m, with via aspect
ratios of less than or equal to 4:1, such that the through-via
diameter must be greater than or about equal to 75 .mu.m.
[0065] Once the supporting carrier has been fabricated, preferably
of a thickness of at least 150 .mu.m and ideally 350 .mu.m in
thickness, with through-vias filled with conductive material that
is thermally matched and modulus matched, multiple devices can be
mounted on both sides of the substrate. As illustrated in FIGS. 13A
and 13B, a system-on-chip 1300 can be realized by connecting
multiple devices to the ultrahigh density package. Silicon carrier
1304 with metallized through-vias 1315, provides connection through
intermediate multilevel wiring layer 1306 for chips 1320 and 1340
mounted on C4s 1325 on one side of the carrier and for chip 1360 on
the other side of the carrier. Since the Si carrier is built from a
semiconductor, it is possible to include all types of active and
passive devices on the carrier, such as are conventionally built in
integrated circuits. Multiple chips and discrete devices including,
but not limited to, optical modulators, FET transistors, thin oxide
trench or surface capacitors, varactors, logic or analog integrated
circuits, resistors, inductors, transmission lines, can be mounted
to the package. The multiple chips and discrete devices may be
mounted in very close proximity (e.g., 5-10 .mu.m) on one or both
sides of the Si carrier. Mounting is done by conventional
techniques. Dual heat spreaders 1350 and 1370 can be provided on
the backside of the mounted chips, using thermal paste or other
conventional heat-sinking interface, to dissipate heat generated by
the chips.
[0066] The silicon carrier preferably includes one or more levels
of wiring, preferably Cu wiring at single .mu.m dimensions for
optimum density and bandwidth. The wiring 1355 may be provided on
one or both sides of the package, with connection through the
through-vias if wiring is only formed on one side of the package.
Dual-damascene processing for Cu wiring, as is well known in the
art, may be used to form the wiring. Pitches for the wiring are
preferably no greater than approximately 5 .mu.m to allow parallel
memory bussing between chips for terabit per second data
processing. For a Si carrier with chips or chip stacks mounted on
both sides, the external I/O would be provided near one or more
edges of the Si carrier top or bottom surface, shown as 1365. For
example, linear or staggered arrays of bonding pads along one or
both surfaces could be bonded to a lead frame or wire bonded to the
inner leads of a socket or edge connector 1365 which would
ultimately mate to an outside socket on a printed circuit board.
Ideally, the entire assembly is enclosed in a metal, plastic,
ceramic, or other material package enclosure, illustratively shown
as 1380, so that all of the electronics are enclosed, with the lead
frame or edge connector leads being exposed and the outer surfaces
of the heat spreaders remaining exposed for thermal contact with
suitable mating structures or materials for external heat sinking.
Heat fins (not shown) may additionally be provided at the assembly
edge not occupied by the edge connector.
[0067] Single or multiple ultrahigh density system-on-chip packages
1400A, 1400B, 1400C, 1400D . . . 1400N and 1410A, 1410B, 1410C,
1410D through 1410N may now be plugged in via their respective edge
connectors 1465A-1465N and 1475A through 1475N to mating connectors
on a printed circuit board 1490, rack, backplane or the like, as
shown in FIGS. 14A and 14B. Heat sink fins or other devices, shown
illustratively as 1450D and 1450N, may be attached to the outside
or outer edges of the ultrahigh density packages. As illustrated in
FIG. 14B, air 1492, or coolant 1494, such as water, could be
circulated through the compartment 1490 to cool the packages,
thereby extracting heat directly from the mounted chips inside the
ultrahigh density package arrays.
[0068] In one embodiment, a complete ultrahigh performance computer
system such as a PC or portable gaming system (e.g., 4 or more
chips) could be packaged in an ultrahigh density package with an
edge connector in such a manner as to comply with the "Compact
Flash" format. In another preferred embodiment, an entire
supercomputer node (CPU, memory communications interfaces) could be
packaged in a similar Compact Flash format and plugged vertically
into a PC board or backplane so that it is, itself, a heat-sink
cooling fin. Alternatively, the supercomputer node could be bolted
into a cold plate that has internal coolant circulation (need
illustrations of the latter two). Multiple similar nodes would then
be plugged into a PC board or backplane in close proximity to form
a composite multi-node heat-sink structure populating the board or
plane. An entire supercomputer could be constructed of the PC
boards with similar ultrahigh density packing of ultrahigh density
integrated nodes. In this manner, there is the potential for orders
of magnitude increase in supercomputer power per unit volume of
space.
[0069] While the invention has been described with reference to
several preferred embodiments, it should be understood that
modifications can be made without departing from the spirit and
scope of the invention as set forth in the appended claims.
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