Lane; Michael Wayne
Patent Applications and Registrations
Patent applications and USPTO patent grants for Lane; Michael Wayne.The latest application filed is for "ultralow dielectric constant layer with controlled biaxial stress".
- Lane; Michael Wayne - Cortlandt Manor NY
| Patent | Date |
|---|---|
| Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures Grant 7,825,516 - Chiras , et al. November 2, 2 | 2010-11-02 |
| Ultralow Dielectric Constant Layer With Controlled Biaxial Stress App 20090304951 - Dimitrakopoulos; Christos Dimitrios ; et al. | 2009-12-10 |
| Ultralow Dielectric Constant Layer With Controlled Biaxial Stress App 20080286494 - Dimitrakopoulos; Christos Dimitrios ; et al. | 2008-11-20 |
| Ultralow dielectric constant layer with controlled biaxial stress Grant 7,357,977 - Dimitrakopoulos , et al. April 15, 2 | 2008-04-15 |
| Ultralow Dielectric Constant Layer With Controlled Biaxial Stress App 20080044668 - Dimitrakopoulos; Christos Dimitrios ; et al. | 2008-02-21 |
| Silicon chip carrier with conductive through-vias and method for fabricating same Grant 7,276,787 - Edelstein , et al. October 2, 2 | 2007-10-02 |
| Line level air gaps App 20060264036 - Chen; Shyng-Tsong ; et al. | 2006-11-23 |
| Line level air gaps Grant 7,084,479 - Chen , et al. August 1, 2 | 2006-08-01 |
| Silicon chip carrier with conductive through-vias and method for fabricating same App 20060027934 - Edelstein; Daniel Charles ; et al. | 2006-02-09 |
| Line level air gaps App 20050127514 - Chen, Shyng-Tsong ; et al. | 2005-06-16 |
| Silicon chip carrier with conductive through-vias and method for fabricating same App 20050121768 - Edelstein, Daniel Charles ; et al. | 2005-06-09 |
| Diffusion barriers formed by low temperature deposition App 20050110142 - Lane, Michael Wayne ; et al. | 2005-05-26 |
| Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures App 20040113277 - Chiras, Stefanie Ruth ; et al. | 2004-06-17 |
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