Andry; Paul Stephen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Andry; Paul Stephen.The latest application filed is for "through silicon via and method of fabricating same".

Company Profile

0.20.16

Andry; Paul Stephen - Yorktown Heights NY US
Andry; Paul Stephen - Mohegan Lake NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Formation of alpha particle shields in chip packaging Grant 8,928,145 - Andry , et al. January 6, 2	2015-01-06
Through silicon via and method of fabricating same Grant 8,735,251 - Andry , et al. May 27, 2	2014-05-27
Through Silicon Via And Method Of Fabricating Same App 20140094007 - Andry; Paul Stephen ; et al.	2014-04-03
Through silicon via for use in integrated circuit chips Grant 8,637,937 - Andry , et al. January 28, 2	2014-01-28
Silicon Carrier Structure And Method Of Forming Same App 20120301977 - Andry; Paul Stephen ; et al.	2012-11-29
Formation Of Alpha Particle Shields In Chip Packaging App 20120267768 - Andry; Paul Stephen ; et al.	2012-10-25
Silicon carrier structure and method of forming same Grant 8,295,056 - Andry , et al. October 23, 2	2012-10-23
Formation of alpha particle shields in chip packaging Grant 8,247,271 - Andry , et al. August 21, 2	2012-08-21
Through Silicon Via And Method Of Fabricating Same App 20120132967 - Andry; Paul Stephen ; et al.	2012-05-31
Laser release process for very thin Si-carrier build Grant 8,187,923 - Andry , et al. May 29, 2	2012-05-29
Through silicon via and method of fabricating same Grant 8,138,036 - Andry , et al. March 20, 2	2012-03-20
Silicon Carrier Structure and Method of Forming Same App 20110019368 - Andry; Paul Stephen ; et al.	2011-01-27
Through-wafer vias Grant 7,741,722 - Andry , et al. June 22, 2	2010-06-22
Method of making through wafer vias Grant 7,678,696 - Andry , et al. March 16, 2	2010-03-16
Method Of Making Through Wafer Vias App 20100035430 - Andry; Paul Stephen ; et al.	2010-02-11
Through Silicon Via And Method Of Fabricating Same App 20100032764 - Andry; Paul Stephen ; et al.	2010-02-11
Method for precision assembly of integrated circuit chip packages Grant 7,615,405 - Andry , et al. November 10, 2	2009-11-10
Chip-to-wafer integration technology for three-dimensional chip stacking Grant 7,514,290 - Sakuma , et al. April 7, 2	2009-04-07
Microelectronic device connection structure Grant 7,501,708 - Andry , et al. March 10, 2	2009-03-10
Formation Of Alpha Particle Shields In Chip Packaging App 20080318365 - Andry; Paul Stephen ; et al.	2008-12-25
Through-wafer Vias App 20080274583 - Andry; Paul Stephen ; et al.	2008-11-06
Method For Precision Assembly Of Integrated Circuit Chip Packages App 20080182362 - Andry; Paul Stephen ; et al.	2008-07-31
Microelectronic Device Connection Structure App 20080023851 - Andry; Paul Stephen ; et al.	2008-01-31
Method for precision assembly of integrated circuit chip packages Grant 7,282,391 - Andry , et al. October 16, 2	2007-10-16
Silicon chip carrier with conductive through-vias and method for fabricating same Grant 7,276,787 - Edelstein , et al. October 2, 2	2007-10-02
Method For Precision Assembly Of Integrated Circuit Chip Packages App 20070222065 - Andry; Paul Stephen ; et al.	2007-09-27
Alpha particle shields in chip packaging App 20070045844 - Andry; Paul Stephen ; et al.	2007-03-01
Silicon chip carrier with through-vias using laser assisted chemical vapor deposition of conductor Grant 7,019,402 - Andry , et al. March 28, 2	2006-03-28
Silicon chip carrier with conductive through-vias and method for fabricating same App 20060027934 - Edelstein; Daniel Charles ; et al.	2006-02-09
Silicon chip carrier with conductive through-vias and method for fabricating same App 20050121768 - Edelstein, Daniel Charles ; et al.	2005-06-09
Silicon chip carrier with through-vias using laser assisted chemical vapor deposition of conductor App 20050082676 - Andry, Paul Stephen ; et al.	2005-04-21
Vertical aligned liquid crystal display and method using dry deposited alignment layer films Grant 6,724,449 - Andry , et al. April 20, 2	2004-04-20
Method of forming ohmic contacts using a self doping layer for thin-film transistors Grant 6,620,719 - Andry , et al. September 16, 2	2003-09-16
Method of forming fully self-aligned TFT with improved process window Grant 6,403,407 - Andry , et al. June 11, 2	2002-06-11

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.