Sprogis; Edmund Juris

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sprogis; Edmund Juris.The latest application filed is for "through silicon via and method of fabricating same".

Company Profile

0.21.21

Sprogis; Edmund Juris - Underhill VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Through silicon via and method of fabricating same Grant 8,735,251 - Andry , et al. May 27, 2	2014-05-27
Through Silicon Via And Method Of Fabricating Same App 20140094007 - Andry; Paul Stephen ; et al.	2014-04-03
Through silicon via for use in integrated circuit chips Grant 8,637,937 - Andry , et al. January 28, 2	2014-01-28
Through Silicon Via And Method Of Fabricating Same App 20120132967 - Andry; Paul Stephen ; et al.	2012-05-31
Through silicon via and method of fabricating same Grant 8,138,036 - Andry , et al. March 20, 2	2012-03-20
Wafer-to-wafer alignments Grant 8,004,289 - Dalton , et al. August 23, 2	2011-08-23
Through Substrate Annular Via Including Plug Filler App 20110129996 - Lindgren; Peter James ; et al.	2011-06-02
Through substrate annular via including plug filler Grant 7,898,063 - Lindgren , et al. March 1, 2	2011-03-01
Low resistance and inductance backside through vias and methods of fabricating same Grant 7,851,923 - Erturk , et al. December 14, 2	2010-12-14
Through-wafer vias Grant 7,741,722 - Andry , et al. June 22, 2	2010-06-22
Method of making through wafer vias Grant 7,678,696 - Andry , et al. March 16, 2	2010-03-16
Through Silicon Via And Method Of Fabricating Same App 20100032764 - Andry; Paul Stephen ; et al.	2010-02-11
Method Of Making Through Wafer Vias App 20100035430 - Andry; Paul Stephen ; et al.	2010-02-11
Through Substrate Annular Via Including Plug Filler App 20090206488 - Lindgren; Peter James ; et al.	2009-08-20
Low Resistance And Inductance Backside Through Vias And Methods Of Fabricating Same App 20090184423 - Erturk; Mete ; et al.	2009-07-23
Low resistance and inductance backside through vias and methods of fabricating same Grant 7,563,714 - Erturk , et al. July 21, 2	2009-07-21
Stacked chip security Grant 7,557,597 - Anderson , et al. July 7, 2	2009-07-07
Methods and Apparatus for Assembling Integrated Circuit Device Utilizing a Thin Si Interposer App 20090085202 - Dang; Bing ; et al.	2009-04-02
Wafer-to-wafer alignments Grant 7,474,104 - Dalton , et al. January 6, 2	2009-01-06
Wafer-to-wafer Alignments App 20080308948 - Dalton; Thomas Joseph ; et al.	2008-12-18
Through-wafer Vias App 20080274583 - Andry; Paul Stephen ; et al.	2008-11-06
Photolithography Mask With Protective Silicide Capping Layer App 20080261121 - Gambino; Jeffrey Peter ; et al.	2008-10-23
Photolithography Mask With Protective Capping Layer App 20080261122 - Gambino; Jeffrey Peter ; et al.	2008-10-23
Photolithography Mask With Integrally Formed Protective Capping Layer App 20080261120 - Gambino; Jeffrey Peter ; et al.	2008-10-23
Post bump passivation for soft error protection Grant 7,348,210 - Daubenspeck , et al. March 25, 2	2008-03-25
Silicon chip carrier with conductive through-vias and method for fabricating same Grant 7,276,787 - Edelstein , et al. October 2, 2	2007-10-02
Low Resistance And Inductance Backside Through Vias And Methods Of Fabricating Same App 20070190692 - Erturk; Mete ; et al.	2007-08-16
Wafer-to-wafer Alignments App 20070132067 - Dalton; Timothy Joseph ; et al.	2007-06-14
Wafer-to-wafer alignments Grant 7,193,423 - Dalton , et al. March 20, 2	2007-03-20
Stacked chip security App 20060273438 - Anderson; Brent Alan ; et al.	2006-12-07
Post Bump Passivation For Soft Error Protection App 20060246703 - Daubenspeck; Timothy Harrison ; et al.	2006-11-02
Silicon chip carrier with conductive through-vias and method for fabricating same App 20060027934 - Edelstein; Daniel Charles ; et al.	2006-02-09
Method For Manufacturing Self-compensating Resistors Within An Integrated Circuit App 20050227449 - Murphy, William Joseph ; et al.	2005-10-13
Silicon chip carrier with conductive through-vias and method for fabricating same App 20050121768 - Edelstein, Daniel Charles ; et al.	2005-06-09
Chip-on-chip interconnections of varied characterstics Grant 6,642,080 - Ference , et al. November 4, 2	2003-11-04
Multi-chip integrated circuit module Grant 6,507,115 - Hofstee , et al. January 14, 2	2003-01-14
Multi-chip integrated circuit module App 20020074668 - Hofstee, Harm Peter ; et al.	2002-06-20
Highly integrated chip-on-chip packaging Grant 6,294,406 - Bertin , et al. September 25, 2	2001-09-25
Highly integrated chip-on-chip packaging Grant 5,977,640 - Bertin , et al. November 2, 1	1999-11-02
Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module Grant 5,923,181 - Beilstein, Jr. , et al. July 13, 1	1999-07-13
Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module Grant 5,686,843 - Beilstein, Jr. , et al. November 11, 1	1997-11-11

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