Montoye; Robert K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Montoye; Robert K..The latest application filed is for "vector cross-compare count and sequence instructions".

Company Profile

7.93.76

Montoye; Robert K. - Rochester MN
Montoye; Robert K. - Yorktown Heights NY
Montoye; Robert K. - New York NY
Montoye; Robert K. - Rocheter MN
Montoye; Robert K. - Yorktown NY US
Montoye; Robert K. - Jersey City NJ
Montoye; Robert K. - Austin TX
Montoye; Robert K. - Los Gatos CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network Grant 11,295,201 - Arthur , et al. April 5, 2	2022-04-05
Vector cross-compare count and sequence instructions Grant 11,061,675 - Derby , et al. July 13, 2	2021-07-13
Reconfigurable and customizable general-purpose circuits for neural networks Grant 10,810,487 - Brezzo , et al. October 20, 2	2020-10-20
Reconfigurable and customizable general-purpose circuits for neural networks Grant 10,628,732 - Brezzo , et al.	2020-04-21
Vector Cross-compare Count And Sequence Instructions App 20200057637 - Derby; Jeffrey H. ; et al.	2020-02-20
Vector cross-compare count and sequence instructions Grant 10,564,964 - Derby , et al. Feb	2020-02-18
Time-division Multiplexed Neurosynaptic Module With Implicit Memory Addressing For Implementing A Neural Network App 20190228289 - Arthur; John V. ; et al.	2019-07-25
Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network Grant 10,331,998 - Arthur , et al.	2019-06-25
Vector Cross-compare Count And Sequence Instructions App 20180060072 - Derby; Jeffrey H. ; et al.	2018-03-01
Efficient voltage conversion Grant 9,887,623 - Chang , et al. February 6, 2	2018-02-06
High-speed latch circuits by selective use of large gate pitch Grant 9,875,328 - Chang , et al. January 23, 2	2018-01-23
Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation Grant 9,818,058 - Arthur , et al. November 14, 2	2017-11-14
High-performance hash joins using memory with extensive internal parallelism Grant 9,817,612 - Derby , et al. November 14, 2	2017-11-14
High-performance hash joins using memory with extensive internal parallelism Grant 9,811,287 - Derby , et al. November 7, 2	2017-11-07
Method and apparatus for cache memory data processing Grant 9,792,209 - Cordero , et al. October 17, 2	2017-10-17
Efficient voltage conversion Grant 9,755,506 - Chang , et al. September 5, 2	2017-09-05
Method and apparatus for cache memory data processing Grant 9,710,381 - Cordero , et al. July 18, 2	2017-07-18
Efficient Voltage Conversion App 20170033685 - Chang; Leland ; et al.	2017-02-02
Reconfigurable And Customizable General-purpose Circuits For Neural Networks App 20160358067 - Brezzo; Bernard V. ; et al.	2016-12-08
High-speed Latch Circuits By Selective Use Of Large Gate Pitch App 20160350451 - Chang; Leland ; et al.	2016-12-01
High-speed latch circuits by selective use of large gate pitch Grant 9,496,854 - Chang , et al. November 15, 2	2016-11-15
Reconfigurable And Customizable General-purpose Circuits For Neural Networks App 20160292569 - Brezzo; Bernard V. ; et al.	2016-10-06
Reconfigurable and customizable general-purpose circuits for neural networks Grant 9,460,383 - Brezzo , et al. October 4, 2	2016-10-04
High-speed Latch Circuits By Selective Use Of Large Gate Pitch App 20160269004 - Chang; Leland ; et al.	2016-09-15
Time-division Multiplexed Neurosynaptic Module With Implicit Memory Addressing For Implementing A Universal Substrate Of Adaptation App 20160260008 - Arthur; John V. ; et al.	2016-09-08
Reconfigurable And Customizable General-purpose Circuits For Neural Networks App 20160247063 - Brezzo; Bernard V. ; et al.	2016-08-25
Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation Grant 9,373,073 - Arthur , et al. June 21, 2	2016-06-21
Efficient Voltage Conversion App 20160172970 - Chang; Leland ; et al.	2016-06-16
High-performance Hash Joins Using Memory With Extensive Internal Parallelism App 20160147451 - Derby; Jeffrey H. ; et al.	2016-05-26
High-performance Hash Joins Using Memory With Extensive Internal Parallelism App 20160147450 - Derby; Jeffrey H. ; et al.	2016-05-26
Time-division Multiplexed Neurosynaptic Module With Implicit Memory Addressing For Implementing A Neural Network App 20160110640 - Arthur; John V. ; et al.	2016-04-21
Time division multiplexed limited switch dynamic logic Grant 9,281,821 - Chang , et al. March 8, 2	2016-03-08
Time division multiplexed limited switch dynamic logic Grant 9,276,580 - Chang , et al. March 1, 2	2016-03-01
Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network Grant 9,239,984 - Arthur , et al. January 19, 2	2016-01-19
Method And Apparatus For Cache Memory Data Processing App 20150370706 - Cordero; Edgar R. ; et al.	2015-12-24
Method And Apparatus For Cache Memory Data Processing App 20150370711 - Cordero; Edgar R. ; et al.	2015-12-24
Random number generation Grant 9,160,533 - Kozlosk , et al. October 13, 2	2015-10-13
Random number generation Grant 9,148,281 - Kozlosk , et al. September 29, 2	2015-09-29
Time Division Multiplexed Limited Switch Dynamic Logic App 20150222267 - CHANG; LELAND ; et al.	2015-08-06
Programmable regular expression and context free grammar matcher Grant 9,093,151 - Freitas , et al. July 28, 2	2015-07-28
Time Division Multiplexed Limited Switch Dynamic Logic App 20150194962 - CHANG; LELAND ; et al.	2015-07-09
Time division multiplexed limited switch dynamic logic Grant 9,030,234 - Chang , et al. May 12, 2	2015-05-12
Time division multiplexed limited switch dynamic logic Grant 9,030,235 - Chang , et al. May 12, 2	2015-05-12
Writing scheme for phase change material-content addressable memory Grant 8,943,374 - Lam , et al. January 27, 2	2015-01-27
Implementing instruction set architectures with non-contiguous register file specifiers Grant 8,918,623 - Gschwind , et al. December 23, 2	2014-12-23
Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming Grant 8,902,690 - Gopalakrishnan , et al. December 2, 2	2014-12-02
Reconfigurable and customizable general-purpose circuits for neural networks Grant 8,898,097 - Brezzo , et al. November 25, 2	2014-11-25
Electronic synapses for reinforcement learning Grant 8,892,487 - Chang , et al. November 18, 2	2014-11-18
Electronic Synapses For Reinforcement Learning App 20140310220 - Chang; Leland ; et al.	2014-10-16
Reconfigurable and customizable general-purpose circuits for neural networks Grant 8,856,055 - Brezzo , et al. October 7, 2	2014-10-07
Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming Grant 8,842,491 - Gopalakrishnan , et al. September 23, 2	2014-09-23
Multi-bit resistance measurement Grant 8,837,198 - Lam , et al. September 16, 2	2014-09-16
Random Number Generation App 20140258589 - Kozlosk; James R. ; et al.	2014-09-11
Random Number Generation App 20140258594 - Kozlosk; James R. ; et al.	2014-09-11
Time-division Multiplexed Neurosynaptic Module With Implicit Memory Addressing For Implementing A Universal Substrate Of Adaptation App 20140180984 - Arthur; John V. ; et al.	2014-06-26
Time-division Multiplexed Neurosynaptic Module With Implicit Memory Addressing For Implementing A Neural Network App 20140180987 - Arthur; John V. ; et al.	2014-06-26
Multi-bit Resistance Measurement App 20140092694 - Lam; Chung H. ; et al.	2014-04-03
Sense scheme for phase change material content addressable memory Grant 8,687,398 - Chang , et al. April 1, 2	2014-04-01
Shared parallel adder tree for executing multiple different population count operations Grant 8,661,072 - Blaner , et al. February 25, 2	2014-02-25
Time Division Multiplexed Limited Switch Dynamic Logic App 20140049289 - Chang; Leland ; et al.	2014-02-20
Multi-bit resistance measurement Grant 8,638,598 - Lam , et al. January 28, 2	2014-01-28
Decoding Scheme For Bipolar-based Diode Three-dimensional Memory Requiring Unipolar Programming App 20140022850 - Gopalakrishnan; Kailash ; et al.	2014-01-23
Decoding Scheme For Bipolar-based Diode Three-dimensional Memory Requiring Unipolar Programming App 20140022851 - Gopalakrishnan; Kailash ; et al.	2014-01-23
Writing Scheme For Phase Change Material-content Addressable Memory App 20140026008 - Lam; Chung H. ; et al.	2014-01-23
Low voltage signaling Grant 8,629,705 - Chang , et al. January 14, 2	2014-01-14
Programmable Regular Expression And Context Free Grammar Matcher App 20130338998 - Freitas; Richard F. ; et al.	2013-12-19
Time Division Multiplexed Limited Switch Dynamic Logic App 20130328592 - CHANG; LELAND ; et al.	2013-12-12
Time Division Multiplexed Limited Switch Dynamic Logic App 20130328593 - Chang; Leland ; et al.	2013-12-12
Time division multiplexed limited switch dynamic logic Grant 8,604,832 - Chang , et al. December 10, 2	2013-12-10
Writing scheme for phase change material-content addressable memory Grant 8,560,902 - Lam , et al. October 15, 2	2013-10-15
Test structure for characterizing multi-port static random access memory and register file arrays Grant 8,555,119 - Chang , et al. October 8, 2	2013-10-08
Sense Scheme For Phase Change Material Content Addressable Memory App 20130223121 - Chang; Leland ; et al.	2013-08-29
Time division multiplexed limited switch dynamic logic Grant 8,493,093 - Chang , et al. July 23, 2	2013-07-23
Micro Architecture For Indirect Access To A Register File In A Processor App 20130151818 - Barak; Erez ; et al.	2013-06-13
Switched capacitor voltage converters Grant 8,395,438 - Dennard , et al. March 12, 2	2013-03-12
Reconfigurable And Customizable General-purpose Circuits For Neural Networks App 20120317062 - BREZZO; Bernard V. ; et al.	2012-12-13
Silicon Carrier Structure And Method Of Forming Same App 20120301977 - Andry; Paul Stephen ; et al.	2012-11-29
Silicon carrier structure and method of forming same Grant 8,295,056 - Andry , et al. October 23, 2	2012-10-23
Switched Capacitor Voltage Converters App 20120262226 - Dennard; Robert H. ; et al.	2012-10-18
Implementing Instruction Set Architectures With Non-contiguous Register File Specifiers App 20120265967 - Gschwind; Michael Karl ; et al.	2012-10-18
Reconfigurable And Customizable General-purpose Circuits For Neural Networks App 20120259804 - Brezzo; Bernard V. ; et al.	2012-10-11
System And Method For Providing Dynamic Addressability Of Data Elements In A Register File With Subword Parallelism App 20120260062 - Derby; Jeffrey H. ; et al.	2012-10-11
Test structure for characterizing multi-port static random access memory and register file arrays Grant 8,261,138 - Chang , et al. September 4, 2	2012-09-04
Test Structure For Characterizing Multi-port Static Random Access Memory And Register File Arrays App 20120212997 - Chang; Leland ; et al.	2012-08-23
Switched capacitor voltage converters Grant 8,248,152 - Dennard , et al. August 21, 2	2012-08-21
Ternary Content Addressable Memory Using Phase Change Devices App 20120120701 - Ji; Brian L. ; et al.	2012-05-17
Ternary content addressable memory using phase change devices Grant 8,120,937 - Ji , et al. February 21, 2	2012-02-21
Resistive memory devices having a not-and (NAND) structure Grant 8,107,276 - Breitwisch , et al. January 31, 2	2012-01-31
Low Voltage Signaling App 20110298440 - Chang; Leland ; et al.	2011-12-08
Content addressable memory array programmed to perform logic operations Grant 8,059,438 - Chang , et al. November 15, 2	2011-11-15
Content addressable memory array Grant 8,054,662 - Chang , et al. November 8, 2	2011-11-08
Resistive Memory Devices Having A Not-and (nand) Structure App 20110134676 - Breitwisch; Matthew J. ; et al.	2011-06-09
Content addressable memory reference clock Grant 7,948,782 - Chang , et al. May 24, 2	2011-05-24
Content Addressable Memory Array App 20110051483 - Chang; Leland ; et al.	2011-03-03
Content Addressable Memory Array Writing App 20110051485 - Chang; Leland ; et al.	2011-03-03
Content Addressable Memory Reference Clock App 20110051486 - Chang; Leland ; et al.	2011-03-03
Content Addressable Memory Array Programmed To Perform Logic Operations App 20110051482 - Chang; Leland ; et al.	2011-03-03
Silicon Carrier Structure and Method of Forming Same App 20110019368 - Andry; Paul Stephen ; et al.	2011-01-27
SerDes double rate bitline with interlock to block precharge capture Grant 7,839,715 - Chang , et al. November 23, 2	2010-11-23
Ternary Content Addressable Memory Using Phase Change Devices App 20100226161 - Ji; Brian L. ; et al.	2010-09-09
Switched Capacitor Voltage Converters App 20100214014 - Dennard; Robert H. ; et al.	2010-08-26
Content addressable memory using phase change devices Grant 7,751,217 - Lam , et al. July 6, 2	2010-07-06
SerDes double rate bitline with interlock to block precharge capture App 20100106996 - Chang; Leland ; et al.	2010-04-29
Shared Parallel Adder Tree For Executing Multiple Different Population Count Operations App 20100049779 - Blaner; Bartholomew ; et al.	2010-02-25
Hybrid static and dynamic sensing for memory arrays Grant 7,668,024 - Chang , et al. February 23, 2	2010-02-23
Content Addressable Memory Using Phase Change Devices App 20100002481 - Lam; Chung H. ; et al.	2010-01-07
System for SIMD-oriented management of register maps for map-based indirect register-file access Grant 7,631,167 - Capek , et al. December 8, 2	2009-12-08
Hybrid Static And Dynamic Sensing For Memory Arrays App 20090109780 - Chang; Leland ; et al.	2009-04-30
Sectored cache memory Grant 7,526,610 - Emma , et al. April 28, 2	2009-04-28
Scannable limited switch dynamic logic (LSDL) circuit Grant 7,501,850 - Correale, Jr. , et al. March 10, 2	2009-03-10
Methods involving memory caches Grant 7,472,226 - Emma , et al. December 30, 2	2008-12-30
Test Structure for Characterizing Multi-Port Static Random Access Memory and Register File Arrays App 20080155362 - Chang; Leland ; et al.	2008-06-26
Method, System And Program Product For Simd-oriented Management Of Register Maps For Map-based Indirect Register-file Access App 20080133874 - CAPEK; Peter G. ; et al.	2008-06-05
Method for SIMD-oriented management of register maps for map-based indirect register-file access Grant 7,360,063 - Capek , et al. April 15, 2	2008-04-15
Methods and arrangements to adjust a duty cycle Grant 7,298,193 - Agarwal , et al. November 20, 2	2007-11-20
4-to-2 carry save adder using limited switching dynamic logic Grant 7,284,029 - Belluomini , et al. October 16, 2	2007-10-16
Method, system and program product for SIMD-oriented management of register maps for map-based indirect register-file access App 20070226466 - Capek; Peter G. ; et al.	2007-09-27
Methods And Arrangements To Adjust A Duty Cycle App 20070216457 - Agarwal; Kanak B. ; et al.	2007-09-20
Computing carry-in bit to most significant bit carry save adder in current stage Grant 7,216,141 - Belluomini , et al. May 8, 2	2007-05-08
Controlled load limited switch dynamic logic circuitry Grant 7,129,754 - Ngo , et al. October 31, 2	2006-10-31
Controlled Load Limited Switch Dynamic Logic Circuitry App 20060208763 - Ngo; Hung C. ; et al.	2006-09-21
Apparatus for increasing addressability of registers within a processor App 20060190704 - Capek; Peter G. ; et al.	2006-08-24
System and method for a fused multiply-add dataflow with early feedback prior to rounding App 20060179096 - Fleischer; Bruce M. ; et al.	2006-08-10
Silicon chip carrier with conductive through-vias and method for fabricating same App 20060027934 - Edelstein; Daniel Charles ; et al.	2006-02-09
Integrated circuit chip package with formable intermediate 3D wiring structure Grant 6,952,352 - Emma , et al. October 4, 2	2005-10-04
4-to-2 carry save adder using limited switching dynamic logic App 20050102345 - Belluomini, Wendy A. ; et al.	2005-05-12
Computing carry-in bit to most significant bit carry save adder in current stage App 20050102346 - Belluomini, Wendy A. ; et al.	2005-05-12
Limited switch dynamic logic selector circuits Grant 6,873,188 - Belluomini , et al. March 29, 2	2005-03-29
Cache memory system for selectively storing directory information for a higher level cache in portions of a lower level cache Grant 6,763,432 - Charney , et al. July 13, 2	2004-07-13
Integrated circuit chip package with formable intermediate 3D wiring structure App 20040109283 - Emma, Philip G. ; et al.	2004-06-10
Limited switch dynamic logic selector circuits App 20040051560 - Belluomini, Wendy A. ; et al.	2004-03-18
Limited switch dynamic logic circuit Grant 6,690,204 - Belluomini , et al. February 10, 2	2004-02-10
Mobile modular computer App 20030154291 - Ocheltree, Kenneth Blair ; et al.	2003-08-14
Methods for caching cache tags Grant 6,311,253 - Chang , et al. October 30, 2	2001-10-30
CMOS buffer circuit having power-down feature Grant 5,570,036 - Montoye , et al. October 29, 1	1996-10-29
Apparatus for storing "Don't Care" in a content addressable memory cell Grant 5,319,590 - Montoye June 7, 1	1994-06-07
Tri state buffer circuit for dual power system Grant 5,266,849 - Kitahara , et al. November 30, 1	1993-11-30
Floating point arithmetic two cycle data flow Grant 5,212,662 - Cocanougher , et al. * May 18, 1	1993-05-18
Floating point arithmetic two cycle data flow Grant 4,999,802 - Cocanougher , et al. March 12, 1	1991-03-12
Floating point unit for calculating A=XY+Z having simultaneous multiply and add Grant 4,969,118 - Montoye , et al. November 6, 1	1990-11-06
Partial decode shifter/rotator Grant 4,931,971 - Cook , et al. June 5, 1	1990-06-05
Leading 0/1 anticipator (LZA) Grant 4,926,369 - Hokenek , et al. May 15, 1	1990-05-15

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