U.S. patent application number 13/545456 was filed with the patent office on 2013-12-05 for cut-very-last dual-epi flow.
This patent application is currently assigned to International Business Machines Corporation. The applicant listed for this patent is Veeraraghavan S. Basker, Huiming Bu, Kangguo Cheng, Balasubramanian S. Haran, Nicolas Loubet, Shom Ponoth, Stefan Schmitz, Theodorus E. Standaert, Tenko Yamashita. Invention is credited to Veeraraghavan S. Basker, Huiming Bu, Kangguo Cheng, Balasubramanian S. Haran, Nicolas Loubet, Shom Ponoth, Stefan Schmitz, Theodorus E. Standaert, Tenko Yamashita.
Application Number | 20130319613 13/545456 |
Document ID | / |
Family ID | 49448560 |
Filed Date | 2013-12-05 |
United States Patent
Application |
20130319613 |
Kind Code |
A1 |
Basker; Veeraraghavan S. ;
et al. |
December 5, 2013 |
CUT-VERY-LAST DUAL-EPI FLOW
Abstract
A method for making dual-epi FinFETs is described. The method
includes adding a first epitaxial material to an array of fins. The
method also includes covering at least a first portion of the array
of fins using a first masking material and removing the first
epitaxial material from an uncovered portion of the array of fins.
Adding a second epitaxial material to the fins in the uncovered
portion of the array of fins is included in the method. The method
also includes covering a second portion of the array of fins using
a second masking material and performing a directional etch using
the first masking material and the second masking material.
Apparatus and computer program products are also described.
Inventors: |
Basker; Veeraraghavan S.;
(Schenectady, NY) ; Bu; Huiming; (Millwood,
NY) ; Cheng; Kangguo; (Schenectady, NY) ;
Haran; Balasubramanian S.; (Watervliet, NY) ; Loubet;
Nicolas; (Guilderland, NY) ; Ponoth; Shom;
(Clifton Park, NY) ; Schmitz; Stefan; (Malta,
NY) ; Standaert; Theodorus E.; (Clifton Park, NY)
; Yamashita; Tenko; (Schenectady, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Basker; Veeraraghavan S.
Bu; Huiming
Cheng; Kangguo
Haran; Balasubramanian S.
Loubet; Nicolas
Ponoth; Shom
Schmitz; Stefan
Standaert; Theodorus E.
Yamashita; Tenko |
Schenectady
Millwood
Schenectady
Watervliet
Guilderland
Clifton Park
Malta
Clifton Park
Schenectady |
NY
NY
NY
NY
NY
NY
NY
NY
NY |
US
US
US
US
US
US
US
US
US |
|
|
Assignee: |
International Business Machines
Corporation
|
Family ID: |
49448560 |
Appl. No.: |
13/545456 |
Filed: |
July 10, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
13487413 |
Jun 4, 2012 |
|
|
|
13545456 |
|
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|
|
Current U.S.
Class: |
156/345.24 ;
156/345.3 |
Current CPC
Class: |
H01L 29/66795 20130101;
H01L 29/6681 20130101; H01L 27/0924 20130101; H01L 21/845 20130101;
H01L 27/1211 20130101; H01L 21/823821 20130101 |
Class at
Publication: |
156/345.24 ;
156/345.3 |
International
Class: |
H01L 21/308 20060101
H01L021/308 |
Claims
1-20. (canceled)
21. An apparatus comprising at least one data processor, wherein
the at least one data processor is operable to perform operations
comprising: to add a first epitaxial material to an array of fins;
to cover at least a first portion of the array of fins using a
first masking material; to remove the first epitaxial material from
an uncovered portion of the array of fins; to add a second
epitaxial material to the fins in the uncovered portion of the
array of fins; to cover a second portion of the array of fins using
a second masking material; and to perform a directional etch using
the first masking material and the second masking material.
22. The apparatus as in claim 21, where the operations further
comprise to perform a reactive ion etch.
23. The apparatus as in claim 21, where the first epitaxial
material is one of: SiGe, in-situ B-doped (ISBD) SiGe and Indium
doped SiGe.
24. The apparatus as in claim 21, where the second epitaxial
material is p-doped Si or undoped silicon.
25. The apparatus as in claim 21, where the first masking material
is one of: a nitride deposition, a thin oxide film, an oxy-nitride
film and a carbon containing silicon nitride film.
26. The apparatus as in claim 21, where the second masking material
is one of: a resist film, an organic planarizing layer, a silicon
layer containing an anti-reflection coating and a resist, and a
multi-layer stack.
27. The apparatus as in claim 21, where the operations further
comprise, in response to covering at least the first portion of the
merged array of fins using the first masking material, to remove
the first masking material from a second portion of the merged
array of fins.
28. The apparatus as in claim 21, when removing the first epitaxial
material, the operations further comprise to remove the first
epitaxial using an HCl etch.
29. The apparatus as in claim 21, when performing the directional
etch, the operations further comprise to remove at least one fin in
the array of fins.
30. The apparatus as in claim 21, where the second epitaxial
material is undoped silicon and the operations further comprise, in
response to performing the directional etch, to dope the second
epitaxial material.
31. An apparatus comprising: means for adding a first epitaxial
material to an array of fins; means for covering at least a first
portion of the array of fins using a first masking material; means
for removing the first epitaxial material from an uncovered portion
of the array of fins; means for adding a second epitaxial material
to the fins in the uncovered portion of the array of fins; means
for covering a second portion of the array of fins using a second
masking material; and means for performing a directional etch using
the first masking material and the second masking material.
32. The apparatus as in claim 31, further comprising means for
performing a reactive ion etch.
33. The apparatus as in claim 31, where the first epitaxial
material is one of: SiGe, in-situ B-doped (ISBD) SiGe and Indium
doped SiGe.
34. The apparatus as in claim 31, where the second epitaxial
material is p-doped Si or undoped silicon.
35. The apparatus as in claim 31, where the first masking material
is one of: a nitride deposition, a thin oxide film, an oxy-nitride
film and a carbon containing silicon nitride film.
36. The apparatus as in claim 31, where the second masking material
is one of: a resist film, an organic planarizing layer, a silicon
layer containing an anti-reflection coating and a resist, and a
multi-layer stack.
37. The apparatus as in claim 31, further comprising means for
removing the first masking material from a second portion of the
merged array of fins in response to covering at least the first
portion of the merged array of fins using the first masking
material.
38. The apparatus as in claim 31, where the first epitaxial
material removing means comprises means for removing the first
epitaxial using an HCl etch.
39. The apparatus as in claim 31, the the directional etch
performing means further comprises means for removing at least one
fin in the array of fins.
40. The apparatus as in claim 31, where the second epitaxial
material is undoped silicon and the apparatus further comprises
means for doping the second epitaxial material in response to
performing the directional etch.
Description
TECHNICAL FIELD
[0001] The exemplary embodiments of this invention relate generally
to field effect transistors (FETs) and, more specifically, relate
to dual-epi FETs.
BACKGROUND
[0002] This section is intended to provide a background or context.
The description herein may include concepts that could be pursued,
but are not necessarily ones that have been previously conceived or
pursued. Therefore, unless otherwise indicated herein, what is
described in this section is not prior art to the description and
claims in this application and is not admitted to be prior art by
inclusion in this section.
[0003] Semiconductors and integrated circuit chips have become
ubiquitous within many products due to their continually decreasing
cost and size. In the microelectronics industry as well as in other
industries involving construction of microscopic structures (such
as micromachines, magnetoresistive heads, etc.) there is a
continued desire to reduce the size of structural features and
microelectronic devices and/or to provide a greater amount of
circuitry for a given chip size. Miniaturization, in general,
allows for increased performance (more processing per clock cycle
and less heat generated) at lower power levels and lower cost.
[0004] Present technology is at or approaching atomic level scaling
of certain micro-devices such as logic gates, FETs and capacitors.
Circuit chips with hundreds of millions of such devices are not
uncommon. Further size reductions appear to be approaching the
physical limit of trace lines and micro-devices that are embedded
upon and within their semiconductor substrates.
BRIEF SUMMARY
[0005] In an exemplary aspect a method includes adding a first
epitaxial material to an array of fins. The method also includes
covering at least a first portion of the array of fins using a
first masking material and removing the first epitaxial material
from an uncovered portion of the array of fins. Adding a second
epitaxial material to the fins in the uncovered portion of the
array of fins is included in the method. The method also includes
covering a second portion of the array of fins using a second
masking material and performing a directional etch using the first
masking material and the second masking material.
[0006] In another exemplary aspect an apparatus includes a
processor and a memory storing program instructions. The memory and
the program instructions are configured to, with the processor,
cause the apparatus to perform actions. The actions include adding
a first epitaxial material to an array of fins. The actions also
include covering at least a first portion of the array of fins
using a first masking material and removing the first epitaxial
material from an uncovered portion of the array of fins. Adding a
second epitaxial material to the fins in the uncovered portion of
the array of fins is included in the actions. The actions also
include covering a second portion of the array of fins using a
second masking material and performing a directional etch using the
first masking material and the second masking material.
[0007] In a further exemplary aspect a computer program product
includes program instructions embodied on a tangible
computer-readable medium, execution of the program instructions
resulting in operations. The operations include adding a first
epitaxial material to an array of fins. The operations also include
covering at least a first portion of the array of fins using a
first masking material and removing the first epitaxial material
from an uncovered portion of the array of fins. Adding a second
epitaxial material to the fins in the uncovered portion of the
array of fins is included in the operations. The operations also
include covering a second portion of the array of fins using a
second masking material and performing a directional etch using the
first masking material and the second masking material.
[0008] In another exemplary aspect an apparatus includes means for
adding a first epitaxial material to an array of fins. The
apparatus also includes means for covering at least a first portion
of the array of fins using a first masking material and means for
removing the first epitaxial material from an uncovered portion of
the array of fins. Means for adding a second epitaxial material to
the fins in the uncovered portion of the array of fins is included
in the apparatus. The apparatus also includes means for covering a
second portion of the array of fins using a second masking material
and means for performing a directional etch using the first masking
material and the second masking material.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0009] The foregoing and other aspects of exemplary embodiments are
made more evident in the following Detailed Description, when read
in conjunction with the attached Drawing Figures, wherein:
[0010] FIGS. 1A and 1B, collectively referred to as FIG. 1,
illustrate a top-down view (FIG. 1A) and a cross-section view (FIG.
1B) of fin FETs created in accordance with an exemplary
embodiment.
[0011] FIGS. 2A and 2B, collectively referred to as FIG. 2,
illustrate a top-down view (FIG. 2A) and a cross-section view (FIG.
2B) of the FinFETs during a stage of creation in accordance with an
exemplary embodiment.
[0012] FIGS. 3A and 3B, collectively referred to as FIG. 3,
illustrate a top-down view (FIG. 3A) and a cross-section view (FIG.
3B) of the FinFETs during another stage of creation in accordance
with an exemplary embodiment.
[0013] FIGS. 4A and 4B, collectively referred to as FIG. 4,
illustrate a top-down view (FIG. 4A) and a cross-section view (FIG.
4B) of the FinFETs during a further stage of creation in accordance
with an exemplary embodiment.
[0014] FIGS. 5A and 5B, collectively referred to as FIG. 5,
illustrate a top-down view (FIG. 5A) and a cross-section view (FIG.
5B) of the FinFETs during another stage of creation in accordance
with an exemplary embodiment.
[0015] FIGS. 6A and 6B, collectively referred to as FIG. 6,
illustrate a top-down view (FIG. 6A) and a cross-section view (FIG.
6B) of the FinFETs during a further stage of creation in accordance
with an exemplary embodiment.
[0016] FIGS. 7A and 7B, collectively referred to as FIG. 7,
illustrate a top-down view (FIG. 7A) and a cross-section view (FIG.
7B) of the FinFETs during another stage of creation in accordance
with an exemplary embodiment.
[0017] FIGS. 8A and 8B, collectively referred to as FIG. 8,
illustrate a top-down view (FIG. 8A) and a cross-section view (FIG.
8B) of the FinFETs during a further stage of creation in accordance
with an exemplary embodiment.
[0018] FIGS. 9A and 9B, collectively referred to as FIG. 9,
illustrate a top-down view (FIG. 9A) and a cross-section view (FIG.
9B) of the FinFETs during another stage of creation in accordance
with an exemplary embodiment.
[0019] FIG. 10 shows a simplified block diagram of exemplary
electronic devices that are suitable for use in practicing various
exemplary embodiments.
[0020] FIG. 11 is a logic flow diagram that illustrates the
operation of an exemplary method, and a result of execution of
computer program instructions embodied on a computer readable
memory, in accordance with various exemplary embodiments.
[0021] FIGS. 12A and 12B, collectively referred to as FIG. 12,
illustrate a top-down view (FIG. 3A) and a cross-section view (FIG.
3B) of the FinFETs during an alternative stage of creation in
accordance with an exemplary embodiment.
DETAILED DESCRIPTION
[0022] The following abbreviations that may be found in the
specification and/or the drawing figures are defined as
follows:
[0023] B--SiGe boron-doped silicon-germanium
[0024] CMOS complementary metal-oxide semiconductor
[0025] epi epitaxial/epitaxy
[0026] FET field effect transistor
[0027] HCl hydrogen chloride
[0028] MOS metal-oxide semiconductor
[0029] NFET n-type FET
[0030] PFET p-type FET
[0031] SIT sidewall image transfer
[0032] SOI silicon-on-insulator
[0033] A field effect transistor (FET) is a transistor having a
source, a gate, and a drain. The action of the FET depends on the
flow of majority carriers along a channel between the source and
drain that runs past the gate. Current through the channel, which
is between the source and drain, may be controlled by a transverse
electric field under the gate.
[0034] As known to those skilled in the art, P-type FETs (PFETs)
turn ON to allow current flow from source to drain when the gate
terminal is at a low or negative potential with respect to the
source. When the gate potential is positive or the same as the
source, the P-type FET is OFF, and does not conduct current. On the
other hand, N-type FETs (NFETs) turn ON to allow current flow from
source to drain when the gate terminal is high or positive with
respect to the source. When the gate potential is negative or the
same as the source, the N-type FET is OFF, and does not conduct
current. Note that in each of these cases there is a threshold
voltage (such as at the gate terminal) for triggering actuation of
the FET.
[0035] More than one gate (multi-gate) can be used to more
effectively control the channel. The length of the gate determines
how fast the FET switches, and can be about the same as the length
of the channel (such as the distance between the source and drain).
Multi-gate FETs are considered to be promising candidates to scale
down complementary metal-oxide semiconductor (CMOS) FET technology.
However, such small dimensions necessitate greater control over
performance issues such as short channel effects, punch-through,
metal-oxide semiconductor (MOS) leakage current and the parasitic
resistance that is present in a multi-gate FET.
[0036] The size of FETs has been successfully reduced through the
use of one or more fin-shaped channels. A FET employing such a
channel structure may be referred to as a FinFET. Previously, CMOS
devices were substantially planar along the surface of the
semiconductor substrate, the exception being the FET gate that was
disposed over the top of the channel. Fins break from this paradigm
by using a vertical channel structure in order to maximize the
surface area of the channel that is exposed to the gate. The gate
controls the channel more strongly because it extends over more
than one side (surface) of the channel. For example, the gate can
enclose three surfaces of the three-dimensional channel, rather
than being disposed only across the top surface of the traditional
planar channel.
[0037] One technique for affecting the threshold voltage (such as
increasing the threshold voltage, encouraging a more constant
threshold voltage over different gate lengths) is to use locally
implanted dopants under the gate edge(s). This is referred to as a
"halo" implant. As non-limiting examples, the halo implant may
include arsenic, phosphorous, boron and/or indium.
[0038] Silicon-on-insulator (SOI) wafers have been used to exploit
the improved quality of monocrystalline silicon provided thereby in
an active layer formed on an insulator over a bulk silicon
"handling" substrate. Similar attributes can be developed in
similar structures of other semiconductor materials and alloys
thereof. The improved quality of the semiconductor material of the
active layer allows transistors and other devices to be scaled to
extremely small sizes with good uniformity of electrical
properties.
[0039] An exemplary embodiment is a cut-very-last processing flow
which enables dual-epi for FinFET. The epi-merge of the fins in the
source/drain (S/D) regions is very challenging if independent epi
control is used for NFET and PFET. In addition, independent epi
control may require mitigation of any unwanted epi-shorting between
devices in the SRAM. In contrast, the new processing flow is a
single-mask solution enabling dual-epi and resolves any
epi-shorting that might occur between various devices.
[0040] In the cut-very-last processing flow, dummy fins remain
until the end of device fabrication and are cut in the last stage
of the device fabrication (after source/drain formation). However,
in a conventional finFET process, fins are defined by sidewall
image transfer (SIT) and unwanted dummy fins are cut (removed)
immediately following SIT. Device fabrication such as gate, spacer,
source/drain are then formed after fin cut.
[0041] FIGS. 1A and 1B illustrate a non-limiting example of finFETs
created in accordance with an exemplary embodiment. In the top-down
view of FIG. 1A, NFETs 110 are shown with P-doped Si 115. The PFETs
120 have BSiGe 125. Layered on top of the FinFETs 110, 120 is gate
102.
[0042] Shown FIG. 1B (the cross-section view), the FinFETs 110, 120
are located on a substrate 140. Each FinFET includes a cap 128. The
FinFETs 110, 120 are regularly spaced with the distance 135 between
the PFETs 120 and their neighbor FinFET (either the other PFET 120
or an NFET 110) is twice the fin pitch 130 (or distance between
adjacent fins of NFETs 110).
[0043] FIGS. 2A and 2B illustrate the finFETs 110, 120 during a
stage of creation in accordance with an exemplary embodiment. At
this stage, an array of fins 104 (which will become FinFETs 110,
120) is positioned on the substrate 140. A gate reactive ion etch
(RIE) may be used to ensure the array of fins 104 is clean of
unwanted debris. Note that for a regular array of fin 104, the fins
104 are evenly spaced such that the distance between adjacent fins
(or fin pitch) 130 is the same for all fins 104.
[0044] FIGS. 3A and 3B illustrate the finFETs 110, 120 during
another stage of creation in accordance with an exemplary
embodiment. At this stage, a first epitaxial material (BSiGe 125)
is added to merge all fins 104.
[0045] FIGS. 4A and 4B illustrate the finFETs 110, 120 during a
further stage of creation in accordance with an exemplary
embodiment. Here, a thin nitride deposition 410 is layered over the
fins 104 and the BSiGe 125. This may be done using an in-situ
radical assisted deposition (iRAD).
[0046] FIGS. 5A and 5B illustrate the finFETs 110, 120 during
another stage of creation in accordance with an exemplary
embodiment. At this stage, the NFET 110 areas are exposed by
removing the nitride deposition 410 covering these areas.
[0047] FIGS. 6A and 6B illustrate the finFETs 110, 120 during a
further stage of creation in accordance with an exemplary
embodiment. During this stage, the BSiGe 125 is removed from the
exposed NFET 110 areas. As a non-limiting example, the BSiGe 125
may be removed using an HCl etch.
[0048] FIGS. 7A and 7B illustrate the finFETs 110, 120 during
another stage of creation in accordance with an exemplary
embodiment. Here, a second epitaxial material (P-doped Si-115) is
added to merge the NFET 110 fins 104. Note that the stages shown in
FIGS. 6 and 7 can be performed in a single step on
epi-platform.
[0049] FIGS. 8A and 8B illustrate the finFETs 110, 120 during a
further stage of creation in accordance with an exemplary
embodiment. The active areas are defined by adding a masking
material 810 which will protect some fins while unwanted dummy fins
are not protected by this mask.
[0050] FIG. 9 illustrates the finFETs 110, 120 during another stage
of creation in accordance with an exemplary embodiment. In this
stage, a direction etch (or cut) is made using the masking material
810 (shown in FIGS. 8A and 8B) and the nitride deposition 410 as
masking materials. This removes the non-active BSiGe 125, P-Doped
Si 115 and some of the non-masked fins 104. The etch also removes
the masking material 810 and the non-masked nitride deposition 410.
The cut may (or may not) also remove a portion of the substrate
140.
[0051] Note that in a further exemplary embodiment the finFETs 110,
120 may be constructed with the locations of the PFETs 120 and
NFETs 110 switched. Accordingly, the epitaxial material (such as
BSiGe 125 and P-Doped Si 115) may also be switched as well as any
accompanying changes to the masking material (masking material 810
and nitride deposition 410).
[0052] The epitaxial material (BSiGe 125 and P-Doped Si 115) may be
of any type suitable to the local technical environment and may be
implemented using any suitable technology. Likewise, the masking
material (masking material 810 and nitride deposition 410) may be
of any type suitable to the local technical environment and may be
implemented using any suitable technology.
[0053] FIGS. 12A and 12B illustrate the finFETs 110, 120 during an
alternative stage of creation in accordance with an exemplary
embodiment. At this stage, which would replace the stage shown in
FIGS. 3A and 3B, the first epitaxial material (BSiGe 125) is added
to the fins 104. While the epitaxial growth is sufficient to be on
the fins, the epitaxial material does not physically merge the
fins.
[0054] In another embodiment, additional spacer material may be
added to cover and isolate "dummy` channels underneath the gate
that may remain after the cut. These channels are undoped and are
invisible from a parasitic point of view.
[0055] By performing the cut last, this enables a uniform gate
profile and extension across all fins. Accordingly, the voltage
threshold (Vt) to width dependence is improved.
[0056] An exemplary cut-very-last process resolves unwanted
epi-shorting between devices as well as wrap-around of epi at gate
line-ends, especially SRAM. The cut-very-last approach uses
dummy/sacrificial fins. These dummy fins are placed at every N-to-P
transition (boundary between N-FETs and P-FETs). Thus, the spacing
of pull-ups (PUs), pass-down and pass-gate devices in the SRAM is
at 2.times.fin pitch.
[0057] The P-Doped Si 115 may be slightly thicker for the NFET
extension/P-doped Si; however, the lateral HCl etch provides
minimal end-device impact. Additionally, the total spacer increase
for the S/D may be accounted for.
[0058] Reference is made to FIG. 10 for illustrating a simplified
block diagram of various electronic devices and apparatus that are
suitable for use in practicing exemplary embodiments. For example,
computer 1010 may be used to control a lithography process in
accordance with an exemplary embodiment.
[0059] The computer 1010 includes a controller, such as a computer
or a data processor (DP) 1014 and a computer-readable memory medium
embodied as a memory (MEM) 1016 that stores a program of computer
instructions (PROG) 1018.
[0060] The PROGs 1018 is assumed to include program instructions
that, when executed by the associated DP 1014, enable the device to
operate in accordance with exemplary embodiments, as will be
discussed below in greater detail.
[0061] That is, various exemplary embodiments may be implemented at
least in part by computer software executable by the DP 1014 of the
computer 1010, or by hardware, or by a combination of software and
hardware (and firmware).
[0062] The computer 1010 may also include dedicated processors, for
example lithography controller 1015.
[0063] The computer readable MEM 1016 may be of any type suitable
to the local technical environment and may be implemented using any
suitable data storage technology, such as semiconductor based
memory devices, flash memory, magnetic memory devices and systems,
optical memory devices and systems, fixed memory and removable
memory. The DP 1014 may be of any type suitable to the local
technical environment, and may include one or more of general
purpose computers, special purpose computers, microprocessors,
digital signal processors (DSPs) and processors based on a
multicore processor architecture, as non-limiting examples.
[0064] The exemplary embodiments, as discussed herein and as
particularly described with respect to exemplary methods, may be
implemented in conjunction with a program storage device (e.g., at
least one memory) readable by a machine, tangibly embodying a
program of instructions (e.g., a program or computer program)
executable by the machine for performing operations. The operations
comprise steps of utilizing the exemplary embodiments or steps of
the method.
[0065] Based on the foregoing it should be apparent that various
exemplary embodiments provide a method, apparatus and computer
program(s) to make dual-epi FinFETs.
[0066] FIG. 11 is a logic flow diagram that illustrates the
operation of a method, and a result of execution of computer
program instructions (such as PROG 1018), in accordance with
exemplary embodiments. In accordance with these exemplary
embodiments a method performs, at Block 1110, a step of adding a
first epitaxial material to an array of fins. A step of covering at
least a first portion of the array of fins using a first masking
material is performed by the method at Block 1120. The method
performs a step of removing the first epitaxial material from an
uncovered portion of the array of fins at Block 1130. At Block
1140, the method performs a step of adding a second epitaxial
material to the fins in the uncovered portion of the array of fins.
A step of covering a second portion of the array of fins using a
second masking material is performed by the method at Block 1150.
The method performs a step of performing a directional etch using
the first masking material and the second masking material at Block
1160.
[0067] The various blocks shown in FIG. 11 may be viewed as method
steps, and/or as operations that result from operation of computer
program code, and/or as a plurality of coupled logic circuit
elements constructed to carry out the associated function(s).
[0068] An exemplary embodiment provides a method for making
dual-epi FinFETs. The method includes adding a first epitaxial
material to an array of fins. The method also includes covering at
least a first portion of the array of fins using a first masking
material and removing the first epitaxial material from an
uncovered portion of the array of fins. Adding a second epitaxial
material to the fins in the uncovered portion of the array of fins
is included in the method. The method also includes covering a
second portion of the array of fins using a second masking material
and performing a directional etch using the first masking material
and the second masking material.
[0069] In a further exemplary embodiment of the method above, the
method also includes performing a reactive ion etch.
[0070] In another exemplary embodiment of any one of the methods
above, the first epitaxial material is SiGe, in-situ B-doped (ISBD)
SiGe and/or Indium doped SiGe.
[0071] In a further exemplary embodiment of any one of the methods
above, the second epitaxial material is p-doped Si or undoped
silicon. If undoped silicon is used, it may be doped after the cut,
for example, using Arsenic.
[0072] In another exemplary embodiment of any one of the methods
above, the first masking material is a nitride deposition, a thin
oxide film, an oxy-nitride film or a carbon containing silicon
nitride film.
[0073] In a further exemplary embodiment of any one of the methods
above, the second masking material is a resist film, an organic
planarizing layer, a silicon layer containing an anti-reflection
coating and a resist, and/or a multi-layer stack.
[0074] In another exemplary embodiment of any one of the methods
above, the method also includes, in response to covering at least
the first portion of the merged array of fins using the first
masking material, removing the first masking material from a second
portion of the merged array of fins.
[0075] In a further exemplary embodiment of any one of the methods
above, removing the first epitaxial material includes removing the
first epitaxial using an HCl etch.
[0076] In another exemplary embodiment of any one of the methods
above, removing the first epitaxial material and adding the second
epitaxial material is performed in a single step on an
epi-platform.
[0077] In a further exemplary embodiment of any one of the methods
above, performing the directional etch removes at least one fin in
the array of fins.
[0078] Another exemplary embodiment provides an apparatus for
making dual-epi FinFETs. The apparatus includes a processor and a
memory storing program instructions. The memory and the program
instructions are configured to, with the processor, cause the
apparatus to perform actions. The actions include adding a first
epitaxial material to an array of fins. The actions also include
covering at least a first portion of the array of fins using a
first masking material and removing the first epitaxial material
from an uncovered portion of the array of fins. Adding a second
epitaxial material to the fins in the uncovered portion of the
array of fins is included in the actions. The actions also include
covering a second portion of the array of fins using a second
masking material and performing a directional etch using the first
masking material and the second masking material.
[0079] In a further exemplary embodiment of the apparatus above,
the actions also include performing a reactive ion etch.
[0080] In another exemplary embodiment of any one of the apparatus
above, the first epitaxial material is SiGe, in-situ B-doped (ISBD)
SiGe and/or Indium doped SiGe.
[0081] In a further exemplary embodiment of any one of the
apparatus above, the second epitaxial material is p-doped Si or
undoped silicon. If undoped silicon is used, it may be doped after
the cut, for example, using Arsenic.
[0082] In another exemplary embodiment of any one of the apparatus
above, the first masking material is a nitride deposition, a thin
oxide film, an oxy-nitride film or a carbon containing silicon
nitride film.
[0083] In a further exemplary embodiment of any one of the
apparatus above, the second masking material is a resist film, an
organic planarizing layer, a silicon layer containing an
anti-reflection coating and a resist, and/or a multi-layer
stack.
[0084] In another exemplary embodiment of any one of the apparatus
above, the actions also include, in response to covering at least
the first portion of the merged array of fins using the first
masking material, removing the first masking material from a second
portion of the merged array of fins.
[0085] In a further exemplary embodiment of any one of the
apparatus above, removing the first epitaxial material includes
removing the first epitaxial using an HCl etch.
[0086] In another exemplary embodiment of any one of the apparatus
above, removing the first epitaxial material and adding the second
epitaxial material is performed in a single step on an
epi-platform.
[0087] In a further exemplary embodiment of any one of the
apparatus above, performing the directional etch removes at least
one fin in the array of fins.
[0088] In another exemplary embodiment of any one of the apparatus
above, the apparatus is embodied in an application-specific
integrated circuit.
[0089] In a further exemplary embodiment of any one of the
apparatus above, the apparatus is embodied in an integrated
circuit.
[0090] Another exemplary embodiment provides a computer program
product for making dual-epi FinFETs. The computer program product
includes program instructions embodied on a tangible
computer-readable medium, execution of the program instructions
resulting in operations. The operations include adding a first
epitaxial material to an array of fins. The operations also include
covering at least a first portion of the array of fins using a
first masking material and removing the first epitaxial material
from an uncovered portion of the array of fins. Adding a second
epitaxial material to the fins in the uncovered portion of the
array of fins is included in the operations. The operations also
include covering a second portion of the array of fins using a
second masking material and performing a directional etch using the
first masking material and the second masking material.
[0091] In a further exemplary embodiment of the computer program
product above, the operations also include performing a reactive
ion etch.
[0092] In another exemplary embodiment of any one of the computer
program products above, the first epitaxial material is SiGe,
in-situ B-doped (ISBD) SiGe and/or Indium doped SiGe.
[0093] In a further exemplary embodiment of any one of the computer
program products above, the second epitaxial material is p-doped Si
or undoped silicon. If undoped silicon is used, it may be doped
after the cut, for example, using Arsenic.
[0094] In another exemplary embodiment of any one of the computer
program products above, the first masking material is a nitride
deposition, a thin oxide film, an oxy-nitride film or a carbon
containing silicon nitride film.
[0095] In a further exemplary embodiment of any one of the computer
program products above, the second masking material is a resist
film, an organic planarizing layer, a silicon layer containing an
anti-reflection coating and a resist, and/or a multi-layer
stack.
[0096] In another exemplary embodiment of any one of the computer
program products above, the operations also include, in response to
covering at least the first portion of the merged array of fins
using the first masking material, removing the first masking
material from a second portion of the merged array of fins.
[0097] In a further exemplary embodiment of any one of the computer
program products above, removing the first epitaxial material
includes removing the first epitaxial using an HCl etch.
[0098] In another exemplary embodiment of any one of the computer
program products above, removing the first epitaxial material and
adding the second epitaxial material is performed in a single step
on an epi-platform.
[0099] In a further exemplary embodiment of any one of the computer
program products above, performing the directional etch removes at
least one fin in the array of fins.
[0100] In another exemplary embodiment of any one of the computer
program products above, the computer-readable medium is a
non-transitory computer readable medium (e.g., CD-ROM, RAM, flash
memory, etc.).
[0101] In a further exemplary embodiment of any one of the computer
program products above, the computer-readable medium is a storage
medium.
[0102] Another exemplary embodiment provides an apparatus for
making dual-epi FinFETs. The apparatus includes means for adding a
first epitaxial material to an array of fins The apparatus also
includes means for covering at least a first portion of the array
of fins using a first masking material and means for removing the
first epitaxial material from an uncovered portion of the array of
fins. Means for adding a second epitaxial material to the fins in
the uncovered portion of the array of fins is included in the
apparatus. The apparatus also includes means for covering a second
portion of the array of fins using a second masking material and
means for performing a directional etch using the first masking
material and the second masking material.
[0103] In a further exemplary embodiment of the apparatus above,
the apparatus also includes means for performing a reactive ion
etch.
[0104] In another exemplary embodiment of any one of the apparatus
above, the first epitaxial material is SiGe, in-situ B-doped (ISBD)
SiGe and/or Indium doped SiGe.
[0105] In a further exemplary embodiment of any one of the
apparatus above, the second epitaxial material is p-doped Si or
undoped silicon. If undoped silicon is used, it may be doped after
the cut, for example, using Arsenic.
[0106] In another exemplary embodiment of any one of the apparatus
above, the first masking material is a nitride deposition, a thin
oxide film, an oxy-nitride film or a carbon containing silicon
nitride film.
[0107] In a further exemplary embodiment of any one of the
apparatus above, the second masking material is a resist film, an
organic planarizing layer, a silicon layer containing an
anti-reflection coating and a resist, and/or a multi-layer
stack.
[0108] In another exemplary embodiment of any one of the apparatus
above, the apparatus also includes means for removing the first
masking material from a second portion of the merged array of fins
in response to covering at least the first portion of the merged
array of fins using the first masking material.
[0109] In a further exemplary embodiment of any one of the
apparatus above, the means for removing the first epitaxial
material includes means for removing the first epitaxial using an
HCl etch.
[0110] In another exemplary embodiment of any one of the apparatus
above, where the means for removing the first epitaxial material
and the means for adding the second epitaxial material are
configured to operate in a single step on an epi-platform.
[0111] In a further exemplary embodiment of any one of the
apparatus above, performing the directional etch removes at least
one fin in the array of fins.
[0112] Any use of the terms "connected", "coupled" or variants
thereof should be interpreted to indicate any such connection or
coupling, direct or indirect, between the identified elements. As a
non-limiting example, one or more intermediate elements may be
present between the "coupled" elements. The connection or coupling
between the identified elements may be, as non-limiting examples,
physical, electrical, magnetic, logical or any suitable combination
thereof in accordance with the described exemplary embodiments. As
non-limiting examples, the connection or coupling may comprise one
or more printed electrical connections, wires, cables, mediums or
any suitable combination thereof.
[0113] Generally, various exemplary embodiments can be implemented
in different mediums, such as software, hardware, logic, special
purpose circuits or any combination thereof. As a non-limiting
example, some aspects may be implemented in software which may be
run on a computing device, while other aspects may be implemented
in hardware.
[0114] The foregoing description has provided by way of exemplary
and non-limiting examples a full and informative description of the
best method and apparatus presently contemplated by the inventors
for carrying out various exemplary embodiments. However, various
modifications and adaptations may become apparent to those skilled
in the relevant arts in view of the foregoing description, when
read in conjunction with the accompanying drawings and the appended
claims. However, all such and similar modifications will still fall
within the scope of the teachings of the exemplary embodiments.
[0115] Furthermore, some of the features of the preferred
embodiments could be used to advantage without the corresponding
use of other features. As such, the foregoing description should be
considered as merely illustrative of the principles, and not in
limitation thereof.
* * * * *