Bu; Huiming

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bu; Huiming.The latest application filed is for "enabling anneal for reliability improvement and multi-vt with interfacial layer regrowth suppression".

Company Profile

46.101.99

Bu; Huiming - Glenmont NY
Bu; Huiming - Millwood NY
Bu; Huiming - Milwood NY
Bu; Huiming - Albany NY
Bu; Huiming - Hopewell Junction NY US
Bu; Huiming - Ossining NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Enabling Anneal For Reliability Improvement And Multi-vt With Interfacial Layer Regrowth Suppression App 20220238682 - Bao; Ruqiang ; et al.	2022-07-28
Enabling anneal for reliability improvement and multi-Vt with interfacial layer regrowth suppression Grant 11,329,136 - Bao , et al. May 10, 2	2022-05-10
Forming A Sacrificial Liner For Dual Channel Devices App 20220069118 - Bu; Huiming ; et al.	2022-03-03
Forming a sacrificial liner for dual channel devices Grant 11,189,729 - Bu , et al. November 30, 2	2021-11-30
Interface-less contacts to source/drain regions and gate electrode over active portion of device Grant 11,139,385 - Wang , et al. October 5, 2	2021-10-05
Forming a sacrificial liner for dual channel devices Grant 11,094,824 - Bu , et al. August 17, 2	2021-08-17
Precise junction placement in vertical semiconductor devices using etch stop layers Grant 11,088,278 - Bu , et al. August 10, 2	2021-08-10
Integrating a junction field effect transistor into a vertical field effect transistor Grant 11,011,513 - Anderson , et al. May 18, 2	2021-05-18
Conformal doping for punch through stopper in fin field effect transistor devices Grant 10,937,867 - Bu , et al. March 2, 2	2021-03-02
Semiconductor device with mitigated local layout effects Grant 10,892,181 - Zhou , et al. January 12, 2	2021-01-12
Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs Grant 10,811,528 - Ebrish , et al. October 20, 2	2020-10-20
Electrostatic discharge devices and methods of manufacture Grant 10,748,893 - Bu , et al. A	2020-08-18
Integration of electrostatic discharge protection into vertical fin technology Grant 10,741,544 - Anderson , et al. A	2020-08-11
Conformal doping for punch through stopper in fin field effect transistor devices Grant 10,741,647 - Bu , et al. A	2020-08-11
Method Of Fin Oxidation By Flowable Oxide Fill And Steam Anneal To Mitigate Local Layout Effects App 20200203214 - Zhou; Huimei ; et al.	2020-06-25
Fin isolation to mitigate local layout effects Grant 10,685,866 - Zhou , et al.	2020-06-16
Method of fin oxidation by flowable oxide fill and steam anneal to mitigate local layout effects Grant 10,658,224 - Zhou , et al.	2020-05-19
Integration Of Electrostatic Discharge Protection Into Vertical Fin Technology App 20200152619 - Anderson; Brent A. ; et al.	2020-05-14
Bottom source/drain silicidation for vertical field-effect transistor (FET) Grant 10,629,443 - Anderson , et al.	2020-04-21
Forming A Sacrificial Liner For Dual Channel Devices App 20200091336 - Bu; Huiming ; et al.	2020-03-19
Forming a sacrificial liner for dual channel devices Grant 10,593,802 - Bu , et al.	2020-03-17
Fin Oxidation By Flowable Oxide Fill And Steam Anneal To Mitigate Local Layout Effects App 20200083089 - Zhou; Huimei ; et al.	2020-03-12
Fin Isolation To Mitigate Local Layout Effects App 20200083088 - Zhou; Huimei ; et al.	2020-03-12
Forming A Sacrificial Liner For Dual Channel Devices App 20200083364 - Bu; Huiming ; et al.	2020-03-12
Integrating A Junction Field Effect Transistor Into A Vertical Field Effect Transistor App 20200066711 - Anderson; Brent A. ; et al.	2020-02-27
Vertical transistor device Grant 10,573,727 - Anderson , et al. Feb	2020-02-25
Fin field-effect transistor for input/output device integrated with nanosheet field-effect transistor Grant 10,522,636 - Yeung , et al. Dec	2019-12-31
Forming a sacrificial liner for dual channel devices Grant 10,510,892 - Bu , et al. Dec	2019-12-17
Integrating a junction field effect transistor into a vertical field effect transistor Grant 10,504,889 - Anderson , et al. Dec	2019-12-10
Enabling Anneal For Reliability Improvement And Multi-vt With Interfacial Layer Regrowth Suppression App 20190371903 - Bao; Ruqiang ; et al.	2019-12-05
Interface-less Contacts To Source/drain Regions And Gate Electrode Over Active Portion Of Device App 20190355829 - Wang; Junli ; et al.	2019-11-21
Conformal Doping For Punch Through Stopper In Fin Field Effect Transistor Devices App 20190341458 - Bu; Huiming ; et al.	2019-11-07
Conformal Doping For Punch Through Stopper In Fin Field Effect Transistor Devices App 20190341457 - Bu; Huiming ; et al.	2019-11-07
Conformal doping for punch through stopper in fin field effect transistor devices Grant 10,453,922 - Bu , et al. Oc	2019-10-22
Two Step Fin Etch and Reveal for VTFETs and High Breakdown LDVTFETs App 20190296142 - Ebrish; Mona ; et al.	2019-09-26
Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process Grant 10,418,462 - Anderson , et al. Sept	2019-09-17
Vertical FET structure Grant 10,347,759 - Anderson , et al. July 9, 2	2019-07-09
Fin Field-effect Transistor For Input/output Device Integrated With Nanosheet Field-effect Transistor App 20190198629 - YEUNG; CHUN WING ; et al.	2019-06-27
Forming eDRAM unit cell with VFET and via capacitance Grant 10,319,852 - Anderson , et al.	2019-06-11
Forming a sacrificial liner for dual channel devices Grant 10,312,370 - Bu , et al.	2019-06-04
Electrostatic Discharge Devices And Methods Of Manufacture App 20190157260 - BU; Huiming ; et al.	2019-05-23
Fin field-effect transistor for input/output device integrated with nanosheet field-effect transistor Grant 10,297,667 - Yeung , et al.	2019-05-21
HDP fill with reduced void formation and spacer damage Grant 10,297,506 - Bu , et al.	2019-05-21
Precise Junction Placement In Vertical Semiconductor Devices Using Etch Stop Layers App 20190148545 - Bu; Huiming ; et al.	2019-05-16
Electrostatic Discharge Protection Using Vertical Fin Cmos Technology App 20190131292 - Anderson; Brent A. ; et al.	2019-05-02
Electrostatic discharge protection using vertical fin CMOS technology Grant 10,276,558 - Anderson , et al.	2019-04-30
Precise junction placement in vertical semiconductor devices using etch stop layers Grant 10,249,754 - Bu , et al.	2019-04-02
Methods and structures for forming field-effect transistors (FETs) with low-k spacers Grant 10,229,983 - Bu , et al.	2019-03-12
Electrostatic discharge devices and methods of manufacture Grant 10,229,905 - Bu , et al.	2019-03-12
Precise junction placement in vertical semiconductor devices using etch stop layers Grant 10,224,429 - Bu , et al.	2019-03-05
Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process Grant 10,211,316 - Anderson , et al. Feb	2019-02-19
Electrostatic discharge devices and methods of manufacture Grant 10,157,908 - Bu , et al. Dec	2018-12-18
Method for making a dipole-based contact structure to reduce the metal-semiconductor contact resistance in MOSFETs Grant 10,153,201 - Bu , et al. Dec	2018-12-11
Vertical transistor device Grant 10,141,426 - Anderson , et al. Nov	2018-11-27
Hdp Fill With Reduced Void Formation And Spacer Damage App 20180323110 - Bu; Huiming ; et al.	2018-11-08
HDP fill with reduced void formation and spacer damage Grant 10,083,861 - Bu , et al. September 25, 2	2018-09-25
Vertical Fet Structure App 20180248037 - ANDERSON; Brent A. ; et al.	2018-08-30
FORMING eDRAM UNIT CELL WITH VFET AND VIA CAPACITANCE App 20180211963 - Anderson; Brent A. ; et al.	2018-07-26
Precise Junction Placement In Vertical Semiconductor Devices Using Etch Stop Layers App 20180182892 - Bu; Huiming ; et al.	2018-06-28
Vertical FET structure Grant 10,002,962 - Anderson , et al. June 19, 2	2018-06-19
HDP fill with reduced void formation and spacer damage Grant 10,002,792 - Bu , et al. June 19, 2	2018-06-19
Forming eDRAM unit cell with VFET and via capacitance Grant 9,991,267 - Anderson , et al. June 5, 2	2018-06-05
Precise junction placement in vertical semiconductor devices using etch stop layers Grant 9,954,101 - Bu , et al. April 24, 2	2018-04-24
Dielectric isolated SiGe fin on bulk substrate Grant 9,947,748 - Bu , et al. April 17, 2	2018-04-17
Dielectric isolated SiGe fin on bulk substrate Grant 9,941,175 - Bu , et al. April 10, 2	2018-04-10
HDP fill with reduced void formation and spacer damage Grant 9,935,003 - Bu , et al. April 3, 2	2018-04-03
Forming A Sacrificial Liner For Dual Channel Devices App 20180090606 - Bu; Huiming ; et al.	2018-03-29
Electrostatic Discharge Devices And Methods Of Manufacture App 20180090484 - BU; Huiming ; et al.	2018-03-29
Forming A Sacrificial Liner For Dual Channel Devices App 20180090599 - Bu; Huiming ; et al.	2018-03-29
Forming A Sacrificial Liner For Dual Channel Devices App 20180090604 - Bu; Huiming ; et al.	2018-03-29
HDP fill with reduced void formation and spacer damage Grant 9,929,057 - Bu , et al. March 27, 2	2018-03-27
Silicidation Of Bottom Source/drain Sheet Using Pinch-off Sacrificial Spacer Process App 20180033868 - ANDERSON; Brent A. ; et al.	2018-02-01
Silicidation Of Bottom Source/drain Sheet Using Pinch-off Sacrificial Spacer Process App 20180019323 - ANDERSON; Brent A. ; et al.	2018-01-18
Forming A Silicon Based Layer In A Trench To Prevent Corner Rounding App 20180005826 - JACOB; Ajey P. ; et al.	2018-01-04
Silicidation Of Bottom Source/drain Sheet Using Pinch-off Sacrificial Spacer Process App 20170373170 - ANDERSON; Brent A. ; et al.	2017-12-28
Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process Grant 9,853,127 - Anderson , et al. December 26, 2	2017-12-26
Precise Junction Placement In Vertical Semiconductor Devices Using Etch Stop Layers App 20170365714 - Bu; Huiming ; et al.	2017-12-21
Precise Junction Placement In Vertical Semiconductor Devices Using Etch Stop Layers App 20170365712 - Bu; Huiming ; et al.	2017-12-21
Bottom Source/drain Silicidation For Vertical Field-effect Transistor (fet) App 20170323794 - Anderson; Brent A. ; et al.	2017-11-09
Vertical Fet Structure App 20170317210 - Anderson; Brent A. ; et al.	2017-11-02
Bottom Source/drain Silicidation For Vertical Field-effect Transistor (fet) App 20170316945 - ANDERSON; BRENT A. ; et al.	2017-11-02
Bottom source/drain silicidation for vertical field-effect transistor (FET) Grant 9,805,935 - Anderson , et al. October 31, 2	2017-10-31
Hdp Fill With Reduced Void Formation And Spacer Damage App 20170287776 - Bu; Huiming ; et al.	2017-10-05
Hdp Fill With Reduced Void Formation And Spacer Damage App 20170287785 - Bu; Huiming ; et al.	2017-10-05
Forming a sacrificial liner for dual channel devices Grant 9,773,893 - Bu , et al. September 26, 2	2017-09-26
Electrostatic Discharge Devices And Methods Of Manufacture App 20170263601 - BU; Huiming ; et al.	2017-09-14
Vertical Transistor Device App 20170229558 - Anderson; Brent A. ; et al.	2017-08-10
Vertical Transistor Device App 20170229556 - Anderson; Brent A. ; et al.	2017-08-10
Cutting fins and gates in CMOS devices Grant 9,721,848 - Bu , et al. August 1, 2	2017-08-01
HDP fill with reduced void formation and spacer damage Grant 9,721,834 - Bu , et al. August 1, 2	2017-08-01
Electrostatic discharge devices and methods of manufacture Grant 9,704,848 - Bu , et al. July 11, 2	2017-07-11
Bottom Source/drain Silicidation For Vertical Field-effect Transistor (fet) App 20170194155 - Anderson; Brent A. ; et al.	2017-07-06
Polysilicon resistor formation in silicon-on-insulator replacement metal gate finFET processes Grant 9,698,061 - Basker , et al. July 4, 2	2017-07-04
Hdp Fill With Reduced Void Formation And Spacer Damage App 20170148668 - Bu; Huiming ; et al.	2017-05-25
Advanced Mosfet Contact Structure To Reduce Metal-semiconductor Interface Resistance App 20170133265 - Bu; Huiming ; et al.	2017-05-11
DIELECTRIC ISOLATED SiGe FIN ON BULK SUBSTRATE App 20170133463 - Bu; Huiming ; et al.	2017-05-11
Conformal Doping For Punch Through Stopper In Fin Field Effect Transistor Devices App 20170117365 - Bu; Huiming ; et al.	2017-04-27
DIELECTRIC ISOLATED SiGe FIN ON BULK SUBSTRATE App 20170098584 - Bu; Huiming ; et al.	2017-04-06
DIELECTRIC ISOLATED SiGe FIN ON BULK SUBSTRATE App 20170098697 - Bu; Huiming ; et al.	2017-04-06
Hdp Fill With Reduced Void Formation And Spacer Damage App 20170076987 - Bu; Huiming ; et al.	2017-03-16
Dielectric isolated SiGe fin on bulk substrate Grant 9,595,599 - Bu , et al. March 14, 2	2017-03-14
Dipole-based contact structure to reduce metal-semiconductor contact resistance in MOSFETs Grant 9,589,851 - Bu , et al. March 7, 2	2017-03-07
Conformal doping for punch through stopper in fin field effect transistor devices Grant 9,583,563 - Bu , et al. February 28, 2	2017-02-28
Recessed metal liner contact with copper fill Grant 9,570,574 - Adusumilli , et al. February 14, 2	2017-02-14
HDP fill with reduced void formation and spacer damage Grant 9,558,995 - Bu , et al. January 31, 2	2017-01-31
Dipole-Based Contact Structure to Reduce Metal-Semiconductor Contact Resistance in MOSFETs App 20170018463 - Bu; Huiming ; et al.	2017-01-19
Asymmetric multi-gate FinFET Grant 9,548,379 - Basker , et al. January 17, 2	2017-01-17
Asymmetric multi-gate finFET Grant 9,543,435 - Basker , et al. January 10, 2	2017-01-10
Hdp Fill With Reduced Void Formation And Spacer Damage App 20160379873 - Bu; Huiming ; et al.	2016-12-29
Hdp Fill With Reduced Void Formation And Spacer Damage App 20160380078 - Bu; Huiming ; et al.	2016-12-29
Polysilicon resistor formation in silicon-on-insulator replacement metal gate finFET processes Grant 9,514,998 - Basker , et al. December 6, 2	2016-12-06
Polysilicon resistor formation in silicon-on-insulator replacement metal gate finFET processes Grant 9,502,313 - Basker , et al. November 22, 2	2016-11-22
Polysilicon Resistor Formation In Silicon-on-insulator Replacement Metal Gate Finfet Processes App 20160336239 - Basker; Veeraraghavan S. ; et al.	2016-11-17
Polysilicon Resistor Formation In Silicon-on-insulator Replacement Metal Gate Finfet Processes App 20160336238 - Basker; Veeraraghavan S. ; et al.	2016-11-17
Polysilicon Resistor Formation In Silicon-on-insulator Replacement Metal Gate Finfet Processes App 20160336348 - Basker; Veeraraghavan S. ; et al.	2016-11-17
Recessed metal liner contact with copper fill Grant 9,496,225 - Adusumilli , et al. November 15, 2	2016-11-15
Electrostatic Discharge Devices And Methods Of Manufacture App 20160315076 - BU; Huiming ; et al.	2016-10-27
Electrostatic discharge devices and methods of manufacture Grant 9,425,184 - Bu , et al. August 23, 2	2016-08-23
Electrostatic discharge devices and methods of manufacture Grant 9,281,303 - Bu , et al. March 8, 2	2016-03-08
Electrostatic Discharge Devices And Methods Of Manufacture App 20160035718 - BU; Huiming ; et al.	2016-02-04
Electrostatic Discharge Devices And Methods Of Manufacture App 20150348958 - BU; Huiming ; et al.	2015-12-03
Method of making a semiconductor device including an all around gate Grant 9,082,788 - Loubet , et al. July 14, 2	2015-07-14
Electrostatic discharge resistant diodes Grant 9,064,885 - Bu , et al. June 23, 2	2015-06-23
Electrostatic discharge resistant diodes Grant 9,054,124 - Bu , et al. June 9, 2	2015-06-09
Transistors Having Multiple Lateral Channel Dimensions App 20150145042 - Bu; Huiming ; et al.	2015-05-28
Device structure, layout and fabrication method for uniaxially strained transistors Grant 8,933,515 - Bedell , et al. January 13, 2	2015-01-13
Method Of Making A Semiconductor Device Including An All Around Gate App 20140357036 - Loubet; Nicolas ; et al.	2014-12-04
Electrostatic Discharge Resistant Diodes App 20140167203 - Bu; Huiming ; et al.	2014-06-19
Electrostatic Discharge Resistant Diodes App 20140167202 - Bu; Huiming ; et al.	2014-06-19
FinFET structure having fully silicided fin Grant 8,753,964 - Bryant , et al. June 17, 2	2014-06-17
SOI FinFET with recessed merged fins and liner for enhanced stress coupling Grant 8,723,262 - Basker , et al. May 13, 2	2014-05-13
Nanopillar decoupling capacitor Grant 8,680,651 - Chakravarti , et al. March 25, 2	2014-03-25
Field Effect Transistor Devices With Recessed Gates App 20140061792 - Bu; Huiming ; et al.	2014-03-06
finFET with merged fins and vertical silicide Grant 8,637,931 - Basker , et al. January 28, 2	2014-01-28
Preventing Fully Silicided Formation In High-k Metal Gate Processing App 20130330899 - Bu; Huiming ; et al.	2013-12-12
Preventing Fully Silicided Formation In High-k Metal Gate Processing App 20130328135 - Bu; Huiming ; et al.	2013-12-12
Cut-very-last Dual-epi Flow App 20130319613 - Basker; Veeraraghavan S. ; et al.	2013-12-05
Source-drain extension formation in replacement metal gate transistor device Grant 8,592,264 - Ando , et al. November 26, 2	2013-11-26
Cut-very-last dual-EPI flow Grant 8,592,290 - Basker , et al. November 26, 2	2013-11-26
High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof Grant 8,575,709 - Bu , et al. November 5, 2	2013-11-05
Cut-very-last dual-epi flow Grant 8,569,152 - Basker , et al. October 29, 2	2013-10-29
High-K metal gate CMOS Grant 8,507,992 - Mo , et al. August 13, 2	2013-08-13
Method And Structure For Inline Electrical Fin Critical Dimension Measurement App 20130173214 - Yamashita; Tenko ; et al.	2013-07-04
Source-drain Extension Formation In Replacement Metal Gate Transistor Device App 20130161763 - Ando; Takashi ; et al.	2013-06-27
Source-drain Extension Formation In Replacement Metal Gate Transistor Device App 20130161745 - Ando; Takashi ; et al.	2013-06-27
Method For Fabricating Finfet With Merged Fins And Vertical Silicide App 20130164890 - BASKER; Veeraraghavan S. ; et al.	2013-06-27
Finfet With Merged Fins And Vertical Silicide App 20130161744 - BASKER; Veeraraghavan S. ; et al.	2013-06-27
Soi Finfet With Recessed Merged Fins And Liner For Enhanced Stress Coupling App 20130154005 - Basker; Veeraraghavan S. ; et al.	2013-06-20
Method for fabricating finFET with merged fins and vertical silicide Grant 8,455,313 - Basker , et al. June 4, 2	2013-06-04
SOI FinFET with recessed merged Fins and liner for enhanced stress coupling Grant 8,445,334 - Basker , et al. May 21, 2	2013-05-21
Nanopillar E-fuse structure and process Grant 8,441,039 - Chakravarti , et al. May 14, 2	2013-05-14
Nanopillar E-Fuse Structure and Process App 20130048988 - Chakravarti; Satya N. ; et al.	2013-02-28
Nanopillar E-fuse structure and process Grant 8,344,428 - Chakravarti , et al. January 1, 2	2013-01-01
High-k dielectric gate structures resistant to oxide growth at the dielectric/silicon substrate interface and methods of manufacture thereof Grant 8,318,565 - Bu , et al. November 27, 2	2012-11-27
High-k Dielectric Gate Structures Resistant To Oxide Growth At The Dielectric/silicon Substrate Interface And Methods Of Manufacture Thereof App 20120286374 - Bu; Huiming ; et al.	2012-11-15
Device Structure, Layout And Fabrication Method For Uniaxially Strained Transistors App 20120261762 - BEDELL; STEPHEN W. ; et al.	2012-10-18
Device structure, layout and fabrication method for uniaxially strained transistors Grant 8,288,218 - Bedell , et al. October 16, 2	2012-10-16
Nanopillar Decoupling Capacitor App 20120256294 - Chakravarti; Satya N. ; et al.	2012-10-11
Nanopillar decoupling capacitor Grant 8,258,037 - Chakravarti , et al. September 4, 2	2012-09-04
FinFET STRUCTURE HAVING FULLY SILICIDED FIN App 20120193712 - Bryant; Andres ; et al.	2012-08-02
Inducing Stress In Fin-fet Device App 20120070947 - Basker; Veeraraghavan S. ; et al.	2012-03-22
Integration of passive device structures with metal gate layers Grant 8,097,520 - Bu , et al. January 17, 2	2012-01-17
CMOS transistors with differential oxygen content high-K dielectrics Grant 8,035,173 - Bu , et al. October 11, 2	2011-10-11
High-k Dielectric Gate Structures Resistant To Oxide Growth At The Dielectric/silicon Substrate Interface And Methods Of Manufacture Thereof App 20110221012 - Bu; Huiming ; et al.	2011-09-15
Device Structure, Layout And Fabrication Method For Uniaxially Strained Transistors App 20110175164 - Bedell; Stephen W. ; et al.	2011-07-21
High-k Metal Gate Cmos App 20110156158 - Mo; Renee T. ; et al.	2011-06-30
Nanopillar E-Fuse Structure and Process App 20110127637 - Chakravarti; Satya N. ; et al.	2011-06-02
High-K metal gate CMOS Grant 7,943,460 - Mo , et al. May 17, 2	2011-05-17
Nanopillar Decoupling Capacitor App 20110049673 - Chakravarti; Satya N. ; et al.	2011-03-03
Integration Of Passive Device Structures With Metal Gate Layers App 20110042786 - Bu; Huiming ; et al.	2011-02-24
Direct contact between high-.kappa./metal gate and wiring process flow Grant 7,863,123 - Bu , et al. January 4, 2	2011-01-04
High-K Metal Gate CMOS App 20100264495 - Mo; Renee T. ; et al.	2010-10-21
Method And Structure For Threshold Voltage Control And Drive Current Improvement For High-k Metal Gate Transistors App 20100244206 - Bu; Huiming ; et al.	2010-09-30
Direct Contact Between High-k/metal Gate And Wiring Process Flow App 20100181630 - Bu; Huiming ; et al.	2010-07-22
Cmos Transistors With Differential Oxygen Content High-k Dielectrics App 20100148273 - Bu; Huiming ; et al.	2010-06-17
CMOS transistors with differential oxygen content high-k dielectrics Grant 7,696,036 - Bu , et al. April 13, 2	2010-04-13
Gate Stack Structure With Oxygen Gettering Layer App 20090152651 - Bu; Huiming ; et al.	2009-06-18
Maskless Stress Memorization Technique For Cmos Devices App 20090142891 - Kim; Young-Hee ; et al.	2009-06-04
Cmos Transistors With Differential Oxygen Content High-k Dielectrics App 20080308872 - Bu; Huiming ; et al.	2008-12-18