U.S. patent number D766,850 [Application Number D/502,191] was granted by the patent office on 2016-09-20 for wafer holder for manufacturing semiconductor.
This patent grant is currently assigned to TOKYO ELECTRON LIMITED. The grantee listed for this patent is TOKYO ELECTRON LIMITED. Invention is credited to Masayuki Harashima, Hirokatsu Kobayashi, Wataru Machiyama, Eisuke Morisaki, Yukio Sano.
United States Patent |
D766,850 |
Morisaki , et al. |
September 20, 2016 |
Wafer holder for manufacturing semiconductor
Claims
CLAIM The ornamental design for a wafer holder for manufacturing
semiconductor, as shown and described.
Inventors: |
Morisaki; Eisuke (Nirasaki,
JP), Machiyama; Wataru (Nirasaki, JP),
Kobayashi; Hirokatsu (Nirasaki, JP), Harashima;
Masayuki (Nirasaki, JP), Sano; Yukio (Nirasaki,
JP) |
Applicant: |
Name |
City |
State |
Country |
Type |
TOKYO ELECTRON LIMITED |
Minato-ku, Tokyo |
N/A |
JP |
|
|
Assignee: |
TOKYO ELECTRON LIMITED
(Minato-ku, Tokyo, JP)
|
Appl.
No.: |
D/502,191 |
Filed: |
September 12, 2014 |
Foreign Application Priority Data
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|
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Mar 28, 2014 [JP] |
|
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D2014-006724 |
Mar 28, 2014 [JP] |
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D2014-006725 |
Mar 28, 2014 [JP] |
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D2014-006726 |
Mar 28, 2014 [JP] |
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D2014-006727 |
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Current U.S.
Class: |
D13/182 |
Current International
Class: |
1303 |
Field of
Search: |
;D13/182
;118/715,500,728,729 ;211/41.18 ;432/253,258
;156/345.51,345.52,345.53,345.55 ;414/217,220.01,935-941 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Jay; Jeremy
Description
FIG. 1 is a front view of a wafer holder for manufacturing
semiconductor showing our new design;
FIG. 2 is a rear view thereof;
FIG. 3 is a top plan view thereof;
FIG. 4 is a bottom plan view thereof;
FIG. 5 is a right side view thereof;
FIG. 6 is a left side view thereof;
FIG. 7 is a front perspective view thereof;
FIG. 8 is an enlarged cross sectional view taken along line 8-8 in
FIG. 1;
FIG. 9 is an enlarged portion view taken along line 9-9 in FIG. 1;
and,
FIG. 10 is another front perspective view of FIG. 1 shown in a used
condition with wafers shown in broken lines.
The features shown in dotted lines depict environmental subject
matter only and form no part of the claimed design.
* * * * *