U.S. patent application number 10/375333 was filed with the patent office on 2003-08-28 for electrically conductive filled through holes.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to Appelt, Bernd K., Gelorme, Jeffrey D., Kang, Sung Kwon, Markovich, Voya R., Papathomas, Kostas, Purushothaman, Sampath.
Application Number | 20030162047 10/375333 |
Document ID | / |
Family ID | 23355004 |
Filed Date | 2003-08-28 |
United States Patent
Application |
20030162047 |
Kind Code |
A1 |
Appelt, Bernd K. ; et
al. |
August 28, 2003 |
Electrically conductive filled through holes
Abstract
The present invention provides a unique conductive composition
for filling vias or through holes to make reliable vertical or
Z-connects. The through holes may be plated or unplated prior to
filling. A description for making high density electronic packaging
using this feature is also disclosed.
Inventors: |
Appelt, Bernd K.; (Endicott,
NY) ; Gelorme, Jeffrey D.; (Plainville, CT) ;
Kang, Sung Kwon; (Chappaqua, NY) ; Markovich, Voya
R.; (Endwell, NY) ; Papathomas, Kostas;
(Endicott, NY) ; Purushothaman, Sampath; (Yorktown
Heights, NY) |
Correspondence
Address: |
IBM Corporation
IP Law N50/040-4
1701 North Street
Endicott
NY
13760
US
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
23355004 |
Appl. No.: |
10/375333 |
Filed: |
February 27, 2003 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10375333 |
Feb 27, 2003 |
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09345428 |
Jul 1, 1999 |
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6555762 |
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Current U.S.
Class: |
428/570 ;
257/E23.067; 257/E23.072; 428/403; 428/404; 428/407 |
Current CPC
Class: |
H01B 1/22 20130101; H01L
2924/0002 20130101; Y10T 428/12181 20150115; H01L 23/49866
20130101; H01L 2924/0002 20130101; Y10T 428/2998 20150115; H01L
23/49827 20130101; H01L 2924/00 20130101; H01B 1/02 20130101; Y10T
428/2993 20150115; Y10T 428/2991 20150115; H05K 1/095 20130101;
H05K 3/4069 20130101 |
Class at
Publication: |
428/570 ;
428/403; 428/404; 428/407 |
International
Class: |
B32B 001/00 |
Claims
We claim:
1. A core-shell particle comprising: a) a core having a
predetermined melting point or decomposition point; and b) a shell
having a predetermined fusing temperature less than said melting
point or decomposition point of said core, so that when said
core-shell particle is heated above said fusing temperature, a
non-porous solid is formed.
2. The core-shell particle recited in claim 1 wherein said particle
is less than 20 microns in diameter and said shell is between about
0.2 and about 1 micron thick.
3. The core-shell particle recited in claim 1 wherein said core
comprises a first metal and said shell comprises a second
metal.
4. The core-shell particle recited in claim 3 wherein said first
metal comprises copper and said second metal is selected from the
group consisting of tin, indium, bismuth and antimony and alloys
thereof.
5. The core-shell particle recited in claim 1 wherein said core
comprises an organic composition.
6. The core-shell particle recited in claim 5 wherein said organic
composition is selected from the group consisting of polyester and
polystyrene.
7. The core-shell particle recited in claim 5 wherein the shell
comprises two metal layers with the first metal selected from the
group consisting of copper, nickel, palladium, platinum, silver and
alloys thereof and the second metal selected from the group
consisting of indium, tin, bismuth, antimony and alloys
thereof.
8. The core-shell particle recited in claim 1 wherein said core
comprises silica.
9. The core-shell particle recited in claim 8 wherein said silica
comprises a solid particle.
10. The core-shell particle recited in claimi 8 wherein said silica
comprises a hollow particle.
11. A mixture of a polymeric material and said core-shell particle
defined in claim 1 wherein said polymeric material is a
thermosetting or thermoplastic substance having a predetermined
curing temperature above said fusing temperature.
12. A three phase composite conductive article comprising: a) a
first phase comprising a metal having a first, three dimensional
lattice network defining a solid volume; b) a second phase
comprising particles embedded in and affixed to said first phase;
and c) a third phase comprising a polymeric material having a
second, three dimensional lattice network, said second, three
dimensional network interwoven within said first, three dimensional
network and substantially filling said solid volume; wherein the
quantity of said second phase is sufficient to render said article
conductive.
13. The conductive article recited in claim 12 wherein said second
phase comprises a second metal, having a higher melting point than
that of said first metal.
14. The conductive article recited in claim 12 wherein said second
phase comprises an organic composition, having a higher melting
point than that of said metal.
15. A process of heating a mixture to form an electrically
conductive, non-porous solid, comprising: a) providing a core-shell
particle comprising a core comprising a first metal having a
predetermined melting point, and a shell surrounding said core
comprising a second metal having a predetermined fusing
temperature, said melting point being greater than said fusing
temperature; b) providing a polymeric thermosetting or
thermoplastic substance having a predetermined curing temperature;
c) mixing said core-shell particle with said polymeric substance to
create a substantially homogeneous mixture; and d) heating said
mixture to a temperature above said curing and said fusing
temperatures to generate an electrically conductive, non-porous
solid.
16. A process of heating a mixture to form an electrically
conductive, non-porous solid, comprising: a) providing a core-shell
particle comprising an organic core having a predetermined melting
or decomposition point, and a metallic shell having a predetermined
fusing temperature, said melting or decomposition point being
greater than said fusing temperature; b) providing a polymeric
thermosetting or thermoplastic substance having a predetermined
curing temperature; c) mixing said core-shell particle with said
polymeric substance to create a substantially homogeneous mixture;
and d) heating said mixture above said curing and said fusing
temperatures to generate an electrically conductive, non-porous
solid.
17. A microelectronic package comprising: a) a dielectric substrate
having upper and lower lateral faces and at least one via being
defined by a wall; b) electronic circuitry and features affixed to
at least one of said lateral surfaces; and c) a composition
comprising an interpenetrating network substantially filling said
via, said network comprising a first matrix of cured thermosetting
or thermoplastic material and a second matrix comprising an
electrically conductive composition electrically connecting said
via to said electronic circuitry.
18. The microelectronic package recited in claim 17 wherein said
conductive composition comprises discrete metallic particles
proximate each other, said particles being embedded in a layer of a
metal.
19. The microelectronic package recited in claim 17 wherein said
conductive composition comprises discrete organic particles
proximate each other, said particles being embedded in a layer of a
metal.
20. The microelectronic package recited in claim 17 wherein said
second matrix is formed upon heating a core-shell particle above
the fusing point thereof.
21. The microelectronic package as recited in claim 17 further
comprising a conductive layer disposed between said
interpenetrating network composition and said wall.
22. A process of manufacturing a microelectronic package
intermediary structure comprising the steps of: a) providing a
dielectric substrate having an upper and lower lateral surface; b)
forming at least one via within said dielectric substrate
connecting said upper surface to said lower surface; c) filling
said via with a substantially uniform mixture of thermosetting or
thermoplastic material having a predetermined curing temperature
and core-shell particles having fusible shells; and d) heating said
filled via and said dielectric substrate to a temperature above
said curing temperature in order to cure said material, to fuse
said core-shell particles, and to form an electrically conductive
via.
23. The process of manufacturing a microelectronic package
intermediary structure as recited in claim 22 further comprising
the step of: e) after forming said via, step (b), flash plating or
electroless plating a conductive layer to said upper and lower
lateral surfaces and a via wall, forming a conductive layer having
a thickness of at least 0.5 mil.
24. The process of manufacturing a microelectronic package
intermediary structure as recited in claim 22 further comprising
the steps of: e) applying conductive layers to at least one of said
lateral surfaces; and f) circuitizing said conductive layer,
whereby said circuitry is in electrical contact with said
electrically conductive via.
25. The process of manufacturing a microelectronic package
intermediary structure as recited in claim 22 further comprising
the step of: e) after heating said via and said substrate step (d),
soldering an electrical component to a top surface of said filled
via without the use of a pad.
Description
FIELD OF THE INVENTION:
[0001] The present invention relates to printed circuit board and
card manufacture and, more particularly, to a unique conductive
composition for filling vias or through holes to make reliable
vertical or Z-connects.
BACKGROUND OF THE INVENTION
[0002] With the continued trend toward reduced size of electronic
components and the resulting high density requirements for
electronic packaging, there has been an increased demand to design
a process that will efficiently generate high quality, high density
electronic packaging such as printed wiring board structures.
[0003] In the past decade the density per unit area of electronic
devices, such as very large scale integrated circuits (VLSIs), has
greatly increased. By some estimates this increase in density has
been on the order of 10,000 times what it was in the earliest days
of the technology. The space or area available outside of a VLSI in
which to make the large number of necessary connections to and from
it and to provide the necessary circuitry is becoming almost
vanishingly small, measured by previous standards. Contrary to the
density increase of VLSIs, the density of the passive circuits on
printed wiring boards has increased (i.e., the parts have decreased
in size) by only a relatively small factor: less than about 4 to 1.
This presents the difficult problem of providing circuitry on the
printed wiring board to the VLSIs which is small enough to fit the
spaces available, while being sufficiently reliable and
manufacturable to be economically useful.
[0004] Perhaps one of the most significant limitations for creating
high density fine line circuitry on printed wiring boards is the
generally known problem of anisotropic etching. It is known that
etching metals, especially copper metal, is not an anisotropic
process. That is, vertical etching is not feasible without some
amount of unwanted horizontal etching. This creates a situation in
which the features and circuitry so formed can be severely
undercut, leading to different types of failures and reject
material. The problem is exacerbated by having thick metal layers
and thick photoresist layers. However, this is precisely the
situation that occurs when plated through holes are part of
-conventional manufacturing process.
[0005] It is also well known that due to the nature of the plating
process, the metal plating within a through hole or via is thinner
than the plating on the external surfaces of the dielectric
substrate; yet a minimum thickness in the through hole is required
in order to provide an adequate and reliable electrical connection
between circuitry on opposing surfaces or at various vertical
levels within the printed wiring board structure. Therefore, the
general practice is to plate excess material on the lateral faces
in order to ensure sufficient plating of the through holes. The
excessive thickness of the lateral surface plating causes greater
amounts of undercutting during the later circuitization/etching
process. To compensate for this effect, the circuitry lines are
designed wider and farther apart than otherwise would be required
or desired. In an attempt to resolve this problem, thinning down
the lateral surface by uniform etching prior to circuitization has
been attempted. If chemically performed, this process can also
undesirably etch within the plated through hole. Mechanical etching
of the lateral surface plating is possible, but requires an
unacceptably long period of time.
[0006] Another difficulty in obtaining sufficient plating thickness
within the through hole, as compared to plating the lateral
surfaces, is the significant increase in expense associated with
plating high aspect vias.
[0007] A land or pad around the through hole is required to provide
a reliable electrical connection in the eventuality that there is a
break in the plating on the rim of the through hole. The trade-off
for applying a reliable land or pad is a thicker than necessary
metallized region. Consequently, a thicker than usual photoresist
layer must be applied to obtain a level surface for placement of
the mask and to ensure the photoresist spanning over the hole
(tenting) does not rupture and result in etchant entering the
plated through hole. Thus, through holes cause an undesirable
increase in thickness both of the surface plating and of the
photoresist layer.
[0008] In addition to the problem of layer thickness discussed
supra, the prior art process of plating through holes requires the
land or pad on the lateral surface of the commoning layer to
connect in a dog-bone configuration to the plated through holes.
The land utilizes valuable space on the lateral surface that could
otherwise be used for circuitry. Consequently, there has been a
long standing desire to eliminate the need for such lands or
pads.
[0009] The plated through hole itself also consumes valuable space
for several reasons. Firstly, the diameter of the hole is typically
dictated by the cost of plating high aspect vias and the cost of
small diameter drilling bits. To avoid the expense of high aspect
plated through holes, larger plated through holes are typically
utilized, but they must be placed at a distance from the areas
containing fine line circuitry. This design, known as "fan-out",
however, contributes to loss of circuitry space due to the need for
greater routing space.
[0010] Another known problem associated with conventional plated
through holes is the different expansion rate between copper
plating and the dielectric or pre-preg layer. When subjected to
heating and cooling cycles, the plating on the through hole is
susceptible to cracking.
PRIOR ART REFERENCES
[0011] Prior art literature addresses the problems associated with
plated through holes and describes processes and materials of
making alternative designs. Relevant prior art patents are
summarized hereinbelow.
[0012] Hayakawa et al. in U.S. Pat. No. 4,383,363, teach the
benefit of using conductive materials for filling through holes.
The patent is directed toward the process of filling through holes
and describes only a limited selection of conductive fillers.
[0013] Lambert et al. in U.S. Pat. No. 4,820,340, disclose a method
of fabricating a conductive polymer interconnect (CPI) which
employs chains of electrically conductive particles within an
elastomeric matrix. The process requires removing a thin layer of
elastomeric material from the outer surfaces by use of plasma
etching in order to provide a conductive surface. Gold- or
silver-plated nickel particles are used, but no mention is made of
using copper as the conductive material. Particles are
approximately 100 micron and are imbedded in an elastomer of
polysiloxane room temperature vulcanizing (RTV) rubber. Magnetic
fields are used to align the particles and then a heat cure step is
performed. Subsequently, the surface layer of the cured rubber is
removed by plasma etching. As reported in Lambert, et al., U.S.
Pat. No. 4,820,376, plasma etching removes the gold shell leaving
the nickel core exposed to air. To prevent aerial oxidation of the
nickel, the material is plated with electroless gold.
[0014] Kawakami et al. disclose, in U.S. Pat. No. 5,220,135, a
conductive filling within the through hole of an insulative
substrate. Conductive resins are described which include silver,
copper, and carbon conductive materials. No mention is made of a
core-shell particle having a fusible shell.
[0015] Higgins, III et al. in U.S. Pat. Nos. 4,967,314 and
5,117,069, describe a method and material for eliminating plating
in through holes by filling the through holes with a silver epoxy
conductive paste. Higgins, III et al. employ a process wherein the
vias are slightly overfilled with the conductive epoxy in order to
create bumps at each end of the via. Then several printed wiring
boards and prepreg layers are stacked up and subsequently
laminated. During the lamination process, the excess epoxy is
squeezed from the ends and spreads out over the printed wiring
board layer to create intimate contact between the circuitry and
the conductive polymer within the through hole. Higgins, III et al.
teach away from the use of a copper epoxy by indicating that the
copper epoxy would have a higher resistance than the silver epoxy.
Furthermore, Higgins, III et al. prefer the use of thermoplastic
paste compositions. Lastly, the epoxy composition is limited to
high viscosity materials of approximately 100 centipoise in order
to provide adequate adhesion of the epoxy within the via.
[0016] Bhatt et al. in U.S. Pat. Nos. 5,557,844 and 5,487,218,
disclose a process and a material for forming filled through holes
and blind holes. The filler material is an organic polymeric
material, optionally with a particulate filler. The filler
composition is compounded to have a coefficient of thermal
expansion matching the coefficient of thermal expansion of the
dielectric substrate. The fill material may be either conductive or
non-conductive. These patents teach laminating a copper foil to a
dielectric substrate, followed by thinning the foil to an
acceptable thickness, then drilling through holes and subsequently
electrolessly plating into the through holes to create a conductive
layer therein. The filling in the '844 patent occurs after the
etching process of the lateral metallized layers. Conductive
filling compositions include resins made from epoxy- or cyanate-
containing materials and have conductive material derived from
carbon, copper, silver, nickel, molybdenum, gold, platinum, and
aluminum. Particle size for the conductive materials ranges from
0.1 to 75 micron, the most preferred size being between 0.5 and 10
micron.
[0017] Chong et al., in U.S. Pat. Nos. 5,699,613 and 5,758,413,
describe a method of manufacturing a multiple layer circuit board
with stacked vias. These patents disclose a filled through hole
having a conductive plug comprising a 70-80% copper fill.
[0018] Boyko et al., in U.S. Pat. No. 5,450,290, describe an
integrated chip carrier and a technique for manufacturing same. The
through hole is formed after copper sheets have been applied to the
dielectric substrate and are initially plated by conventional
electroless or electroplating techniques. Then a conductive paste
is applied to the through holes. The paste is a epoxy novalak
containing copper powder.
[0019] Gaynes et al., in U.S. Pat. No. 5,542,602, describe a
conductive adhesive comprising a core-shell material having an
inner core of copper, silver or gold and an outer shell of indium,
tin or lead. Particles are approximately 10-15 micron in size and
have a shell thickness of 1.0-1.5 micron. The patent is directed
toward a solder replacement that can be used to affix two layers at
temperatures below 220.degree. C. and exploits a transient liquid
phase (TLP) reaction for alloying on metals. A second application
of the '602 patent replaces conventional conductive adhesives which
require high concentrations of conductive particles in intimate
contact to achieve a connector structure that is itself conductive.
A polymeric material is used as a matrix or binder for the
conductive particles. Upon curing, the binder creates compressive
forces that ensure intimate contact of the conductive particles.
The underlying concept of both applications in the '602 patent is
that the shell metal, having a lower melting point than the core,
will melt and alloy with the core upon reaching a critical
temperature, creating a second phase that is between, but still
electrically connected to, the core particles. In this manner, a
low melting eutectic is formed which will create an isotropic
stable conductive connection that can survive repeated thermal
cycles. The patent is directed toward forming a metallurgical bond
between two metal surfaces. No mention is made of using this
material or similar materials as a filler within a through hole,
nor is any mention made of the benefit that would be derived from
such a process (i.e., the elimination of various processing steps
such as electroless copper plating). Further, for the process to
perform optimally, the curing temperature must be below the TLP
temperature.
[0020] Other references to transient liquid phase bonding include:
Wilcox et al., in U.S. Pat. No. 5,038,996; Davis et al., in U.S.
Pat. No. 5,280,414; Galasco et al., in U.S. Pat. No. 5,432,998;
Davis et al., in U.S. Pat. No. 5,620,782; and Gaynes et al., in
U.S. Pat. No. 5,713,508.
[0021] Having discussed the general problem associated with the
current practice of plating through holes to create Z-connects and
the current attempts at solving the problem, it is understood that
additional improvements would still be beneficial.
[0022] In summary, having the flexibility to eliminate or replace
the thick lands surrounding the plated vias and to eliminate the
plating of the vias would constitute a significant advancement in
electronic package manufacturing and would alleviate the
constraints imposed by the through hole plating process.
[0023] Therefore it is an object of the current invention to
provide a high density (low pitch) fine line circuitry printed
wiring board structure without the need for plating through
holes.
[0024] It is another object of the invention to provide a high
density (low pitch) fine line circuitry printed wiring board having
multiple layers of circuitry interconnected with filled conductive
through holes or blind holes.
[0025] It is another object of the invention to provide filled
through holes to eliminate or reduce the need for thick lands,
thereby providing higher density circuitry.
[0026] It is another object of the invention to utilize a thin,
non-tenting resist in order to obtain high density circuitry.
[0027] It is yet another object of the invention to provide a
process of filling the vias by vacuum fixturing without the need to
plug via holes separately.
[0028] It is still another object of the invention to design a
conductive fill material that can wet copper as well as dielectric
material and also that can be directly solderable.
[0029] It is yet another object of the invention to reduce the
registration budget by providing landless vias, having eliminated
the concern for hole breakout.
[0030] Yet another object of this invention is to provide a method
of making a circuitized substrate capable of being used as a chip
carrier assembly, the method being performed in a facile and
relatively inexpensive manner in comparison to existing carrier
manufacturing processes.
[0031] It is a more particular object of the invention to provide
such a process which is readily adaptable to existing manufacturing
equipment without extensive modification thereof.
SUMMARY OF THE INVENTION
[0032] The present invention is designed to address the
deficiencies in the art as well as the specific objects disclosed
hereinabove.
[0033] In order to meet the objectives listed supra, a process has
been designed to provide vias filled with a unique and novel
conductive material.
[0034] The primary feature of the invention is to provide a
conductive material that can be used to fill through holes or vias
to Z-connect two or more layers of circuitry or conductor runs. The
vias may optionally be plated with a conductive material; however,
in one preferred aspect of the invention this is not required.
[0035] In accordance with another aspect of this invention, there
is defined a method of making a circuitized substrate, the method
comprising the steps of providing an electrically insulative base
member having first and second surfaces, formation of at least one
via hole, filling said via with a conductive material, optional
planarization of the filled via on at least one of the first and
second surfaces, and applying a first electrically conductive layer
onto the first and second surfaces of the base member. The method
still further includes applying a photoimaging material onto the
thinned first conductive layer, then exposing and developing
selected portions of the photoimaging material to define a pattern
within the photoimaging material on the thinned first conductive
layer. The method even further includes circuitizing the first
conductive layer and then removing the photoimaging material from
the first conductive layer. The fill material contained in the
plated vias is not removed and can optionally be used to act as a
solder point for surface mounting various components.
[0036] If multilayer structures are desired, the material described
supra can be laminated to dielectric substrates containing a
pre-preg and/or copper foil surfaces. In this manner, electrically
conductive filled vias can connect external circuitry to internal
circuitry or conductor runs.
[0037] The inventive fill material comprises a core-shell particle
in a polymeric media that, under a defined pressure and temperature
regime, cures to generate a solid plug having minimal shrinkage,
thereby essentially filling the via volume. For purposes of
definition, the curing temperature is considered the temperature at
which a glass, viscous liquid, or rubber state resinous composition
is converted into a solid three dimensional structure. The
temperature at which this occurs is not necessarily a precise point
and is affected by such factors as catalyst amount, pressure, and
radiation. Therefore, the curing process occurs over a range of
temperatures, but is easily observable as a physical change in
state. The shells of the core-shell particles are designed to fuse
with each other to generate an electrically connected network
within the cured medium. The fusing temperature is defined as the
melting temperature of the pure metal in the shell or the eutectic
melting point of an alloy with core metal, should that occur.
Therefore, in a single process, the invention provides a means for
generating a solid conductive plug which can be electrically
connected to later formed circuitry on the surfaces of the base
member and to optional internal circuitry.
[0038] The benefit of the present invention is the ability to
produce higher density circuitry than is currently available from
existing designs. This invention can produce circuitry having a
cross-section width of 0.7-2.0 mil and spacing between the
circuitry of 1-2 mil. No other photolithographic processes are
known to the inventors that can generate these same dimensions.
[0039] Other benefits and further scope of applicability of the
present invention will become apparent from the detailed
description given hereinbelow. It should be understood, however,
that the detailed description and specific examples, while
indicating preferred embodiments of the invention, are given by way
of illustration only and are not to be construed as limitations of
the current invention, since various changes and modifications
within the scope and spirit of the invention will become apparent
to those skilled in the art from this detailed description.
[0040] Furthermore, as is known in the art, changes in the amount
of most critical parameters affect the benefit of an invention by a
matter of degree and not normally with a precise point of success
or failure. This is especially true when multiple variables might
be involved. In this case, the situation is further complicated by
interactions between such variables. Therefore, where parameters
are given a value or range of values, it should be understood that
these well defined areas clearly are within the scope of the
invention. Yet other values might still be within the scope of the
invention if the desired beneficial effects of the invention are
demonstrated. For this reason, words such as "approximately" or
"about" are used to indicate that the values presented are not
necessarily true limits to the invention. The true inventive scope
can be readily determined by experimentation.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0041] The inventive core-shell material requires that the outer
shell be composed of material that has a fusing temperature below
the melting point of the internal core material. Several
embodiments of this concept are contemplated within this invention.
In one embodiment, the core comprises copper and the shell
comprises tin (Sn), indium (In), bismuth (Bi), or antimony (Sb) and
their alloys. In another embodiment, the core is an organic
material and the shell is a metal, such as copper, tin or
combinations thereof. In still another embodiment, the core is an
inorganic material such as silica spheres, solid or hollow in
nature and the shell is a metal such as tin or bismuth. When the
core is composed of an organic material it might have a true
melting point defined by a specific temperature at which the solid
phase of the material is converted into a liquid phase. The melting
process is a reversible process wherein the liquid phase can be
converted into the solid phase by cooling. However, certain organic
materials do not possess a melting point. Rather, they have a point
at which the material irreversibly decomposes. Because this is not
a reversible physical process, but rather a chemical reaction, the
decomposition point is dependent on many factors, including rate of
heating and presence of air.
[0042] Preferred organic materials used as a core particle in this
invention include polyester and polystyrene.
[0043] The core-shell particles can be any shape, but typically
they are essentially spherical. The particle size of the core
material is 5-20 micron and the shell size is 0.2-1.0 micron.
Therefore, the core-shell particle is preferably between about 5.4
and 22 micron. The core can be either solid or hollow depending on
process of manufacture.
[0044] Preferred manufacturing processes for core-shell particles
as found in the current invention include electroless coating,
electrodeposition, physical or chemical vapor deposition,
sputtering or the like.
[0045] The core-shell particle is then dispersed by mixing into a
liquid media. The liquid media may be an organic resin which, upon
heating, cures into a solid conductive article. Typically, an
organic substance is used that is either thermosetting or
thermoplastic. Examples of such a resin are epoxy, phenoxy,
silicones, polyimides, polyimidesiloxane, siloxane, styrene allyl
alcohol, polyester, and polystyrene.
[0046] The quantity of core-shell particle within the mixture is
determined by the onset of electric conductivity within the cured
article. The minimum electrical conductivity of the cured article
in the present invention is (0.01+0.1).times.10.sup.6
ohm.sup.-1cm.sup.-1. This corresponds to a minimum concentration of
0.3 to 0.9 gm particles/gm mixture, which agrees with percolation
theory models that have been generated to predict the concentration
necessary to form a continuous, three dimensional network of
conductive particles within a second matrix of non-conductive
material. This model is used when interpenetrating networks (IPN)
of the type described herein are formed. In addition to the
conductive core-shell particle and the organic resin, other
components are particularly useful within the current design as
curing agents, such as anionic initiators, cationic initiators,
carboxy functionalized initiators, polyamides, amido amines,
polyamines, melamine-formaldehydes, phenol-formaldehydes,
urea-formaldehydes, dicyandiamide, polyphenols, polysulfides,
ketimines, novolacs, anhydrides, blocked isocyanates, imidazoles
and carboxylic acids; and as catalysts or accelerators such as
amines, phosphines, hydroxyl-containing compounds, imidazoles,
organometallic compounds, Lewis acid compounds and sulfonium salts.
The mixture of conductive particles, organic resin, curing agent
and catalyst into a resinous composition creates a conductive paste
or adhesive which, under the proper conditions, hardens to a solid
plug.
[0047] The particles described hereinabove can be used to
manufacture high density microelectronic packaging. For this
application, the inventive process begins with an organic
dielectric or insulative substrate in the form of a film in order
to, provide a rigid or flexible printed wiring board structure. The
thickness of the film can range from 0.5 mils to 8 mils, the
preferred thickness range being between 1 mil and 3 mils. The
substrate must contain at least one through hole or blind hole and
may additionally be multilayered, having embedded circuitry or
conductor runs. The chemical composition of the dielectric
substrate can be of various types including epoxies, polyimides,
bismaleimides, cyanate esters, and combinations thereof, Teflon
based dielectrics, aramid based dielectrics, woven or non-woven
dielectric substrates, and particulate or nonparticulate filled
dielectrics. Preferred compositions include epoxies, polyimides,
cyanate esters, and mixtures thereof, and Teflon based dielectrics.
Such compositions are commercially available and are known in the
art as organic circuit board laminates.
[0048] The through holes can be formed by anyone of known
penetrating techniques in the art, including drilling, punching,
etching, or laser vaporization. Size of the through hole is not
critical to the invention, but it is preferred that the holes be as
small as manufacturable by the various techniques. A typical
diameter range for the through hole utilized in the present
invention is about 0,5 to about 18 mil, preferred diameter size
being about 2 to about 12 mil.
[0049] After formation of the through holes, the inner surface
walls should optionally be cleaned to remove debris and condition
the surface for later coating applications. Although not required,
one embodiment of the invention allows for flash plating a layer of
less than 0.3 mil or electroless metal plating a layer of about 0.5
mil on the through hole wall and on major lateral surfaces of the
dielectric substrate.
[0050] Prior to applying the optional metallic plate, the
dielectric substrate may need to be pretreated to assure sufficient
adhesion to the metal plate composition. Known processes such as
conditioning with a cationic polymer and subsequent seeding with a
noble metal such as palladium can be employed. Other methods that
chemically or physically etch the dielectric substrate surface are
also useful in this invention.
[0051] The through holes are filled with the electrically
conductive composition, described in detail hereinabove, by known
processes in the art. Typically, due to the nature of the
conductive material, filling can readily be achieved by using a
mask and applying the filling material through the mask either
under pressure or by vacuum. It is important that the filling
process not entrap significant quantities of air, since after
curing, the air pockets may cause physical weakening of the plug.
To achieve a void-free plug, the conductive composition must be
designed with appropriate viscosity and surface tension.
[0052] The filled through hole and surrounding dielectric substrate
is then subjected to a predetermined temperature to cure the
polymeric binder within the conductive material. The heat treatment
also fuses the outer shell of the core-shell particles together in
order to create the continuous, three dimensional, electrically
conductive network within the cured polymeric binder. Operating
temperature for this process is typically in the range of
100.degree. C. to about 200.degree. C., a preferred temperature
range being typically about 130.degree. C. to about 180.degree.
C.
[0053] If performed in a single step (i.e., curing and fusing),
then the operating temperature must be above both the curing and
fusing temperature, but below the melt temperature of the core. In
one embodiment, the curing temperature is above the fusing
temperature. The curing and fusing temperatures are predetermined
to be of sufficiently low value so that a wide operating
temperature range exists without concern for thermal damage to
physical or electrical properties of the dielectric substrate,
circuitry or other components. Furthermore, the melting point of
the metal core of the core-shell particles is specifically
determined to be above the operating temperature range for this
invention.
[0054] The heating treatment is typically employed for about 15 to
about 60 minutes, preferably about 15 to about 30 minutes. Optimal
times depend on the operating temperature of the process.
[0055] The cured polymer binder and electrical conductive network
possess certain unique, beneficial properties. A particularly
beneficial property is for the material to be non-shrinking during
curing. This is extremely important in order to create a tight seal
between the cured polymeric binder structure (also known as a plug)
and the vertical wall of the dielectric substrate. Values of less
than 28 ppm/.degree. C. are considered useful for this formulation.
Adhesion of the uncured and cured resin to the wall is also a
critical feature.
[0056] Another useful property of the cured plug is that it is
non-porous. This property allows the later use of a liquid
photoresist or flashing or etching solutions without the need to
protect the outer surface from liquid infiltration.
[0057] Another useful property of the cured plug is that it dry to
a tack-free surface.
[0058] Still another useful property is the low thermal expansion
of the cured material. The benefit of this feature is that no
cracking is observed when the finished microelectronic package
containing this cured plug is subjected to repeated heating and
cooling conditions.
[0059] It is also an important design feature of the invention to
use the outer surface of the conductive plug as a solder site for
various surface mount microelectronic components.
[0060] Although the filling operation is intended to provide a
sufficient volume of binder and core-shell particles in order to
just fill the through holes, commonly excess material is deposited
and the ends of the plug extend beyond the lateral surface of the
dielectric substrate. Depending on final packaging design, the
excessive outer end of the cured plug can be removed in an optional
planarizing step. Planarization typically is performed by
mechanical means well known in the art.
[0061] The dielectric substrate is then coated with a metal that
ultimately provides the circuitry and features of the manufactured
printing board. The coating of the dielectric substrate can be
accomplished by any of the known methods of plating, such as
sputtering, electroless plating or electrolytic plating. Plating
thickness can range from 5 microns to about 50 microns, the
preferred thickness being in the range of 8 microns to 25
microns.
[0062] The chemical composition of the plating material typically
is a conductive metal, examples including copper and its alloys,
aluminum and its alloys, and nickel and its alloys. The uniform
metallic plating thus applied is then converted into the necessary
features and fine line circuitry found on the finished printed
wiring board. Conversion, known in the industry as
"personalization", typically is performed by photolithographic
means that employ a series of steps including:
[0063] a) applying a photoresist to the metallic layer;
[0064] b) applying an opaque mask over the photoresist, the mask
having discrete openings in the form of an image that are
ultimately transferred to the metallic layer;
[0065] c) exposing the mask to electromagnetic radiation or an
electron beam so that such radiation impinges only on the
photoresist in areas of openings in the mask;
[0066] d) removing the mask;
[0067] e) applying a chemical etchant to the photoresist to create
a series of openings extending to the underlying metallic layer in
areas where the photoresist has high solubility;
[0068] f) chemically etching the areas of uncovered metal to
uncover dielectric substrate, forming electrically discrete
features and circuitry; and
[0069] g) stripping the remaining portion of the photoresist from
the upper surface of the latent features and circuitry.
[0070] The general description for this process is applicable to
either a negative or positive working photoresist system. In the
case of a negative working photoresist, the areas of photoresist
etched are those that are unexposed to light; while for positive
working photoresists, the areas exposed to light are more
susceptible to etching. In either case, the present invention can
generate the necessary features and fine line circuitry. Most
preferred is the use of negative working photoresists either in dry
film or liquid form. Examples of such materials include acrylate
based dry film resist such as: MI supplied by McDermid, 4830, 4820
or PM 115 supplied by DuPont; and liquid negative resists such as
polyisoprene or acrylate-based SM32 supplied by Shipley.
[0071] The thickness of the photoresist can be kept to a minimum,
since tenting can be avoided in the current invention. The benefit
of using such thin photoresist layer is the ability to achieve high
circuit densities. Typical photoresist thickness in this invention
is 0.2 mil to about 2.0 mil, a preferred thickness range being from
about 0.5 mil to about 1.0 mil.
[0072] Depending on the thickness of the initial metallic layer,
the discrete features and circuitry can be formed by any of the
known processes in the art including subtractive, additive or
semiadditive.
[0073] The next step in the process is to protect the fine line
circuitry from the later plating steps of the features. Protection
is achieved by employing a mask and photoresist of the types
previously described. In this case, the photoresist is etched in
areas where the features are to be plated and cover the fine line
circuitry. The features that are exposed are the intermediary
stages of the connection sites for external components (i.e., land
grid arrays).
[0074] Since other modifications and changes varied to fit
particular operating requirements and environments will be apparent
to those skilled in the art, the invention is not considered
limited to the example chosen for purposes of disclosure, and
covers all changes and modifications which do not constitute
departures from the true spirit and scope of this invention.
[0075] Having thus described the invention, what is desired to be
protected by Letters Patent is presented in the subsequently
appended claims.
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