Purushothaman; Sampath

Patent Applications and Registrations

Patent applications and USPTO patent grants for Purushothaman; Sampath.The latest application filed is for "enhanced adhesive materials and processes for 3d applications".

Company Profile

12.200.165

Purushothaman; Sampath - Yorktown Heights NY
Purushothaman; Sampath - Armonk NY
- Yorktown Heights NY US
Purushothaman; Sampath - Yorktown Height NY
Purushothaman, Sampath - Yorktown NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Enhanced adhesive materials and processes for 3D applications Grant 11,168,234 - Hedrick , et al. November 9, 2	2021-11-09
3D integration method using SOI substrates and structures produced thereby Grant 10,796,958 - Purushothaman , et al. October 6, 2	2020-10-06
3D integration method using SOI substrates and structures produced thereby Grant 10,777,454 - Purushothaman , et al. Sept	2020-09-15
Enhanced adhesive materials and processes for 3D applications Grant 10,767,084 - Hedrick , et al. Sep	2020-09-08
Enhanced Adhesive Materials And Processes For 3d Applications App 20200165494 - Hedrick; James L. ; et al.	2020-05-28
3D integration method using SOI substrates and structures produced thereby Grant 10,651,086 - Purushothaman , et al.	2020-05-12
Enhanced Adhesive Materials And Processes For 3d Applications App 20190378781 - Hedrick; James L. ; et al.	2019-12-12
Enhanced via fill material and processing for dual damscene integration Grant 10,340,182 - Doyle , et al.	2019-07-02
Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby App 20180374751 - Purushothaman; Sampath ; et al.	2018-12-27
Enhanced Adhesive Materials And Processes For 3d Applications App 20180340100 - Hedrick; James L. ; et al.	2018-11-29
Novel 3d Integration Method Using Soi Substrates And Structures Produced Thereby App 20180337091 - Purushothaman; Sampath ; et al.	2018-11-22
Novel 3d Integration Method Using Soi Substrates And Structures Produced Thereby App 20180315655 - Purushothaman; Sampath ; et al.	2018-11-01
Enhanced adhesive materials and processes for 3D applications Grant 9,994,741 - Hedrick , et al. June 12, 2	2018-06-12
Enhanced Via Fill Material And Processing For Dual Damascene Integration App 20180138084 - Doyle; James P. ; et al.	2018-05-17
Novel 3D Integration Method Using SOI Substrates And Structures Produced Thereby App 20170271207 - Purushothaman; Sampath ; et al.	2017-09-21
Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby App 20170229392 - PURUSHOTHAMAN; Sampath ; et al.	2017-08-10
Enhanced Adhesive Materials And Processes For 3d Applications App 20170166784 - Hedrick; James L. ; et al.	2017-06-15
Enhanced Via Fill Material And Processing For Dual Damscene Integration App 20170154812 - DOYLE; James P. ; et al.	2017-06-01
Three-dimensional integrated circuit device fabrication including wafer scale membrane Grant 9,412,620 - La Tulipe, Jr. , et al. August 9, 2	2016-08-09
Capping coating for 3D integration applications Grant 9,218,956 - Purushothaman , et al. December 22, 2	2015-12-22
Process for enhanced 3D integration and structures generated using the same Grant 9,111,925 - Colgan , et al. August 18, 2	2015-08-18
Corrugated interfaces for multilayered interconnects Grant 9,089,080 - Clevenger , et al. July 21, 2	2015-07-21
Lock and key through-via method for wafer level 3D integration and structures produced thereby Grant 9,064,717 - Purushothaman , et al. June 23, 2	2015-06-23
Three-dimensional Integrated Circuit Device Fabrication Including Wafer Scale Membrane App 20150147869 - LA TULIPE, JR.; Douglas C. ; et al.	2015-05-28
Novel 3D Integration Method Using SOI Substrates And Structures Produced Thereby App 20150054149 - Purushothaman; Sampath ; et al.	2015-02-26
Three-dimensional integrated circuit device using a wafer scale membrane Grant 8,963,278 - La Tulipe, Jr. , et al. February 24, 2	2015-02-24
Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrier Grant 8,962,448 - Farooq , et al. February 24, 2	2015-02-24
Computer Readable Medium Encoded With A Program For Fabricating 3d Integrated Circuit Device Using Interface Wafer As Permanent Carrier App 20150024548 - Farooq; Mukta G. ; et al.	2015-01-22
Capping Coating For 3d Integration Applications App 20150011072 - Purushothaman; Sampath ; et al.	2015-01-08
Bonding of substrates including metal-dielectric patterns with metal raised above dielectric and structures so formed Grant 8,927,087 - Chen , et al. January 6, 2	2015-01-06
Capping coating for 3D integration applications Grant 8,912,050 - Purushothaman , et al. December 16, 2	2014-12-16
Interconnect structures with engineered dielectrics with nanocolumnar porosity Grant 8,901,741 - Colburn , et al. December 2, 2	2014-12-02
Corrugated interfaces for multilayered interconnects Grant 8,828,521 - Clevenger , et al. September 9, 2	2014-09-09
Capping coating for 3D integration applications Grant 8,778,736 - Purushothaman , et al. July 15, 2	2014-07-15
3D integrated circuit device fabrication with precisely controllable substrate removal Grant 8,738,167 - Farooq , et al. May 27, 2	2014-05-27
Bonding Of Substrates Including Metal-dielectric Patterns With Metal Raised Above Dielectric And Structures So Formed App 20140097543 - Chen; Kuan-Neng ; et al.	2014-04-10
Three-dimensional Integrated Circuit Device Using A Wafer Scale Membrane App 20140077330 - LA TULIPE, JR.; Douglas C. ; et al.	2014-03-20
Method for fabricating 3D integrated circuit device using interface wafer as permanent carrier Grant 8,664,081 - Farooq , et al. March 4, 2	2014-03-04
Wafer scale membrane for three-dimensional integrated circuit device fabrication Grant 8,637,953 - La Tulipe, Jr. , et al. January 28, 2	2014-01-28
Semiconductor Structure App 20140021616 - Anzola; Diego ; et al.	2014-01-23
Semiconductor Structure App 20140024146 - Anzola; Diego ; et al.	2014-01-23
3D integrated circuit device fabrication with precisely controllable substrate removal Grant 8,629,553 - Farooq , et al. January 14, 2	2014-01-14
Homogeneous porous low dielectric constant materials Grant 8,623,741 - Purushothaman , et al. January 7, 2	2014-01-07
Bonding of substrates including metal-dielectric patterns with metal raised above dielectric and structures so formed Grant 8,617,689 - Chen , et al. December 31, 2	2013-12-31
Bonding of substrates including metal-dielectric patterns with metal raised above dielectric and structures so formed Grant 08617689 -	2013-12-31
Process For Enhanced 3D Integration and Structures Generated Using the Same App 20130341791 - Colgan; Evan George ; et al.	2013-12-26
Process for enhanced 3D integration and structures generated using the same Grant 8,600,202 - Colgan , et al. December 3, 2	2013-12-03
Bonding Of Substrates Including Metal-dielectric Patterns With Metal Raised Above Dielectric And Structures So Formed App 20130307139 - Chen; Kuan-Neng ; et al.	2013-11-21
High memory density, high input/output bandwidth logic-memory structure and architecture Grant 8,569,874 - Colgan , et al. October 29, 2	2013-10-29
3D integration method using SOI substrates and structures produced thereby Grant 8,563,396 - Purushothaman , et al. October 22, 2	2013-10-22
Corrugated Interfaces For Multilayered Interconnects App 20130273325 - Clevenger; Lawrence A. ; et al.	2013-10-17
Corrugated Interfaces For Multilayered Interconnects App 20130270224 - Clevenger; Lawrence A. ; et al.	2013-10-17
Programmable via devices Grant 8,525,144 - Chen , et al. September 3, 2	2013-09-03
Self-aligned dual damascene BEOL structures with patternable low- K material and methods of forming same Grant 8,519,540 - Chen , et al. August 27, 2	2013-08-27
Corrugated interfaces for multilayered interconnects Grant 8,512,849 - Clevenger , et al. August 20, 2	2013-08-20
Computer Readable Medium Encoded With A Program For Fabricating A 3d Integrated Circuit Structure App 20130189813 - FAROOQ; Mukta G. ; et al.	2013-07-25
3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer Grant 8,492,869 - Farooq , et al. July 23, 2	2013-07-23
Homogeneous porous low dielectric constant materials Grant 8,492,239 - Bruce , et al. July 23, 2	2013-07-23
Selectively coated self-aligned mask Grant 8,491,987 - Colburn , et al. July 23, 2	2013-07-23
Methods to mitigate plasma damage in organosilicate dielectrics Grant 8,481,423 - Arnold , et al. July 9, 2	2013-07-09
Process for enhanced 3D integration and structures generated using the same Grant 8,476,753 - Colgan , et al. July 2, 2	2013-07-02
Methods to mitigate plasma damage in organosilicate dielectrics Grant 8,470,706 - Arnold , et al. June 25, 2	2013-06-25
Self-aligned dual damascene BEOL structures with patternable low-k material and methods of forming same Grant 8,415,248 - Chen , et al. April 9, 2	2013-04-09
Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer Grant 8,399,336 - Farooq , et al. March 19, 2	2013-03-19
Protection of intermetal dielectric layers in multilevel wiring structures App 20130056874 - Darnon; Maxime ; et al.	2013-03-07
Programmable via devices Grant 8,389,967 - Chen , et al. March 5, 2	2013-03-05
Interconnect structures with engineered dielectrics with nanocolumnar porosity Grant 8,358,011 - Colburn , et al. January 22, 2	2013-01-22
Interconnect Structures With Engineered Dielectrics With Nanocolumnar Porosity App 20130009315 - Colburn; Matthew E. ; et al.	2013-01-10
Device and methodology for reducing effective dielectric constant in semiconductor devices Grant 8,343,868 - Edelstein , et al. January 1, 2	2013-01-01
Capping Coating for 3D Integration Applications App 20120329244 - Purushothaman; Sampath ; et al.	2012-12-27
Methods To Mitigate Plasma Damage In Organosilicate Dielectrics App 20120329269 - Arnold; John C. ; et al.	2012-12-27
Homogeneous Porous Low Dielectric Constant Materials App 20120329273 - Bruce; Robert L. ; et al.	2012-12-27
Interconnect structures with ternary patterned features generated from two lithographic processes Grant 8,338,952 - Colburn , et al. December 25, 2	2012-12-25
Process for Enhanced 3D Integration and Structures Generated Using the Same App 20120314994 - Colgan; Evan G. ; et al.	2012-12-13
Processes for enhanced 3D integration and structures generated using the same Grant 8,330,262 - Colgan , et al. December 11, 2	2012-12-11
Method For Fabricating 3d Integrated Circuit Device Using Interface Wafer As Permanent Carrier App 20120309127 - FAROOQ; Mukta G. ; et al.	2012-12-06
Process for Enhanced 3D Integration and Structures Generated Using the Same App 20120308241 - Colgan; Egan G. ; et al.	2012-12-06
Process for Enhanced 3D Integration and Structures Generated using the Same App 20120307444 - Colgan; Evan G. ; et al.	2012-12-06
METHOD OF PE-ALD OF SiNxCy AND INTEGRATION OF LINER MATERIALS ON POROUS LOW K SUBSTRATES App 20120301706 - Kellock; Andrew J. ; et al.	2012-11-29
3d Integrated Circuit Device Having Lower-cost Active Circuitry Layers Stacked Before Higher-cost Active Circuitry Layer App 20120299200 - FAROOQ; Mukta G. ; et al.	2012-11-29
Apparatus For Three-dimensional Integrated Circuit Device Fabrication Including Wafer Scale Membrane App 20120299145 - LA TULIPE, JR.; Douglas C. ; et al.	2012-11-29
Method Of Fabrication Of A Three-dimensional Integrated Circuit Device Using A Wafer Scale Membrane App 20120302040 - LA TULIPE, JR.; Douglas C. ; et al.	2012-11-29
Homogeneous porous low dielectric constant materials Grant 8,314,005 - Purushothaman , et al. November 20, 2	2012-11-20
Homogeneous Porous Low Dielectric Constant Materials App 20120282784 - Purushothaman; Sampath ; et al.	2012-11-08
3D integrated circuit device fabrication using interface wafer as permanent carrier Grant 8,298,914 - Farooq , et al. October 30, 2	2012-10-30
Interconnect Structures With Engineered Dielectrics With Nanocolumnar Porosity App 20120261823 - Colburn; Matthew E. ; et al.	2012-10-18
Self-aligned Dual Damascene Beol Structures With Patternable Low- K Material And Methods Of Forming Same App 20120231622 - Chen; Shyng-Tsong ; et al.	2012-09-13
High Memory Density, High Input/output Bandwidth Logic-memory Structure And Architecture App 20120233510 - Colgan; Evan G. ; et al.	2012-09-13
Bonding of substrates including metal-dielectric patterns with metal raised above dielectric Grant 8,241,995 - Chen , et al. August 14, 2	2012-08-14
Programmable via devices in back end of line level Grant 8,243,507 - Chen , et al. August 14, 2	2012-08-14
Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby App 20120193752 - Purushothaman; Sampath ; et al.	2012-08-02
3d Integrated Circuit Device Fabrication With Precisely Controllable Substrate Removal App 20120153429 - FAROOQ; Mukta G. ; et al.	2012-06-21
3d Integrated Circuit Device Fabrication With Precisely Controllable Substrate Removal App 20120149173 - Farooq; Mukta G. ; et al.	2012-06-14
Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer Grant 8,129,843 - Arnold , et al. March 6, 2	2012-03-06
Reducing effective dielectric constant in semiconductor devices Grant 8,129,286 - Edelstein , et al. March 6, 2	2012-03-06
3D integrated circuit device fabrication with precisely controllable substrate removal Grant 8,129,256 - Farooq , et al. March 6, 2	2012-03-06
Lock and key through-via method for wafer level 3D integration and structures produced Grant 8,093,099 - Purushothaman , et al. January 10, 2	2012-01-10
Programmable Via Devices in Back End of Line Level App 20110217836 - Chen; Kuan-Neng ; et al.	2011-09-08
Processes for Enhanced 3D Integration and Structures Generated Using the Same App 20110188209 - Colgan; Evan G. ; et al.	2011-08-04
Anisotropic stress generation by stress-generating liners having a sublithographic width Grant 7,989,291 - Clevenger , et al. August 2, 2	2011-08-02
Homogeneous Porous Low Dielectric Constant Materials App 20110183525 - Purushothaman; Sampath ; et al.	2011-07-28
Programmable via devices with air gap isolation Grant 7,977,203 - Chen , et al. July 12, 2	2011-07-12
Method To Generate Airgaps With A Template First Scheme And A Self Aligned Blockout Mask And Structure App 20110163446 - Nitta; Satyanarayana Venkata ; et al.	2011-07-07
Programmable via devices in back end of line level Grant 7,969,770 - Chen , et al. June 28, 2	2011-06-28
Methods for incorporating high dielectric materials for enhanced SRAM operation and structures produced thereby Grant 7,968,450 - Bhavnagarwala , et al. June 28, 2	2011-06-28
Electronics structures using a sacrificial multi-layer hardmask scheme Grant 7,947,907 - Colburn , et al. May 24, 2	2011-05-24
Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same Grant 7,948,051 - Colburn , et al. May 24, 2	2011-05-24
Spin-on antireflective coating for integration of patternable dielectric materials and interconnect structures Grant 7,944,055 - Allen , et al. May 17, 2	2011-05-17
Device And Methodology For Reducing Effective Dielectric Constant In Semiconductor Devices App 20110111590 - Edelstein; Daniel C. ; et al.	2011-05-12
Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced Thereby App 20110111560 - Purushothaman; Sampath ; et al.	2011-05-12
Photopatternable dielectric materials for BEOL applications and methods for use Grant 7,919,225 - Allen , et al. April 5, 2	2011-04-05
Data protection by detection of intrusion into electronic assemblies Grant 7,901,977 - Angelopoulos , et al. March 8, 2	2011-03-08
Device and methodology for reducing effective dielectric constant in semiconductor devices Grant 7,892,940 - Edelstein , et al. February 22, 2	2011-02-22
Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer Grant 7,880,305 - Cheng , et al. February 1, 2	2011-02-01
Method to generate airgaps with a template first scheme and a self aligned blockout mask Grant 7,863,150 - Colburn , et al. January 4, 2	2011-01-04
Methods To Mitigate Plasma Damage In Organosilicate Dielectrics Using A Protective Sidewall Spacer App 20100320617 - Arnold; John C. ; et al.	2010-12-23
Layer transfer process and functionally enhanced integrated circuits produced thereby Grant 7,855,101 - Furman , et al. December 21, 2	2010-12-21
Lock and key through-via method for wafer level 3 D integration and structures produced Grant 7,855,455 - Purushothaman , et al. December 21, 2	2010-12-21
3d Integrated Circuit Device Having Lower-cost Active Circuitry Layers Stacked Before Higher-cost Active Circuitry Layer App 20100314711 - Farooq; Mukta G. ; et al.	2010-12-16
Self-aligned Dual Damascene Beol Structures With Patternable Low- K Material And Methods Of Forming Same App 20100314767 - Chen; Shyng-Tsong ; et al.	2010-12-16
Surface treatment for selective metal cap applications Grant 7,830,010 - Yang , et al. November 9, 2	2010-11-09
Integrated wafer processing system for integration of patternable dielectric materials Grant 7,811,923 - Lin , et al. October 12, 2	2010-10-12
Bonding Of Substrates Including Metal-dielectric Patterns With Metal Raised Above Dielectric App 20100255262 - Chen; Kuan-Neng ; et al.	2010-10-07
Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer Grant 7,781,332 - Arnold , et al. August 24, 2	2010-08-24
Spin-on Antireflective Coating For Integration Of Patternable Dielectric Materials And Interconnect Structures App 20100207276 - Allen; Robert D. ; et al.	2010-08-19
Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced App 20100200992 - Purushothaman; Sampath ; et al.	2010-08-12
Treatment of plasma damaged layer for critical dimension retention, pore sealing and repair Grant 7,750,479 - Purushothaman , et al. July 6, 2	2010-07-06
Anisotropic Stress Generation By Stress-generating Liners Having A Sublithographic Width App 20100151638 - Clevenger; Lawrence A. ; et al.	2010-06-17
Spin-on antireflective coating for integration of patternable dielectric materials and interconnect structures Grant 7,709,370 - Allen , et al. May 4, 2	2010-05-04
Anisotropic stress generation by stress-generating liners having a sublithographic width Grant 7,696,542 - Clevenger , et al. April 13, 2	2010-04-13
Layer Transfer Process And Functionally Enhanced Integrated Circuits Produced Thereby App 20100081232 - Furman; Bruce K. ; et al.	2010-04-01
Lock and Key Through-Via Method for Wafer Level 3 D Integration and Structures Produced App 20100078770 - Purushothaman; Sampath ; et al.	2010-04-01
Recovery of hydrophobicity of low-k and ultra low-k organosilicate films used as inter metal dielectrics Grant 7,687,913 - Chakrapani , et al. March 30, 2	2010-03-30
METHOD OF PE-ALD OF SiNxCy AND INTEGRATION OF LINER MATERIALS ON POROUS LOW K SUBSTRATES App 20100055442 - Kellock; Andrew J. ; et al.	2010-03-04
3d Integrated Circuit Device Fabrication Using Interface Wafer As Permanent Carrier App 20100047964 - FAROOQ; Mukta G. ; et al.	2010-02-25
3d Integrated Circuit Device Fabrication With Precisely Controllable Substrate Removal App 20100044826 - FAROOQ; Mukta G. ; et al.	2010-02-25
Methods For Incorporating High Dielectric Materials For Enhanced Sram Operation And Structures Produced Thereby App 20100041227 - Bhavnagarwala; Azeez J. ; et al.	2010-02-18
Programmable via devices with air gap isolation Grant 7,659,534 - Chen , et al. February 9, 2	2010-02-09
Wafer Scale Membrane For Three-dimensional Integrated Circuit Device Fabrication App 20100006972 - LA TULIPE, JR.; DOUGLAS C. ; et al.	2010-01-14
Method For Enabling Hard Mask Free Integration Of Ultra Low-k Materials And Structures Produced Thereby App 20090311859 - Bonilla; Griselda ; et al.	2009-12-17
Programmable fuse/non-volatile memory structures in BEOL regions using externally heated phase change material Grant 7,633,079 - Chen , et al. December 15, 2	2009-12-15
Programmable Via Devices with Air Gap Isolation App 20090305460 - Chen; Kuan-Neng ; et al.	2009-12-10
Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer App 20090302454 - Cheng; Yu- Ting ; et al.	2009-12-10
Interconnect Structures With Ternary Patterned Features Generated From Two Lithographic Processes App 20090294982 - Colburn; Matthew E. ; et al.	2009-12-03
Photopatternable Dielectric Materials For Beol Applications And Methods For Use App 20090291389 - Allen; Robert D. ; et al.	2009-11-26
Programmable Via Devices App 20090291546 - Chen; Kuan-Neng ; et al.	2009-11-26
Surface Treatment For Selective Metal Cap Applications App 20090250815 - YANG; CHIH-CHAO ; et al.	2009-10-08
Device and methodology for reducing effective dielectric constant in semiconductor devices Grant 7,592,685 - Edelstein , et al. September 22, 2	2009-09-22
Techniques for Layer Transfer Processing App 20090233079 - Bedell; Stephen W. ; et al.	2009-09-17
Anisotropic Stress Generation By Stress-generating Liners Having A Sublithographic Width App 20090184374 - Clevenger; Lawrence A. ; et al.	2009-07-23
Static random access memory cell with improved stability Grant 7,545,671 - Bhavnagarwala , et al. June 9, 2	2009-06-09
Method of Forming Programmable Via Devices App 20090111263 - Chen; Kuan-Neng ; et al.	2009-04-30
Programmable Via Devices App 20090101882 - Chen; Kuan-Neng ; et al.	2009-04-23
Method of producing self-aligned mask in conjunction with blocking mask, articles produced by same and composition for same Grant 7,517,637 - Colburn , et al. April 14, 2	2009-04-14
Spin-on Antireflective Coating For Integration Of Patternable Dielectric Materials And Interconnect Structures App 20090081418 - Allen; Robert D. ; et al.	2009-03-26
Methods To Mitigate Plasma Damage In Organosilicate Dielectrics App 20090075472 - Arnold; John C. ; et al.	2009-03-19
Methods To Mitigate Plasma Damage In Organosilicate Dielectrics Using A Protective Sidewall Spacer App 20090072401 - Arnold; John C. ; et al.	2009-03-19
Programmable Fuse/non-volatile Memory Structures In Beol Regions Using Externally Heated Phase Change Material App 20090065761 - Chen; Kuang-Neng ; et al.	2009-03-12
Capping Coating for 3D Integration Applications App 20090042338 - Purushothaman; Sampath ; et al.	2009-02-12
Corrugated Interfaces For Multilayered Interconnects App 20090041989 - Clevenger; Lawrence A. ; et al.	2009-02-12
Programmable Via Devices In Back End Of Line Level App 20090033358 - Chen; Kuan-Neng ; et al.	2009-02-05
Programmable Via Devices With Air Gap Isolation App 20090033360 - Chen; Kuan-Neng ; et al.	2009-02-05
Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same Grant 7,485,341 - Colburn , et al. February 3, 2	2009-02-03
Integrated Wafer Processing System for Integration of Patternable Dielectric Materials App 20090023284 - Lin; Qinghuang ; et al.	2009-01-22
Electrically conducting adhesives for via fill applications Grant 7,467,742 - Gelorme , et al. December 23, 2	2008-12-23
Interconnect Structures With Ternary Patterned Features Generated From Two Lithographic Processes App 20080284039 - Colburn; Matthew E. ; et al.	2008-11-20
Layer Transfer Process and Functionally Enhanced Integrated Circuits Products Thereby App 20080277778 - Furman; Bruce K. ; et al.	2008-11-13
Techniques for Layer Transfer Processing App 20080280416 - Bedell; Stephen W. ; et al.	2008-11-13
Nonlithographic Method to Produce Self-Aligned Mask, Articles Produced by Same and Compositions for Same App 20080265382 - Colburn; Matthew E. ; et al.	2008-10-30
Nonlithographic Method to Produce Self-Aligned Mask, Articles Produced by Same and Compositions for Same App 20080265415 - Colburn; Matthew E. ; et al.	2008-10-30
Device And Methodology For Reducing Effective Dielectric Constant In Semiconductor Devices App 20080254630 - EDELSTEIN; Daniel C. ; et al.	2008-10-16
Electronics Structures Using a Sacrificial Multi-Layer Hardmask Scheme App 20080251284 - Colburn; Matthew Earl ; et al.	2008-10-16
Static Random Access Memory Cell With Improved Stability App 20080225573 - Bhavnagarwala; Azeez ; et al.	2008-09-18
Device and methodology for reducing effective dielectric constant in semiconductor devices Grant 7,405,147 - Edelstein , et al. July 29, 2	2008-07-29
Fabrication of Interconnect Structures App 20080166870 - Huang; Elbert Emin ; et al.	2008-07-10
Static random access memory cell with improved stability Grant 7,397,691 - Bhavnagarwala , et al. July 8, 2	2008-07-08
Method of forming closed air gap interconnects and structures formed thereby Grant 7,393,776 - Colburn , et al. July 1, 2	2008-07-01
Method to generate airgaps with a template first scheme and a self aligned blockout mask App 20080122106 - Nitta; Satyanarayana Venkata ; et al.	2008-05-29
Process for preparing electronics structures using a sacrificial multilayer hardmask scheme Grant 7,371,684 - Colburn , et al. May 13, 2	2008-05-13
Closed air gap interconnect structure Grant 7,361,991 - Saenger , et al. April 22, 2	2008-04-22
Treatment Of Plasma Damaged Layer For Critical Dimension Retention, Pore Sealing And Repair App 20080042283 - Purushothaman; Sampath ; et al.	2008-02-21
Device And Methodology For Reducing Effective Dielectric Constant In Semiconductor Devices App 20080038923 - EDELSTEIN; Daniel C. ; et al.	2008-02-14
Device And Methodology For Reducing Effective Dielectric Constant In Semiconductor Devices App 20080038915 - EDELSTEIN; Daniel C. ; et al.	2008-02-14
Method of forming closed air gap interconnects and structures formed thereby Grant 7,309,649 - Colburn , et al. December 18, 2	2007-12-18
Techniques for Layer Transfer Processing App 20070281439 - Bedell; Stephen W. ; et al.	2007-12-06
Static random access memory cell with improved stability App 20070247896 - Bhavnagarwala; Azeez ; et al.	2007-10-25
Method For Enabling Hard Mask Free Integration Of Ultra Low-k Materials And Structures Produced Thereby App 20070249156 - Bonilla; Griselda ; et al.	2007-10-25
Interconnect structures with engineered dielectrics with nanocolumnar porosity Grant 7,268,432 - Colburn , et al. September 11, 2	2007-09-11
Recovery Of Hydrophobicity Of Low-k And Ultra Low-k Organosilicate Films Used As Inter Metal Dielectrics App 20070138640 - Chakrapani; Nirupama ; et al.	2007-06-21
Recovery of hydrophobicity of low-k and ultra low-k organosilicate films used as inter metal dielectrics Grant 7,179,758 - Chakrapani , et al. February 20, 2	2007-02-20
Method of forming closed air gap interconnects and structures formed thereby App 20060267208 - Colburn; Matthew E. ; et al.	2006-11-30
Line level air gaps App 20060264036 - Chen; Shyng-Tsong ; et al.	2006-11-23
Process for preparing electronics structures using a sacrificial multilayer hardmask scheme App 20060258159 - Colburn; Matthew Earl ; et al.	2006-11-16
Method of forming closed air gap interconnects and structures formed thereby App 20060258147 - Colburn; Matthew E. ; et al.	2006-11-16
Multilayer interconnect structure containing air gaps and method for making Grant 7,098,476 - Babich , et al. August 29, 2	2006-08-29
Line level air gaps Grant 7,084,479 - Chen , et al. August 1, 2	2006-08-01
Methods for incorporating high k dielectric materials for enhanced SRAM operation and structures produced thereby App 20060103023 - Bhavnagarwala; Azeez J. ; et al.	2006-05-18
Very low effective dielectric constant interconnect structures and methods for fabricating the same Grant 7,045,453 - Canaperi , et al. May 16, 2	2006-05-16
Method for fabricating a self-aligned nanocolumnar airbridge and structure produced thereby Grant 7,037,744 - Colburn , et al. May 2, 2	2006-05-02
High density chip carrier with integrated passive devices Grant 7,030,481 - Chudzik , et al. April 18, 2	2006-04-18
Method for fabricating a self-aligned nanocolumnar airbridge and structure produced thereby Grant 7,030,495 - Colburn , et al. April 18, 2	2006-04-18
Very low effective dielectric constant interconnect Structures and methods for fabricating the same Grant 7,023,093 - Canaperi , et al. April 4, 2	2006-04-04
Method for fabricating a self-aligned nanocolumnar airbridge and structure produced thereby App 20050272341 - Colburn, Matthew E. ; et al.	2005-12-08
High density chip carrier with integrated passive devices Grant 6,962,872 - Chudzik , et al. November 8, 2	2005-11-08
Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same App 20050233597 - Colburn, Matthew E. ; et al.	2005-10-20
Method of producing self-aligned mask in conjuction with blocking mask, articles produced by same and composition for same App 20050208430 - Colburn, Matthew E. ; et al.	2005-09-22
Method For Fabricating A Self-aligned Nanocolumnar Airbridge And Structure Produced Thereby App 20050208752 - Colburn, Matthew E. ; et al.	2005-09-22
Semiconductor devices containing a discontinuous cap layer and methods for forming same Grant 6,943,451 - Whitehair , et al. September 13, 2	2005-09-13
Very low effective dielectric constant interconnect structures and methods for fabricating the same App 20050186778 - Canaperi, Donald F. ; et al.	2005-08-25
Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence Grant 6,930,034 - Colburn , et al. August 16, 2	2005-08-16
Device And Methodology For Reducing Effective Dielectric Constant In Semiconductor Devices App 20050167838 - Edelstein, Daniel C. ; et al.	2005-08-04
Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same Grant 6,911,400 - Colburn , et al. June 28, 2	2005-06-28
Line level air gaps App 20050127514 - Chen, Shyng-Tsong ; et al.	2005-06-16
Recovery of hydrophobicity of low-k and ultra low-k organosilicate films used as inter metal dielectrics App 20050106762 - Chakrapani, Nirupama ; et al.	2005-05-19
Techniques for layer transfer processing App 20050082526 - Bedell, Stephen W. ; et al.	2005-04-21
Interconnect structures with engineered dielectrics with nanocolumnar porosity App 20050079719 - Colburn, Matthew E. ; et al.	2005-04-14
Method of forming closed air gap interconnects and structures formed thereby App 20050062165 - Saenger, Katherine L. ; et al.	2005-03-24
Multilayer interconnect structure containing air gaps and method for making App 20050037604 - Babich, Katherina E. ; et al.	2005-02-17
High density chip carrier with integrated passive devices App 20050023664 - Chudzik, Michael Patrick ; et al.	2005-02-03
Method for forming a porous dielectric material layer in a semiconductor device and device formed Grant 6,831,364 - Dalton , et al. December 14, 2	2004-12-14
Interconnects containing first and second porous low-k dielectrics separated by a porous buried etch stop layer Grant 6,831,366 - Gates , et al. December 14, 2	2004-12-14
High density area array solder microjoining interconnect structure and fabrication method Grant 6,819,000 - Magerlein , et al. November 16, 2	2004-11-16
Multilayer interconnect structure containing air gaps and method for making Grant 6,815,329 - Babich , et al. November 9, 2	2004-11-09
Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same App 20040213971 - Colburn, Matthew E. ; et al.	2004-10-28
Diffusion barrier layer and semiconductor device containing same Grant 6,784,485 - Cohen , et al. August 31, 2	2004-08-31
Ordered two-phase dielectric film, and semiconductor device containing the same Grant 6,780,499 - Gates , et al. August 24, 2	2004-08-24
Capping coating for 3D integration applications App 20040150096 - Purushothaman, Sampath ; et al.	2004-08-05
Stabilization of fluorine-containing low-k dielectrics in a metal/insulator wiring structure by ultraviolet irradiation Grant 6,759,321 - Babich , et al. July 6, 2	2004-07-06
Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence App 20040127001 - Colburn, Matthew E. ; et al.	2004-07-01
High density chip carrier with integrated passive devices App 20040108587 - Chudzik, Michael Patrick ; et al.	2004-06-10
Temporary device attach structure for test and burn in of microjoint interconnects and method for fabricating the same Grant 6,747,472 - Magerlein , et al. June 8, 2	2004-06-08
Multilevel interconnect structure containing air gaps and method for making Grant 6,737,725 - Grill , et al. May 18, 2	2004-05-18
Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer App 20040089948 - Cheng, Yu-Ting ; et al.	2004-05-13
High density raised stud microjoining system and methods of fabricating the same Grant 6,732,908 - Furman , et al. May 11, 2	2004-05-11
Very low effective dielectric constant interconnect Structures and methods for fabricating the same App 20040087135 - Canaperi, Donald F. ; et al.	2004-05-06
Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same App 20040087176 - Colburn, Matthew E. ; et al.	2004-05-06
High density area array solder microjoining interconnect structure and fabrication method App 20040084782 - Magerlein, John Harold ; et al.	2004-05-06
Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same App 20040087177 - Colburn, Matthew E. ; et al.	2004-05-06
Laminated diffusion barrier Grant 6,726,996 - Barth , et al. April 27, 2	2004-04-27
Spin-on cap layer, and semiconductor device containing same Grant 6,724,069 - Dalton , et al. April 20, 2	2004-04-20
Protective hardmask for producing interconnect structures Grant 6,720,249 - Dalton , et al. April 13, 2	2004-04-13
Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics Grant 6,716,742 - Gates , et al. April 6, 2	2004-04-06
Interconnect structure with precise conductor resistance and method to form same Grant 6,710,450 - Gates , et al. March 23, 2	2004-03-23
Semiconductor recessed mask interconnect technology App 20040051178 - Cohen, Stephen Alan ; et al.	2004-03-18
Liquid crystal display cell having liquid crystal molecules in vertical or substantially vertical alignment Grant 6,682,786 - Lien , et al. January 27, 2	2004-01-27
Process for forming a multi-level thin-film electronic packaging structure Grant 6,678,949 - Prasad , et al. January 20, 2	2004-01-20
Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials Grant 6,677,680 - Gates , et al. January 13, 2	2004-01-13
High density area array solder microjoining interconnect structure and fabrication method Grant 6,661,098 - Magerlein , et al. December 9, 2	2003-12-09
Semiconductor recessed mask interconnect technology Grant 6,657,305 - Cohen , et al. December 2, 2	2003-12-02
Structure comprising beam leads bonded with electrically conductive adhesive Grant 6,646,355 - Kang , et al. November 11, 2	2003-11-11
Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same Grant 6,641,899 - Colburn , et al. November 4, 2	2003-11-04
Method of making a lamination and surface planarization for multilayer thin film interconnect Grant 6,632,314 - Yu , et al. October 14, 2	2003-10-14
Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics App 20030183937 - Gates, Stephen McConnell ; et al.	2003-10-02
Electrically conductive filled through holes App 20030162047 - Appelt, Bernd K. ; et al.	2003-08-28
Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics Grant 6,603,204 - Gates , et al. August 5, 2	2003-08-05
High density raised stud microjoining system and methods of fabricating the same App 20030136814 - Furman, Bruce Kenneth ; et al.	2003-07-24
Temporary device attach structure for test and burn in of microjoint interconnects and method for fabricating the same App 20030136813 - Magerlein, John Harold ; et al.	2003-07-24
High density area array solder microjoining interconnect structure and fabrication method App 20030137058 - Magerlein, John Harold ; et al.	2003-07-24
Self alignment of substrates by magnetic alignment Grant 6,583,847 - Callegari , et al. June 24, 2	2003-06-24
Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same Grant 6,577,011 - Buchwalter , et al. June 10, 2	2003-06-10
Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics App 20030075803 - Gates, Stephen McConnell ; et al.	2003-04-24
Method for forming a porous dielectric material layer in a semiconductor device and device formed App 20030057414 - Dalton, Timothy Joseph ; et al.	2003-03-27
An Electronic Package Having A Substrate With Electrically Conductive Filled Through Holes App 20030006066 - APPELT, BERND K. ; et al.	2003-01-09
Semiconductor devices containing a discontinuous cap layer and methods for forming same App 20030001240 - Whitehair, Stanley Joseph ; et al.	2003-01-02
Method for patterning sensitive organic thin films Grant 6,500,604 - Dimitrakopoulos , et al. December 31, 2	2002-12-31
Self alignment of substrates App 20020191143 - Callegari, Alessandro C. ; et al.	2002-12-19
Stabilization of fluorine-containing low-k dielectrics in a metal/insulator wiring structure by ultraviolet irradiation App 20020185741 - Babich, Katherina ; et al.	2002-12-12
Laminated diffusion barrier App 20020172811 - Barth, Edward Paul ; et al.	2002-11-21
Ordered two-phase dielectric film, and semiconductor device containing the same App 20020164891 - Gates, Stephen McConnell ; et al.	2002-11-07
Multilayer interconnect structure containing air gaps and method for making App 20020158337 - Babich, Katherina E. ; et al.	2002-10-31
Spin-on cap layer, and semiconductor device containing same App 20020145200 - Dalton, Timothy Joseph ; et al.	2002-10-10
Method for forming a porous dielectric material layer in a semiconductor device and device formed Grant 6,451,712 - Dalton , et al. September 17, 2	2002-09-17
Multilevel interconnect structure containing air gaps and method for making App 20020127844 - Grill, Alfred ; et al.	2002-09-12
Interconnect structure with precise conductor resistance and method to form same App 20020117737 - Gates, Stephen McConnell ; et al.	2002-08-29
Method for dual-damascene patterning of low-k interconnects using spin-on distributed hardmask App 20020119654 - Fornof, Ann Rhea-Helene ; et al.	2002-08-29
Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics App 20020117760 - Gates, Stephen McConnell ; et al.	2002-08-29
Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials App 20020117754 - Gates, Stephen McConnell ; et al.	2002-08-29
Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material Grant 6,413,852 - Grill , et al. July 2, 2	2002-07-02
Method for forming a porous dielectric material layer in a semiconductor device and device formed App 20020074659 - Dalton, Timothy Joseph ; et al.	2002-06-20
Interconnections with electrically conductive adhesives: structures, materials, method and their applications App 20020056925 - Kang, Sung Kwon ; et al.	2002-05-16
Method for improving performance of organic semiconductors in bottom electrode structure App 20020045289 - Dimitrakopoulos, Christos Dimitrios ; et al.	2002-04-18
Stabilization Of Fluorine-containing Low-k Dielectrics In A Metal/insulator Wiring Structure By Ultraviolet Irradiation App 20020033535 - BABICH, KATHERINA ; et al.	2002-03-21
Structure employing electrically conductive adhesives Grant 6,337,522 - Kang , et al. January 8, 2	2002-01-08
Method for improving performance of organic semiconductors in bottom electrode structure Grant 6,335,539 - Dimitrakopoulos , et al. January 1, 2	2002-01-01
Process for forming a multi-level thin-film electronic packaging structure App 20010037565 - Prasad, Chandrika ; et al.	2001-11-08
Structure, materials, and methods for socketable ball grid Grant 6,300,164 - Call , et al. October 9, 2	2001-10-09
Structure, materials, and applications of ball grid array interconnections Grant 6,297,559 - Call , et al. October 2, 2	2001-10-02
Multi-level thin-film electronic packaging structure and related method Grant 6,281,452 - Prasad , et al. August 28, 2	2001-08-28
Low temperature thin film transistor fabrication App 20010015438 - Callegari, Alessandro Cesare ; et al.	2001-08-23
Metal embedded passivation layer structure for microelectronic interconnect formation, customization and repair Grant 6,255,671 - Bojarczuk, Jr. , et al. July 3, 2	2001-07-03
High conductivity, high strength, lead-free, low cost, electrically conducting materials and applications Grant 6,238,599 - Gelorme , et al. May 29, 2	2001-05-29
Flip-Chip interconnections using lead-free solders Grant 6,224,690 - Andricacos , et al. May 1, 2	2001-05-01
Low temperature thin film transistor fabrication Grant 6,207,472 - Callegari , et al. March 27, 2	2001-03-27
Corrosion-free multi-layer conductor Grant 6,203,926 - Ahmad , et al. March 20, 2	2001-03-20
Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same Grant 6,184,121 - Buchwalter , et al. February 6, 2	2001-02-06
Structure, materials, and methods for socketable ball grid Grant 6,120,885 - Call , et al. September 19, 2	2000-09-19
Thermally conducting materials and applications for microelectronic packaging Grant 6,114,413 - Kang , et al. September 5, 2	2000-09-05
Precision alignment of plates Grant 6,104,466 - Buchwalter , et al. August 15, 2	2000-08-15
Alignment of liquid crystal layers Grant 6,061,114 - Callegari , et al. May 9, 2	2000-05-09
Method of fabricating coated powder materials and their use for high conductivity paste applications Grant 6,059,952 - Kang , et al. May 9, 2	2000-05-09
Dry processing for liquid-crystal displays using low energy ion bombardment Grant 6,020,946 - Callegari , et al. February 1, 2	2000-02-01
Method for providing discharge protection or shielding Grant 5,997,773 - Angelopoulos , et al. December 7, 1	1999-12-07
Housing for electromagnetic interference shielding Grant 5,985,458 - Angelopoulos , et al. November 16, 1	1999-11-16
Thin-film field-effect transistor with organic semiconductor requiring low operating voltages Grant 5,981,970 - Dimitrakopoulos , et al. November 9, 1	1999-11-09
Dendritic powder materials for high conductivity paste applications Grant 5,958,590 - Kang , et al. September 28, 1	1999-09-28
Fabrication of thin film effect transistor comprising an organic semiconductor and chemical solution deposited metal oxide gate dielectric Grant 5,946,551 - Dimitrakopoulos , et al. August 31, 1	1999-08-31
Composite comprising a metal substrate and a corrosion protecting layer Grant 5,922,466 - Angelopoulos , et al. July 13, 1	1999-07-13
Method for providing discharge protection or shielding Grant 5,916,486 - Angelopoulos , et al. June 29, 1	1999-06-29
Electronic devices having metallurgies containing copper-semiconductor compounds Grant 5,855,993 - Brady , et al. January 5, 1	1999-01-05
Sputter deposition of hydrogenated amorphous carbon film and applications thereof Grant 5,830,332 - Babich , et al. November 3, 1	1998-11-03
Composition containing a polymer and conductive filler and use thereof Grant 5,700,398 - Angelopoulos , et al. December 23, 1	1997-12-23
Electronic devices having metallurgies containing copper-semiconductor compounds Grant 5,633,047 - Brady , et al. May 27, 1	1997-05-27
Adhesive layer in multi-level packaging and organic material as a metal diffusion barrier Grant 5,582,858 - Adamopoulos , et al. December 10, 1	1996-12-10
Diamond-like carbon films from a hydrocarbon helium plasma Grant 5,569,501 - Bailey , et al. October 29, 1	1996-10-29
Method for fabricating multi-layer thin film structure having a separation layer Grant 5,534,094 - Arjavalingam , et al. July 9, 1	1996-07-09
Electronic package having active means to maintain its operating temperature constant Grant 5,491,610 - Mok , et al. February 13, 1	1996-02-13
Module input-output pad having stepped set-back Grant 5,483,105 - Kaja , et al. January 9, 1	1996-01-09
Diamond-like carbon films from a hydrocarbon helium plasma Grant 5,470,661 - Bailey , et al. November 28, 1	1995-11-28
Interconnect structure having improved metallization Grant 5,436,412 - Ahmad , et al. July 25, 1	1995-07-25
Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal Grant 5,420,073 - DiGiacomo , et al. May 30, 1	1995-05-30
Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal Grant 5,367,195 - DiGiacomo , et al. November 22, 1	1994-11-22
Adhesive layer in multi-level packaging and organic material as a metal diffusion barrier Grant 5,326,643 - Adamopoulos , et al. July 5, 1	1994-07-05
Methods for etching a less reactive material in the presence of a more reactive material Grant 5,304,284 - Jagannathan , et al. April 19, 1	1994-04-19
Multi-layer thin film structure and parallel processing method for fabricating same Grant 5,258,236 - Arjavalingam , et al. November 2, 1	1993-11-02
Composition and coating to prevent current induced electrochemical dendrite formation between conductors on dielectric substrate Grant 5,074,969 - Brewer , et al. December 24, 1	1991-12-24
Composition and coating to prevent current induced electrochemical dendrite formation between conductors on dielectric substrate Grant 5,038,195 - Brewer , et al. August 6, 1	1991-08-06
Multilayered metallurgical structure for an electronic component Grant 4,985,310 - Agarwala , et al. January 15, 1	1991-01-15