U.S. patent application number 12/983885 was filed with the patent office on 2011-07-07 for method to generate airgaps with a template first scheme and a self aligned blockout mask and structure.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Matthew E. Colburn, Daniel C. Edelstein, Satyanarayana Venkata Nitta, Shom Ponoth, Sampath PURUSHOTHAMAN.
Application Number | 20110163446 12/983885 |
Document ID | / |
Family ID | 39462831 |
Filed Date | 2011-07-07 |
United States Patent
Application |
20110163446 |
Kind Code |
A1 |
Nitta; Satyanarayana Venkata ;
et al. |
July 7, 2011 |
METHOD TO GENERATE AIRGAPS WITH A TEMPLATE FIRST SCHEME AND A SELF
ALIGNED BLOCKOUT MASK AND STRUCTURE
Abstract
A structure and method to produce an airgap on a substrate
having a dielectric layer and copper interconnects with
sublithographic perforations therein which are ordered throughout
the wafer structure in a macro level and a micro level with no
change in order orientation and the top layer of the copper
interconnects are not exposed.
Inventors: |
Nitta; Satyanarayana Venkata;
(POUGHQUAG, NY) ; PURUSHOTHAMAN; Sampath;
(Yorktown Heights, NY) ; Colburn; Matthew E.;
(Hopewell Junction, NY) ; Edelstein; Daniel C.;
(White Plains, NY) ; Ponoth; Shom; (Fishkill,
NY) |
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
Armonk
NY
|
Family ID: |
39462831 |
Appl. No.: |
12/983885 |
Filed: |
January 4, 2011 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11518773 |
Sep 11, 2006 |
7863150 |
|
|
12983885 |
|
|
|
|
Current U.S.
Class: |
257/741 ;
257/E23.01 |
Current CPC
Class: |
H01L 21/7682
20130101 |
Class at
Publication: |
257/741 ;
257/E23.01 |
International
Class: |
H01L 23/48 20060101
H01L023/48 |
Claims
1. A wafer containing an interconnect structure with airgaps
comprising: a) a substrate having at least one dielectric cap layer
on the substrate, and at least two copper interconnects with a top
layer and with spaces between the copper interconnects; and b)
multiple sublithographic perforations in the cap layer on top of
the interconnect and which overlay the spaces between the copper
interconnects and not overlying the copper interconnects, wherein
the perforations are ordered throughout the wafer with no change in
order orientation and the top layer of the copper interconnects are
not exposed.
2. The structure of claim 1 wherein the perforations are supra
lithographic.
3. The structure of claim 1 wherein the perforations in the cap
layer are pinched off with multiple and discrete pinch-points
within a given space between the copper interconnects and having
pinch-off heights that are on order of the perforations.
4. The structure of claim 1 wherein the perforations are at least
as small as the minimum distance between the copper
interconnects.
5. The structure of claim 1 wherein the perforations are smaller
than the minimum distance between the copper interconnects.
6. The structure of claim 1 wherein the perforations exceeds the
depth of the copper interconnects.
7. The structure of claim 6 wherein the depth of the transferred
perforations in the dielectric layer is at least 25% deeper than
the depth of the copper interconnects.
8. The structure of claim 1 wherein perforation size is reduced by
silyation.
9. The structure of claim 1 wherein perforation size is reduced by
the deposition of a self assembled monolayer.
10. The structure of claim 1 further comprising a resist layer on
the cap layer having multiple perforations wherein the perforation
size in the resist layer is reduced using chemically assisted
shrinks.
11. The structure of claim 1 further comprising a conformal layer
which is about 5 nm to about 25 nm thick.
12. The structure of claim 1 further comprising a self assembled
monolayer on top of the cap layer and wherein the self assembled
monolayer is a long chain aliphatic compound.
13. The structure of claim 12 wherein the self assembled monolayer
is a long chain aromatic compound.
14. The structure of claim 12 wherein the self assembled monolayer
is a long chain aliphatic compound.
15. The structure of claim 1 further comprising an at least second
cap layer.
16. The structure of claim 15 wherein the at least second cap layer
is deposited via flash deposition, wherein the second cap layer
protects any exposed copper during pinching-off and wherein the
perforations are pinched off by the deposition of the second cap
layer.
17. The structure of claim 1 further comprising a second dielectric
layer.
18. The structure of claim 1 further comprising a compressive film
at every level to interrupt the build up of the air gaps and
tensile stress areas.
19. A wafer containing an interconnect structure with airgaps
comprising: a) a substrate having at least one dielectric cap layer
on the substrate, and multiple copper interconnects each with a top
layer and with spaces between the copper interconnects; and b)
multiple sublithographic perforations in the cap layer on top of
the interconnect and which overlay the spaces between the copper
interconnects and not overlying the copper interconnects and
wherein the perforations are smaller than the minimum distance
between the copper interconnects, wherein the perforations are
ordered throughout the wafer in a macro level and a micro level
with no change in order orientation and the top layer of the copper
interconnects are not exposed.
20. A wafer containing an interconnect structure with airgaps
comprising: a) a substrate having at least one dielectric cap layer
on the substrate, and multiple copper interconnects each with a top
layer and with spaces between the copper interconnects; b) a
conformal layer which is about 5 nm to about 25 nm thick; c) a
second dielectric layer; and d) multiple sublithographic
perforations in the cap layer on top of the interconnect and which
overlay the spaces between the copper interconnects and not
overlying the copper interconnects and wherein the perforations are
at least as deep as a height of the copper interconnects, wherein
the perforations are ordered throughout the wafer in a macro level
and a micro level with no change in order orientation and the top
layer of the copper interconnects are not exposed.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This is a divisional application of co-pending application
Ser. No. 11/518,773 filed on Sep. 11, 2006.
FIELD OF THE INVENTION
[0002] The present invention relates to a method of producing air
gap-containing metal-insulator interconnect structures for Very
Large Scale Integrated (VLSI) and Ultra-Large Scale Integrated
(ULSI) devices and such structures.
BACKGROUND OF THE INVENTION
[0003] There are many known techniques for lowering the effective
dielectric constant for the dielectrics used in semiconductor
devices, however most of these methods suffer from several
drawbacks including poor mechanical strength. This poor mechanical
strength results in reliability issues in the final device.
[0004] For example, one methodology for creating insulator voids
(gaps, airgaps, etc.) in dielectric materials embedded in
multilevel integrated interconnect structures to lower the
effective dielectric constant includes the combination of supra
lithographic plus sub-lithographic masking to create selectively
blocked-out nanocolumns or airgaps in an already-built wiring level
as disclosed in US2005/0167838A1. The method includes at least one
layer of a block out mask and a layer of diblock copolymer which
forms tiny self assembled perforations (200A in a polymeric matrix
which are then transferred into the underlying dielectric to create
a nanocolumnar structure. Further, ways to isotropically increase
column or gap size underneath a perforated mask, such that larger
gaps could be made without impacting rapid pinch off are described.
However, problems exist with this method. For example, it is not
readily practicable for larger dimension copper wiring levels. When
supra-lithographic block out shapes are combined with a self
assembled layer to create a sublithographic nanocolumnar structure,
significant areas of the copper interconnect surfaces are exposed
to etch, strip, and wet clean processes through the nano-sized
perforated perforations in the cap. Although these perforations may
be plugged by the subsequent pinchoff deposition of an additional
cap dielectric material, there may be excessive copper sputtered
through the perforations, and possibly integration defects
associated with these copper and copper/cap interface exposures.
Another potential problem is scaling to very large dimension wiring
levels due to increased aspect ratios for nanocolumn etching,
assuming the sublithographic mask perforations could not be scaled
accordingly. Finally, such method requires two cycles of mask
apply, develop, and reactive ion etching for the diblock and
blockout pattern transfer.
[0005] A different method for forming an airgap is described in US
2006/0183315 (Ser. No. 10/906,267) using electron-beam and UV
radiation to selectively damage the SiCOH interlayer dielectric. A
blockout mask limits exposure to the electron-beam or UV such that
only the areas not covered by the blockout mask get exposed to the
radiation with the result that the exposed regions of the
dielectric are demethylated and are thus rendered etchable However,
the main drawback of this method is that the depth and extent to
which the UV or the electron-beam demethylates damages the SiCOH
dielectric and the damaged dielectric may extend all the way to the
depth of the trench.
[0006] An etchback process is disclosed in Integration of a 3 Level
Cu--SiO2 Air Gap Interconnect for Sub 0.1 micron CMOS Technologies
(2001 Proc. IEEE International Interconnect Technology Conference,
2001, pages 298-300, Arnal et al.) wherein a full trench is etched
through a lithographic mask into the underlying dielectric. A
pinch-off airgap is then formed during the deposition of the next
level of dielectric. This method has several drawbacks including
problems of excess topography in the next level after dielectric
deposition which requires added chemically-mechanically polished
touchup or changes to the interlayer dielectric process as well as
excess redeposition in airgaps, and in the extreme, pinch-off
points which are so high that they can interfere with trenches on
the subsequent wiring level. Additionally, in this method, there
will be situations where there are several levels of dielectric and
pinch-off airgap that can be stacked on top of each other without
any intervening compressive film to break up the buildup of tensile
stress with the result that this structure is mechanically
unstable. Finally, this method does not scale well with shrinking
dimensions and airgaps at the thin wire level using aggressive
shrink factors and cannot easily be fabricated using it due to the
fact that there will be exposed copper along the entire length of
an interconnect during the etchback resulting in electromigration
failures during reliability stressing.
[0007] Thus there exists a need for an airgap method which limits
exposed copper during etching and in some cases eliminates it. A
further need exists for an airgap method where pinch-off heights
are limited such that the trench bottoms from the subsequent level
do not intersect the pinch-off gaps.
[0008] There further exists a need for an airgap structure where
there is no build-up of topography after the subsequent level
dielectric deposition. Another need exists for an airgap structure
where there is no build-up of tensile dielectric or airgap without
compressive films to interrupt the build up of the gaps and tensile
stress areas. There further exists a need for an airgap method
where the depth of the gap is not limited by limitations of etch
due to high aspect ratios.
[0009] A need further exists for an airgap method where the depth
of the gap is not limited by the depth to which the dielectric can
be demethylated and thus rendered etchable. Additionally, a need
exists for a streamlined airgap method with less masking and
etching steps per wiring level while still ensuring that the gaps
can be made at thin wire levels which are close to the transistor
as well as "fat" wires which reside at the upper levels of the
interconnect scheme in a hierarchical structure.
[0010] These needs and many others are met by a process for
producing airgaps on a substrate using the inventive method which
uses a self aligned template with sub and supra lithographic
perforations within a blockout mask and the structure. Other
advantages of the present invention will become apparent from the
following description and appended claims.
DRAWINGS
[0011] FIG. 1 is a process flow of the present invention for
generating airgaps.
[0012] FIG. 2 is a schematic of alternate perforation shapes of a
mask of the present invention.
[0013] FIG. 3 is a representation of tolerance considerations for
block out and gap image sizes of a mask of the present
invention.
[0014] FIG. 4 is alternate process flows of the present invention
for generating airgaps.
SUMMARY OF INVENTION
[0015] The invention includes a method to produce an airgap on a
substrate comprising a dielectric layer on the substrate, a pattern
transferred onto the dielectric layer using a self aligned block
out mask which prevents etch of the dielectric layer in the
blockout regions
[0016] A further embodiment of the inventive method includes
depositing dielectric having interconnects on a substrate, a cap
layer, a sacrificial antireflective coating layer, a sacrificial
resist layer, applying a lithographic blockout mask having a
perforation pattern which does not overly the interconnects,
transferring the perforation pattern, extracting the dielectric
layer between the interconnects, depositing a second dielectric
layer, and pinching-off the second dielectric layer.
[0017] The invention also is a wafer containing an airgap
interconnect structure including a substrate with a dielectric cap
layer and an interconnect with spaces, and perforations in the cap
layer and spaces between the interconnect.
DETAILED DESCRIPTION OF THE INVENTION
[0018] The invention is an air gap-containing metal-insulator
interconnect structure for VLSI and ULSI devices and a method for
producing same A conventional lithographic mask is used which has
specific and carefully defined perforation openings as well as
blockout shapes to cover areas where gaps or perforations are not
desired.
[0019] A process flow for the method of this invention is shown in
FIG. 1. The wafer 100 includes a substrate and dielectric material
110. The desired metal-insulator dual damascene interconnect level
120 which needs to be gapped is built all the way up to the
deposition of the dielectric cap 130 using methods known in the
art. Following this, an optional hard mask layer which could act as
a resist poisoning layer if needed is deposited. An antireflective
coating and a resist layer may be deposited directly on the cap
layer or the hard mask layer if it is present. Subsequently, a
blockout mask 140 is used to pattern the resist layer. In the
blockout mask, the perforations 150 are in the shape of
perforations, rectangles, squares, other shapes and combinations
thereof and are at locations where the underlying metal shapes are
not present. FIG. 2 shows some non-limiting examples of perforation
shapes of a mask of the present invention. In order to minimize or
eliminate the exposure of copper during the subsequent etchback
steps, the size of the perforations is tailored in such a way that
the perforations have at least one dimension smaller than the
interline spacing.
[0020] FIG. 3 shows the considerations that go into choosing the
size of the perforations and these include the overlay tolerance
for the optical lithography of the blockout mask and variations in
perforation as well as interconnect wire critical dimension (CD).
The perforations can be placed at any suitable distance away from
each other and in any pattern that is desired but are preferably
placed in an hexagonal close packed (HCP) pattern to maximize the
open area while still ensuring that the spaces between perforations
are substantial enough to provide more than adequate mechanical
reinforcement of the cap into which these perforations will be
subsequently transferred. The blockout mask is applied via known
lithography methods.
[0021] After lithography, a blockout mask pattern with perforations
is transferred into the underlying cap material. The pattern may be
transferred all the way into the underlying dielectric as shown in
FIG. 1, or just left in the cap as shown in FIG. 4.
[0022] Subsequently, an ash step is used to remove the resist layer
and antireflective coating layers if present, and also to
optionally damage the dielectric pillars in between the transfer
patterns The demethylation of the dielectric pillars may be
necessary if the underlying dielectric is an organosilicate
material such as a dense or porous, spin-on or chemical vapor
deposition (CVD), SiCOH based material. The next step involves the
use of any known etchant, such as but not limited to wet etchants
such as dilute hydrofluoric acid (DHF) or ammonium hydroxide based
etchants, to either remove the dielectric pillars, or to completely
etch out the dielectric depending on whether the pattern is
transferred from the cap into the dielectric or not, to leave
behind a completely evacuated gap. The wet etchant can also be used
to remove any resputtered copper should the perforations still
accidentally intersect the copper. The etchant may also be vapor
based or CO.sub.2 based.
[0023] Prior to the deposition of the next level dielectric, an
optional flash deposition of the cap dielectric may be employed
should there be any exposed copper during the etchback.
[0024] The gap is sealed to leave behind a full airgap in between
the interconnect wires by the deposition of the subsequent level
dielectric.
[0025] In order to ensure that there is absolutely no exposed
copper during the etch and ash steps, sub-lithographic perforations
can also be employed as described below.
[0026] In a second embodiment of the invention as shown in FIG. 4
in 3a, 4a and 5a, after lithography using the blackout mask, a
chemically assisted shrink process that is well known in the art
can be employed to shrink perforation size in the resist used for
the lithography such that the minimum perforation size is far
smaller than the space in between the interconnect wires and is
small enough such that even when the overlay tolerance and the
interconnect chemical deposition are at the upper end of the
specifications for the technology, there is no danger that the
perforations will intersect the copper.
[0027] In a third embodiment of the invention as shown in FIG. 4 in
3b, 4b and 5b, a similar effect can be achieved in place of the
chemically assisted shrink process by depositing a very thin,
conformal layer such that the gap CD is reduced. The conformal
layer may be deposited by CVD, atomic layer deposition (ALD),
spin-on or any known method in the art. A conformal, thin, low
temperature oxide layer may be deposited such that the perforation
openings are reduced by the thickness of the oxide layer. The oxide
layer can be about 5 nm to about 25 nm thick such that if, for
example, the initial perforations are 75 nm in diameter, the
diameter is reduced to about 65 nm to about 25 nm respectively thus
ensuring that the perforation sizes are sub-lithographic. The
bottom of the conformal layer is removed at the beginning of the
etchback step and the rest of the layer can be removed during the
ash step and the wet etch step.
[0028] In a further embodiment, the perforation size can be reduced
either by silylation or the deposition of self assembled monolayers
(SAMS), such as by employing long chain polymeric siloxanes if
silylation is employed or by using long aliphatic or aromatic chain
SAMS.
[0029] A further embodiment of the invention includes imprint
lithography to produce sub-lithographic perforations placed in
between the copper wires. These perforations are produced in an
imprintable layer which is coated on top of the cap and is used in
place of the conventional resist and antireflective coating
layer.
[0030] While not being bound by theory, the present invention's use
of sub-spacing and/or sublithographic gap perforation openings
allows isotropic etch extraction of interlayer dielectric material
to gap widths larger than the mask perforation openings. This
improves gap size versus pinchoff size and allows for lower
capacitances. Further, by appropriately choosing the interlayer
dielectric and the etchant, and by employing interlayer dielectric
modification ("damage") mechanisms, it is possible to transfer the
perforation pattern only partially or minimally through the cap,
and then enlarge the perforations in the interlayer dielectric
underneath the cap by isotropic etching using a selective wet or SC
CO.sub.2 based etchant or vapor etchant.
[0031] The resulting inventive wafer contains airgaps which are
ordered in the macro level and the micro level, that is they are
ordered throughout the levels of dielectric material and the
airgaps contain no distinguishable changes in orientation of these
ordered regions.
[0032] The inventive method is streamlined having fewer masking and
etching steps per wiring level than the known methods, while still
ensuring that the airgaps can be made at thin wire levels which are
close to the transistor as well as "fat" wires which reside at the
upper levels of the interconnect scheme in a hierarchical
structure.
[0033] The present invention leads to suitable combinations of
wire-level scaling, image and overlay tolerances, mask resolution,
airgap perforation sizes, and borders on perforation placement. All
of the copper shapes may be protected by block out shapes as only
the spaces between the copper are exposed for the pattern transfer
for worst-case tolerance deviations. Thus, the present invention
limits exposed copper during etching and in some cases eliminates
it. Further, any limited exposed copper during etching is not
exposed along the entire length of the interconnect wire.
[0034] In order to facilitate easy pinch-off and minimize
dielectric redeposition within the gaps, specific gap etch patterns
are defined which have at least one dimension smaller than the
interline spacing. The present invention further lifts limits on
the maximum scale size for gaps below wiring trenches, where, for
example, a diblock scheme with limited perforation diameter might
start to fail at the largest desired wiring level scales. In
addition, the pinch-off heights of the present invention are
limited such that the trench bottoms from the subsequent level do
not intersect the pinch-off gaps.
[0035] The airgap structure of the present invention exhibits no
build-up of topography after the subsequent level dielectric
deposition.
[0036] The air gap structure of the present invention also includes
a compressive film at every level to interrupt the build up of the
gaps and tensile stress areas.
[0037] In addition, the present inventive method results in an
airgap depth not limited by limitations of etch due to high aspect
ratios. The inventive method does not limit the depth to which the
dielectric can be demethylated and thus rendered etchable.
[0038] The structure and method of the present invention is further
illustrated by the following non-limiting examples.
Example 1
[0039] The desired interlevel dielectric on a semiconductor
substrate was processed through a standard dual damascene scheme
all the way to the deposition of the post-chemically-mechanically
polished cap or thin hardmask. Following this, an antireflective
coating and a standard 193 or 248 nm resist layer was coated on to
the cap layer. A blockout mask, with perforations at least 50 nm or
larger, was employed to print openings into the resist layer.
Subsequently, the openings were transferred into the cap layer
only. DHF was used as an etchant to etch out and remove the
dielectric underneath the cap and leave behind a complete gap
beneath a perforated cap. Finally, the openings in the cap were
pinched-off during the deposition of the next level dielectric with
very short pinch-off heights that are on the order of the
perforation sizes and little or no topography at the top of the
dielectric.
Example 2
[0040] The desired interlevel dielectric on a semiconductor
substrate was processed through a standard dual damascene scheme
all the way to the deposition of the post-chemically-mechanically
polished cap or thin hardmask. An antireflective coating and a
standard 193 or 248 nm resist layer is coated on to the cap layer.
A blockout mask with perforations that are at least 50 nm or larger
is employed to print openings into the resist layer. The openings
are transferred into and through the cap layer and into the
underlying dielectric such that the openings are at least as deep
as, or, preferably at least 25% deeper than the height of the
interconnect wire. An oxidizing ash step is employed to remove the
resist and further demethylate the remaining dielectric pillars if
necessary. DHF is used as an etchant to remove the dielectric
pillars underneath the cap and leave behind a complete gap beneath
a perforated cap. Finally, the openings in the cap are pinched-off
during the deposition of the next level dielectric with very short
pinch-off heights that are on the order of the perforation sizes
and little or no topography at the top of the dielectric.
Example 3
[0041] The desired interlevel dielectric on a semiconductor
substrate was processed through a standard dual damascene scheme
all the way to the deposition of the post-chemically-mechanically
polished cap or thin hardmask. An antireflective coating and a
standard 193 or 248 nm resist layer is coated on to the cap layer.
A blockout mask with perforations that are at least 50 nm or larger
is employed to print openings into the resist layer. A conformal,
thin, low temperature oxide layer is deposited such that the
perforation openings are reduced by the thickness of the oxide
layer. The oxide layer can be about 5 nm to 25 nm thick such that
if the initial perforations are 75 nm in diameter, the diameter is
reduced to about 65 to 25 nm respectively thus ensuring that the
perforation sizes are sub-lithographic.
[0042] The openings are transferred into and through the cap layer
and into the underlying dielectric such that the openings are at
least as deep as, or, preferably at least 25% deeper than the
height of the interconnect wire. An oxidizing ash step is employed
to remove the resist layer as well as the oxide layer that reduces
the perforation openings, and also to further demethylate the
remaining dielectric pillars if necessary. DHF is used as an
etchant to remove the dielectric pillars underneath the cap and
leave behind a complete gap beneath a perforated cap. The openings
in the cap are then pinched-off during the deposition of the next
level dielectric with very short pinch-off heights that are on the
order of the perforation sizes and little or no topography at the
top of the dielectric.
[0043] The invention has been described in terms of embodiments
thereof, but is more broadly applicable as will be understood by
those skilled in the art. The scope of the invention is only
limited by the following claims.
* * * * *