| Patent | Date |
|---|
Cross-bar fin formation
Grant 11,456,181 - Cheng , et al. September 27, 2 | 2022-09-27 |
Formation of trench silicide source or drain contacts without gate damage
Grant 11,443,982 - Greene , et al. September 13, 2 | 2022-09-13 |
Techniques for forming replacement metal gate for VFET
Grant 11,437,489 - Xie , et al. September 6, 2 | 2022-09-06 |
Resistive Random-access Memory Cell And Manufacturing Method Thereof
App 20220254996 - Cheng; Kangguo ; et al. | 2022-08-11 |
Subtractive back-end-of-line vias
Grant 11,410,879 - Park , et al. August 9, 2 | 2022-08-09 |
Methods, Apparatus, And Manufacturing System For Self-aligned Patterning Of A Vertical Transistor
App 20220238386 - Park; Chanro ; et al. | 2022-07-28 |
Variable Sheet Forkfet Device
App 20220231020 - Frougier; Julien ; et al. | 2022-07-21 |
Interconnect structures of semiconductor devices having a via structure through an upper conductive line
Grant 11,380,581 - Labonte , et al. July 5, 2 | 2022-07-05 |
Nanosheet Transistors With Wrap Around Contact
App 20220208981 - Frougier; Julien ; et al. | 2022-06-30 |
Beol Metallization Formation
App 20220189826 - Park; Chanro ; et al. | 2022-06-16 |
Fin Stack Including Tensile-strained And Compressively Strained Fin Portions
App 20220157816 - Cheng; Kangguo ; et al. | 2022-05-19 |
Bi metal subtractive etch for trench and via formation
Grant 11,328,954 - Mignot , et al. May 10, 2 | 2022-05-10 |
Back end of line structures with metal lines with alternating patterning and metallization schemes
Grant 11,315,799 - Xie , et al. April 26, 2 | 2022-04-26 |
Self-aligned top via
Grant 11,315,872 - Park , et al. April 26, 2 | 2022-04-26 |
Methods, apparatus, and manufacturing system for self-aligned patterning of a vertical transistor
Grant 11,309,220 - Park , et al. April 19, 2 | 2022-04-19 |
Fully aligned interconnects with selective area deposition
Grant 11,289,375 - Park , et al. March 29, 2 | 2022-03-29 |
Stacked gate structures
Grant 11,282,838 - Zhang , et al. March 22, 2 | 2022-03-22 |
BEOL metallization formation
Grant 11,270,913 - Park , et al. March 8, 2 | 2022-03-08 |
Self-aligned source and drain contacts
Grant 11,264,481 - Park , et al. March 1, 2 | 2022-03-01 |
Contact structures
Grant 11,257,718 - Park , et al. February 22, 2 | 2022-02-22 |
Vertical Stacked Nanosheet Cmos Transistors With Different Work Function Metals
App 20220044973 - CHENG; Kangguo ; et al. | 2022-02-10 |
Dual damascene fully aligned via in interconnects
Grant 11,244,854 - Cheng , et al. February 8, 2 | 2022-02-08 |
Back end of line metallization
Grant 11,244,897 - Park , et al. February 8, 2 | 2022-02-08 |
Fully aligned via interconnects with partially removed etch stop layer
Grant 11,244,853 - Motoyama , et al. February 8, 2 | 2022-02-08 |
Scalable Device for FINFET Technology
App 20220037212 - Xie; Ruilong ; et al. | 2022-02-03 |
Removal Of Barrier And Liner Layers From A Bottom Of A Via
App 20220028738 - Park; Chanro ; et al. | 2022-01-27 |
Augmented Semiconductor Lasers With Spontaneous Emissions Blockage
App 20220013986 - FROUGIER; Julien ; et al. | 2022-01-13 |
Cross-bar Fin Formation
App 20220013366 - Cheng; Kangguo ; et al. | 2022-01-13 |
Stacked Gate Structures
App 20220013521 - Zhang; Chen ; et al. | 2022-01-13 |
Self-Aligned Source and Drain Contacts
App 20220005934 - Park; Chanro ; et al. | 2022-01-06 |
Transistor Having Stacked Source/drain Regions With Formation Assistance Regions And Multi-region Wrap-around Source/drain Contacts
App 20210408233 - Xie; Ruilong ; et al. | 2021-12-30 |
Using selectively formed cap layers to form self-aligned contacts to source/drain regions
Grant 11,211,462 - Park , et al. December 28, 2 | 2021-12-28 |
Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contacts
Grant 11,211,452 - Xie , et al. December 28, 2 | 2021-12-28 |
Top via interconnect with self-aligned barrier layer
Grant 11,205,591 - Cheng , et al. December 21, 2 | 2021-12-21 |
Pitch multiplication with high pattern fidelity
Grant 11,201,056 - Park , et al. December 14, 2 | 2021-12-14 |
Fully-aligned skip-vias
Grant 11,201,112 - Cheng , et al. December 14, 2 | 2021-12-14 |
Vertical Transistor With Self-aligned Gate
App 20210376140 - Li; Juntao ; et al. | 2021-12-02 |
Reduced Source/drain Coupling For Cfet
App 20210366782 - Xie; Ruilong ; et al. | 2021-11-25 |
Nanosheet transistor with inner spacers
Grant 11,183,561 - Cheng , et al. November 23, 2 | 2021-11-23 |
Vertical field effect transistor having improved uniformity
Grant 11,183,581 - Cheng , et al. November 23, 2 | 2021-11-23 |
Removal of barrier and liner layers from a bottom of a via
Grant 11,177,170 - Park , et al. November 16, 2 | 2021-11-16 |
Augmented semiconductor lasers with spontaneous emissions blockage
Grant 11,177,632 - Frougier , et al. November 16, 2 | 2021-11-16 |
Scalable device for FINFET technology
Grant 11,177,181 - Xie , et al. November 16, 2 | 2021-11-16 |
Top via structure with enlarged contact area with upper metallization level
Grant 11,177,163 - Motoyama , et al. November 16, 2 | 2021-11-16 |
Interconnects with hybrid metal conductors
Grant 11,177,214 - Cheng , et al. November 16, 2 | 2021-11-16 |
Planarization Controllability For Interconnect Structures
App 20210351064 - Xie; Ruilong ; et al. | 2021-11-11 |
Planarization controllability for interconnect structures
Grant 11,171,044 - Xie , et al. November 9, 2 | 2021-11-09 |
Structure And Method To Fabricate Resistive Memory With Vertical Pre-determined Filament
App 20210343938 - PARK; Chanro ; et al. | 2021-11-04 |
Interconnects with spacer structure for forming air-gaps
Grant 11,164,774 - Cheng , et al. November 2, 2 | 2021-11-02 |
Reduced source/drain coupling for CFET
Grant 11,164,793 - Xie , et al. November 2, 2 | 2021-11-02 |
Beol Metallization Formation
App 20210335666 - Park; Chanro ; et al. | 2021-10-28 |
Fully Aligned Via Interconnects With Partially Removed Etch Stop Layer
App 20210335659 - Motoyama; Koichi ; et al. | 2021-10-28 |
Vertical stacked nanosheet CMOS transistors with different work function metals
Grant 11,158,544 - Cheng , et al. October 26, 2 | 2021-10-26 |
Confined Gate Recessing For Vertical Transport Field Effect Transistors
App 20210327759 - Xie; Ruilong ; et al. | 2021-10-21 |
Subtractive Back-end-of-line Vias
App 20210313226 - Park; Chanro ; et al. | 2021-10-07 |
Back End Of Line Metallization
App 20210313264 - PARK; CHANRO ; et al. | 2021-10-07 |
Fully aligned top vias with replacement metal lines
Grant 11,139,202 - Park , et al. October 5, 2 | 2021-10-05 |
Vertical transistor with self-aligned gate
Grant 11,139,399 - Li , et al. October 5, 2 | 2021-10-05 |
Dual Damascene Fully Aligned Via Interconnects
App 20210305090 - Cheng; Kenneth Chun Kuen ; et al. | 2021-09-30 |
Ion-sensitive field-effect transistor with sawtooth well to enhance sensitivity
Grant 11,131,647 - Park , et al. September 28, 2 | 2021-09-28 |
Uniform work function metal recess for vertical transistor complementary metal oxide semiconductor technology
Grant 11,133,308 - Xie , et al. September 28, 2 | 2021-09-28 |
Pitch Multiplication With High Pattern Fidelity
App 20210296127 - PARK; CHANRO ; et al. | 2021-09-23 |
Reduced Source/drain Coupling For Cfet
App 20210296184 - Xie; Ruilong ; et al. | 2021-09-23 |
Fully Aligned Interconnects With Selective Area Deposition
App 20210296172 - Park; Chanro ; et al. | 2021-09-23 |
Top Via Structure With Enlarged Contact Area With Upper Metallization Level
App 20210296164 - Motoyama; Koichi ; et al. | 2021-09-23 |
Middle-of-line contacts with varying contact area providing reduced contact resistance
Grant 11,127,825 - Park , et al. September 21, 2 | 2021-09-21 |
Removal or reduction of chamfer for fully-aligned via
Grant 11,127,676 - Park , et al. September 21, 2 | 2021-09-21 |
Augmented Semiconductor Lasers With Spontaneous Emissions Blockage
App 20210288468 - FROUGIER; Julien ; et al. | 2021-09-16 |
Bi Metal Subtractive Etch For Trench And Via Formation
App 20210287940 - Mignot; Yann ; et al. | 2021-09-16 |
Structurally Stable Self-Aligned Subtractive Vias
App 20210280465 - Mukesh; Sagarika ; et al. | 2021-09-09 |
Using Selectively Formed Cap Layers To Form Self-aligned Contacts To Source/drain Regions
App 20210280690 - Park; Chanro ; et al. | 2021-09-09 |
Staircase surface-enhanced raman scattering substrate
Grant 11,092,551 - Cheng , et al. August 17, 2 | 2021-08-17 |
Structure and method to fabricate resistive memory with vertical pre-determined filament
Grant 11,094,883 - Park , et al. August 17, 2 | 2021-08-17 |
Gate-all-around field effect transistor having stacked U shaped channels configured to improve the effective width of the transistor
Grant 11,094,784 - Cheng , et al. August 17, 2 | 2021-08-17 |
Structurally stable self-aligned subtractive vias
Grant 11,094,590 - Mukesh , et al. August 17, 2 | 2021-08-17 |
Structure and method to fabricate fully aligned via with reduced contact resistance
Grant 11,094,580 - Park , et al. August 17, 2 | 2021-08-17 |
Removal Or Reduction Of Chamfer For Fully-aligned Via
App 20210225759 - Park; Chanro ; et al. | 2021-07-22 |
Fully-aligned Skip-vias
App 20210225760 - Cheng; Kenneth Chun Kuen ; et al. | 2021-07-22 |
Removal Of Barrier And Liner Layers From A Bottom Of A Via
App 20210225702 - Park; Chanro ; et al. | 2021-07-22 |
Interconnects With Spacer Structure For Forming Air-gaps
App 20210225691 - Cheng; Kenneth Chun Kuen ; et al. | 2021-07-22 |
FinFET-based integrated circuits with reduced parasitic capacitance
Grant 11,069,680 - Xie , et al. July 20, 2 | 2021-07-20 |
Semiconductor device comprising metal-insulator-metal (MIM) capacitor
Grant 11,069,677 - Park , et al. July 20, 2 | 2021-07-20 |
Scalable Device for FINFET Technology
App 20210217667 - Xie; Ruilong ; et al. | 2021-07-15 |
Interconnects With Hybrid Metal Conductors
App 20210217698 - Cheng; Kenneth Chun Kuen ; et al. | 2021-07-15 |
Top Via Interconnect With Self-aligned Barrier Layer
App 20210217662 - Cheng; Kenneth Chun Kuen ; et al. | 2021-07-15 |
Nanosheet Transistor With Inner Spacers
App 20210210598 - Cheng; Kangguo ; et al. | 2021-07-08 |
Integration of air spacer with self-aligned contact in transistor
Grant 11,043,411 - Park , et al. June 22, 2 | 2021-06-22 |
Gate cap last for self-aligned contact
Grant 11,031,295 - Park , et al. June 8, 2 | 2021-06-08 |
Transistor with airgap spacer
Grant 11,031,485 - Cheng , et al. June 8, 2 | 2021-06-08 |
Non-self aligned contact semiconductor devices
Grant 11,024,720 - Xie , et al. June 1, 2 | 2021-06-01 |
Embedded anti-fuses for small scale applications
Grant 11,024,577 - Park , et al. June 1, 2 | 2021-06-01 |
Semiconductor Device With Improved Contact Resistance And Via Connectivity
App 20210151323 - Park; Chanro ; et al. | 2021-05-20 |
Back End Of Line Structures With Metal Lines With Alternating Patterning And Metallization Schemes
App 20210151327 - Xie; Ruilong ; et al. | 2021-05-20 |
Transistor having airgap spacer around gate structure
Grant 11,011,638 - Xie , et al. May 18, 2 | 2021-05-18 |
Fin field-effect transistor with reduced parasitic capacitance and reduced variability
Grant 11,011,626 - Cheng , et al. May 18, 2 | 2021-05-18 |
Middle of the line contact formation
Grant 11,004,750 - Xie , et al. May 11, 2 | 2021-05-11 |
Structure And Method To Fabricate Resistive Memory With Vertical Pre-determined Filament
App 20210135108 - PARK; Chanro ; et al. | 2021-05-06 |
Vertical metal-air transistor
Grant 10,998,424 - Li , et al. May 4, 2 | 2021-05-04 |
Airgap Vertical Transistor Without Structural Collapse
App 20210118721 - Cheng; Kangguo ; et al. | 2021-04-22 |
Staircase Surface-enhanced Raman Scattering Substrate
App 20210116383 - Cheng; Kangguo ; et al. | 2021-04-22 |
Interconnect structure having fully aligned vias
Grant 10,978,343 - Park , et al. April 13, 2 | 2021-04-13 |
Floating gate prevention and capacitance reduction in semiconductor devices
Grant 10,978,574 - Xie , et al. April 13, 2 | 2021-04-13 |
Extreme ultraviolet patterning process with resist hardening
Grant 10,971,362 - Park , et al. April 6, 2 | 2021-04-06 |
Structure And Method To Fabricate Fully Aligned Via With Reduced Contact Resistance
App 20210098287 - Park; Chanro ; et al. | 2021-04-01 |
Fully Aligned Top Vias With Replacement Metal Lines
App 20210098284 - Park; Chanro ; et al. | 2021-04-01 |
Techniques for Forming Replacement Metal Gate for VFET
App 20210098602 - Xie; Ruilong ; et al. | 2021-04-01 |
Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions
Grant 10,957,799 - Xie , et al. March 23, 2 | 2021-03-23 |
Middle Of The Line Contact Formation
App 20210082770 - Xie; Ruilong ; et al. | 2021-03-18 |
Back End Of Line Structures With Metal Lines With Alternating Patterning And Metallization Schemes
App 20210082714 - Xie; Ruilong ; et al. | 2021-03-18 |
Vertical Metal-air Transistor
App 20210083075 - Li; Juntao ; et al. | 2021-03-18 |
Back end of line structures with metal lines with alternating patterning and metallization schemes
Grant 10,950,459 - Xie , et al. March 16, 2 | 2021-03-16 |
Transistor Having Airgap Spacer
App 20210066489 - Xie; Ruilong ; et al. | 2021-03-04 |
Ion-sensitive field-effect transistor formed with alternating dielectric stack to enhance sensitivity
Grant 10,935,516 - Cheng , et al. March 2, 2 | 2021-03-02 |
Vertical Transistor With Self-aligned Gate
App 20210057565 - Li; Juntao ; et al. | 2021-02-25 |
Method and structure to improve overlay margin of non-self-aligned contact in metallization layer
Grant 10,930,568 - Xie , et al. February 23, 2 | 2021-02-23 |
Semiconductor device with improved contact resistance and via connectivity
Grant 10,930,510 - Park , et al. February 23, 2 | 2021-02-23 |
Interconnect Structure Having Fully Aligned Vias
App 20210050260 - Park; Chanro ; et al. | 2021-02-18 |
Air-gap spacers for field-effect transistors
Grant 10,923,389 - Park , et al. February 16, 2 | 2021-02-16 |
Wrap-around contact for vertical field effect transistors
Grant 10,923,590 - Cheng , et al. February 16, 2 | 2021-02-16 |
Gate-all-around Field Effect Transistors With Robust Inner Spacers And Methods
App 20210043727 - Frougier; Julien ; et al. | 2021-02-11 |
Uniform bottom spacer for VFET devices
Grant 10,916,650 - Bentley , et al. February 9, 2 | 2021-02-09 |
Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions
Grant 10,903,369 - Xie , et al. January 26, 2 | 2021-01-26 |
Gate-all-around field effect transistors with robust inner spacers and methods
Grant 10,903,317 - Frougier , et al. January 26, 2 | 2021-01-26 |
Surface enhanced Raman scattering substrate
Grant 10,900,906 - Cheng , et al. January 26, 2 | 2021-01-26 |
Airgap vertical transistor without structural collapse
Grant 10,896,845 - Cheng , et al. January 19, 2 | 2021-01-19 |
Floating Gate Prevention And Capacitance Reduction In Semiconductor Devices
App 20210013322 - Xie; Ruilong ; et al. | 2021-01-14 |
Method of forming air-gap spacers and gate contact over active region and the resulting device
Grant 10,886,378 - Xie , et al. January 5, 2 | 2021-01-05 |
Insulating gate separation structure for transistor devices
Grant 10,879,073 - Park , et al. December 29, 2 | 2020-12-29 |
Methods, Apparatus And System For Forming On-chip Metal-insulator-meal (mim) Capacitor
App 20200402976 - Park; Chanro ; et al. | 2020-12-24 |
Airgap Vertical Transistor Without Structural Collapse
App 20200395238 - Cheng; Kangguo ; et al. | 2020-12-17 |
Transistor With Airgap Spacer
App 20200388694 - Cheng; Kangguo ; et al. | 2020-12-10 |
Surface Enhanced Raman Scattering Substrate
App 20200386685 - Cheng; Kangguo ; et al. | 2020-12-10 |
Gate Cap Last For Self-aligned Contact
App 20200381306 - Park; Chanro ; et al. | 2020-12-03 |
Semiconductor Device With Improved Contact Resistance And Via Connectivity
App 20200373165 - Park; Chanro ; et al. | 2020-11-26 |
One-time Programmable Device Compatible With Vertical Transistor Processing
App 20200365607 - Cheng; Kangguo ; et al. | 2020-11-19 |
One-time programmable device compatible with vertical transistor processing
Grant 10,840,148 - Cheng , et al. November 17, 2 | 2020-11-17 |
Fin Field-effect Transistor With Reduced Parasitic Capacitance And Reduced Variability
App 20200357896 - Cheng; Kangguo ; et al. | 2020-11-12 |
Gate-all-around Field Effect Transistors With Inner Spacers And Methods
App 20200357911 - Frougier; Julien ; et al. | 2020-11-12 |
Replacement contact formation for gate contact over active region with selective metal growth
Grant 10,832,964 - Xie , et al. November 10, 2 | 2020-11-10 |
Fully aligned via formation without metal recessing
Grant 10,832,947 - Park , et al. November 10, 2 | 2020-11-10 |
Asymmetric air spacer gate-controlled device with reduced parasitic capacitance
Grant 10,833,165 - Cheng , et al. November 10, 2 | 2020-11-10 |
Sacrificial gate spacer regions for gate contacts formed over the active region of a transistor
Grant 10,832,961 - Fan , et al. November 10, 2 | 2020-11-10 |
Interconnect structure having reduced resistance variation and method of forming same
Grant 10,832,944 - LiCausi , et al. November 10, 2 | 2020-11-10 |
Uniform Work Function Metal Recess For Vertical Transistor Complementary Metal Oxide Semiconductor Technology
App 20200350313 - XIE; RUILONG ; et al. | 2020-11-05 |
Sacrificial Gate Spacer Regions For Gate Contacts Formed Over The Active Region Of A Transistor
App 20200335401 - Fan; Su Chen ; et al. | 2020-10-22 |
Ion-sensitive Field-effect Transistor With Micro-pillar Well To Enhance Sensitivity
App 20200328088 - Li; Juntao ; et al. | 2020-10-15 |
Gate-all-around Field Effect Transistor Having Stacked U Shaped Channels Configured To Improve The Effective Width Of The Transistor
App 20200321434 - Cheng; Kangguo ; et al. | 2020-10-08 |
FinFET-BASED INTEGRATED CIRCUITS WITH REDUCED PARASITIC CAPACITANCE
App 20200312843 - Xie; Ruilong ; et al. | 2020-10-01 |
finFET with improved nitride to fin spacing
Grant 10,790,395 - Ok , et al. September 29, 2 | 2020-09-29 |
Contact structures
Grant 10,790,376 - Xie , et al. September 29, 2 | 2020-09-29 |
Ion-sensitive field-effect transistor with micro-pillar well to enhance sensitivity
Grant 10,788,446 - Li , et al. September 29, 2 | 2020-09-29 |
Middle-of-line Contacts With Varying Contact Area Providing Reduced Contact Resistance
App 20200303264 - Park; Chanro ; et al. | 2020-09-24 |
Wrap-Around Contact for Vertical Field Effect Transistors
App 20200303543 - Cheng; Kangguo ; et al. | 2020-09-24 |
Ion-sensitive Field-effect Transistor With Sawtooth Well To Enhance Sensitivity
App 20200292491 - Park; Chanro ; et al. | 2020-09-17 |
Vertical Stacked Nanosheet Cmos Transistors With Different Work Function Metals
App 20200294866 - CHENG; Kangguo ; et al. | 2020-09-17 |
Ion-sensitive Field-effect Transistor Formed With Alternating Dielectric Stack To Enhance Sensitivity
App 20200292490 - Cheng; Kangguo ; et al. | 2020-09-17 |
Non-self Aligned Contact Semiconductor Devices
App 20200295151 - Xie; Ruilong ; et al. | 2020-09-17 |
Interlayer dielectric replacement techniques with protection for source/drain contacts
Grant 10,770,562 - Cheng , et al. Sep | 2020-09-08 |
Unique gate cap and gate cap spacer structures for devices on integrated circuit products
Grant 10,770,566 - Frougier , et al. Sep | 2020-09-08 |
On-chip metal-insulator-metal (MIM) capacitor and methods and systems for forming same
Grant 10,770,454 - Park , et al. Sep | 2020-09-08 |
Self-aligned buried contact for vertical field-effect transistor and method of production thereof
Grant 10,770,585 - Xie , et al. Sep | 2020-09-08 |
Fully Aligned Via Formation Without Metal Recessing
App 20200279769 - Park; Chanro ; et al. | 2020-09-03 |
Interlayer Dielectric Replacement Techniques With Protection For Source/drain Contacts
App 20200279933 - Cheng; Kangguo ; et al. | 2020-09-03 |
Transistor Channel Having Vertically Stacked Nanosheets Coupled By Fin-shaped Bridge Regions
App 20200273979 - XIE; RUILONG ; et al. | 2020-08-27 |
Transistor Channel Having Vertically Stacked Nanosheets Coupled By Fin-shaped Bridge Regions
App 20200274000 - XIE; RUILONG ; et al. | 2020-08-27 |
Extreme Ultraviolet Patterning Process With Resist Hardening
App 20200273704 - PARK; Chanro ; et al. | 2020-08-27 |
Ion-sensitive Field Effect Transistor (isfet) With Enhanced Sensitivity
App 20200271620 - Cheng; Kangguo ; et al. | 2020-08-27 |
Vertical Field Effect Transistor Having Improved Uniformity
App 20200266288 - CHENG; Kangguo ; et al. | 2020-08-20 |
Ion-sensitive field effect transistor (ISFET) with enhanced sensitivity
Grant 10,746,691 - Cheng , et al. A | 2020-08-18 |
FinFET having insulating layers between gate and source/drain contacts
Grant 10,741,451 - Zang , et al. A | 2020-08-11 |
Integrated gate contact and cross-coupling contact formation
Grant 10,727,136 - Zang , et al. | 2020-07-28 |
Method Of Forming Air-gap Spacers And Gate Contact Over Active Region And The Resulting Device
App 20200212192 - XIE; Ruilong ; et al. | 2020-07-02 |
Late gate cut using selective dielectric deposition
Grant 10,699,957 - Zang , et al. | 2020-06-30 |
Vertical-transport field-effect transistors having gate contacts located over the active region
Grant 10,699,942 - Xie , et al. | 2020-06-30 |
Uniform Bottom Spacer For Vfet Devices
App 20200194587 - Bentley; Steven ; et al. | 2020-06-18 |
Airgap spacers formed in conjunction with a late gate cut
Grant 10,679,894 - Frougier , et al. | 2020-06-09 |
Method of forming nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness
Grant 10,679,906 - Cheng , et al. | 2020-06-09 |
Contact Structures
App 20200176325 - PARK; Chanro ; et al. | 2020-06-04 |
Late Gate Cut Using Selective Dielectric Deposition
App 20200168509 - Zang; Hui ; et al. | 2020-05-28 |
Non-self aligned gate contacts formed over the active region of a transistor
Grant 10,665,692 - Xie , et al. | 2020-05-26 |
Integration Of Air Spacer With Self-aligned Contact In Transistor
App 20200161169 - Park; Chanro ; et al. | 2020-05-21 |
Method for forming replacement metal gate and related structures
Grant 10,658,243 - Xie , et al. | 2020-05-19 |
Fin cut last method for forming a vertical FinFET device
Grant 10,658,506 - Park , et al. | 2020-05-19 |
Airgap Spacers Formed In Conjunction With A Late Gate Cut
App 20200152504 - Frougier; Julien ; et al. | 2020-05-14 |
Interconnect Structures Of Semiconductor Devices
App 20200152512 - Labonte; Andre P. ; et al. | 2020-05-14 |
Formation Of Trench Silicide Source Or Drain Contacts Without Gate Damage
App 20200152509 - Greene; Andrew ; et al. | 2020-05-14 |
Integrated Gate Contact And Cross-coupling Contact Formation
App 20200152518 - Zang; Hui ; et al. | 2020-05-14 |
Interconnect Structure Having Reduced Resistance Variation And Method Of Forming Same
App 20200144106 - LiCausi; Nicholas V. ; et al. | 2020-05-07 |
Non-self Aligned Gate Contacts Formed Over The Active Region Of A Transistor
App 20200135885 - Xie; Ruilong ; et al. | 2020-04-30 |
Finfet With Improved Nitride To Fin Spacing
App 20200135927 - OK; Injo ; et al. | 2020-04-30 |
Insulating Gate Separation Structure For Transistor Devices
App 20200135473 - Park; Chanro ; et al. | 2020-04-30 |
Vertical transistor with reduced parasitic capacitance
Grant 10,622,260 - Xie , et al. | 2020-04-14 |
Uniform bottom spacer for VFET devices
Grant 10,622,475 - Bentley , et al. | 2020-04-14 |
Finfet Having Insulating Layers Between Gate And Source/drain Contacts
App 20200111713 - Zang; Hui ; et al. | 2020-04-09 |
Self-aligned Buried Contact For Vertical Field-effect Transistor And Method Of Production Thereof
App 20200098913 - XIE; Ruilong ; et al. | 2020-03-26 |
Contact structures
Grant 10,593,599 - Park , et al. | 2020-03-17 |
Integration Of Air Spacer With Self-aligned Contact In Transistor
App 20200083101 - Park; Chanro ; et al. | 2020-03-12 |
Integration of air spacer with self-aligned contact in transistor
Grant 10,580,692 - Park , et al. | 2020-03-03 |
Contact Structures
App 20200058757 - XIE; Ruilong ; et al. | 2020-02-20 |
Work function metal patterning for N-P spaces between active nanostructures using unitary isolation pillar
Grant 10,566,248 - Chanemougame , et al. Feb | 2020-02-18 |
Gate cut method after source/drain metallization
Grant 10,566,201 - Park , et al. Feb | 2020-02-18 |
Unique Gate Cap And Gate Cap Spacer Structures For Devices On Integrated Circuit Products
App 20200052088 - Frougier; Julien ; et al. | 2020-02-13 |
Work Function Metal Patterning For N-p Spaces Between Active Nanostructures Using Unitary Isolation Pillar
App 20200035567 - Chanemougame; Daniel ; et al. | 2020-01-30 |
Fin Cut Last Method For Forming A Vertical Finfet Device
App 20200027981 - PARK; Chanro ; et al. | 2020-01-23 |
Uniform Bottom Spacer For Vfet Devices
App 20200027983 - Bentley; Steven ; et al. | 2020-01-23 |
Transistor Structures With Reduced Parasitic Capacitance And Improved Junction Sharpness
App 20200027959 - Cheng; Kangguo ; et al. | 2020-01-23 |
Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices
Grant 10,529,826 - Frougier , et al. J | 2020-01-07 |
Vertical field effect transistor having improved uniformity
Grant 10,522,658 - Cheng , et al. Dec | 2019-12-31 |
Semiconductor Device With Improved Gate-source/drain Metallization Isolation
App 20190378722 - Economikos; Laertis ; et al. | 2019-12-12 |
Method For Forming Replacement Metal Gate And Related Structures
App 20190378761 - Xie; Ruilong ; et al. | 2019-12-12 |
Vertical Transistor With Reduced Parasitic Capacitance
App 20190378765 - Xie; Ruilong ; et al. | 2019-12-12 |
Gate cut in replacement metal gate process
Grant 10,504,798 - Xie , et al. Dec | 2019-12-10 |
Vertical field effect transistor with self-aligned contacts
Grant 10,497,798 - Xie , et al. De | 2019-12-03 |
Contacting source and drain of a transistor device
Grant 10,468,300 - Xie , et al. No | 2019-11-05 |
Asymmetric Air Spacer Gate-controlled Device With Reduced Parasitic Capacitance
App 20190334009 - Cheng; Kangguo ; et al. | 2019-10-31 |
Control of length in gate region during processing of VFET structures
Grant 10,461,196 - Park , et al. Oc | 2019-10-29 |
Vertical-transport Field-effect Transistors Having Gate Contacts Located Over The Active Region
App 20190326165 - Xie; Ruilong ; et al. | 2019-10-24 |
Hard mask layer to reduce loss of isolation material during dummy gate removal
Grant 10,446,399 - Xie , et al. Oc | 2019-10-15 |
Transistor-based semiconductor device with air-gap spacers and gate contact over active area
Grant 10,446,653 - Xie , et al. Oc | 2019-10-15 |
On-chip Metal-insulator-metal (mim) Capacitor And Methods And Systems For Forming Same
App 20190312028 - Park; Chanro ; et al. | 2019-10-10 |
Contacts Formed With Self-aligned Cuts
App 20190295898 - Xie; Ruilong ; et al. | 2019-09-26 |
Air gap spacer formation for nano-scale semiconductor devices
Grant 10,418,277 - Cheng , et al. Sept | 2019-09-17 |
Contact Structures
App 20190279910 - PARK; Chanro ; et al. | 2019-09-12 |
Replacement metal gate patterning for nanosheet devices
Grant 10,410,933 - Xie , et al. Sept | 2019-09-10 |
Air Gap Spacer Formation For Nano-scale Semiconductor Devices
App 20190267279 - Cheng; Kangguo ; et al. | 2019-08-29 |
Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same
Grant 10,388,652 - Shi , et al. A | 2019-08-20 |
Gate and source/drain contact structures positioned above an active region of a transistor device
Grant 10,388,770 - Xie , et al. A | 2019-08-20 |
Gate Cut In Replacement Metal Gate Process
App 20190252268 - Xie; Ruilong ; et al. | 2019-08-15 |
Vertical Field Effect Transistor With Self-aligned Contacts
App 20190252267 - Xie; Ruilong ; et al. | 2019-08-15 |
Contacts formed with self-aligned cuts
Grant 10,373,875 - Xie , et al. | 2019-08-06 |
Gate cut in replacement metal gate process
Grant 10,373,873 - Park , et al. | 2019-08-06 |
Self-aligned gate cut isolation
Grant 10,366,930 - Xie , et al. July 30, 2 | 2019-07-30 |
Air-gap Spacers For Field-effect Transistors
App 20190198381 - Park; Chanro ; et al. | 2019-06-27 |
Air-gap spacers for field-effect transistors
Grant 10,319,627 - Park , et al. | 2019-06-11 |
Method of forming vertical FinFET device having self-aligned contacts
Grant 10,312,154 - Xie , et al. | 2019-06-04 |
Composite isolation structures for a fin-type field effect transistor
Grant 10,297,597 - Sung , et al. | 2019-05-21 |
Forming Contacts For Vfets
App 20190148494 - Xie; Ruilong ; et al. | 2019-05-16 |
Integrated Circuit Structure Including Single Diffusion Break Abutting End Isolation Region, And Methods Of Forming Same
App 20190148373 - Shi; Yongiun ; et al. | 2019-05-16 |
Methods of forming conductive contact structures to semiconductor devices and the resulting structures
Grant 10,290,544 - Xie , et al. | 2019-05-14 |
Self-aligned Gate Isolation
App 20190139830 - XIE; Ruilong ; et al. | 2019-05-09 |
Hybrid spacer integration for field-effect transistors
Grant 10,283,617 - Xie , et al. | 2019-05-07 |
Middle of the line (MOL) contacts with two-dimensional self-alignment
Grant 10,283,408 - Xie , et al. | 2019-05-07 |
Hybrid Spacer Integration For Field-effect Transistors
App 20190131430 - Xie; Ruilong ; et al. | 2019-05-02 |
Forming contacts for VFETs
Grant 10,269,812 - Xie , et al. | 2019-04-23 |
Methods Of Forming Conductive Contact Structures To Semiconductor Devices And The Resulting Structures
App 20190109045 - Xie; Ruilong ; et al. | 2019-04-11 |
Methods of forming a protection layer on a semiconductor device and the resulting device
Grant 10,249,726 - Xie , et al. | 2019-04-02 |
Gate Stack Processes And Structures
App 20190096679 - Kannan; Balaji ; et al. | 2019-03-28 |
Gate contact structure positioned above an active region of a transistor device
Grant 10,243,053 - Xie , et al. | 2019-03-26 |
Self-aligned Contacts For Vertical Field Effect Transistor Cell Height Scaling
App 20190088764 - XIE; Ruilong ; et al. | 2019-03-21 |
Methods, apparatus and system for STI recess control for highly scaled finFET devices
Grant 10,236,291 - Sung , et al. | 2019-03-19 |
Methods of forming transistor devices with different threshold voltages and the resulting devices
Grant 10,229,855 - Kim , et al. | 2019-03-12 |
Gate Cut Method For Replacement Metal Gate
App 20190067115 - PARK; Chanro ; et al. | 2019-02-28 |
Field effect transistor (FET) with a gate having a recessed work function metal layer and method of forming the FET
Grant 10,217,839 - Park , et al. Feb | 2019-02-26 |
Vertical field effect transistor formation with critical dimension control
Grant 10,217,846 - Xie , et al. Feb | 2019-02-26 |
Metal-insulator-metal capacitors with dielectric inner spacers
Grant 10,211,147 - Zhang , et al. Feb | 2019-02-19 |
Transistor with robust air spacer
Grant 10,211,092 - Cheng , et al. Feb | 2019-02-19 |
Methods of forming an air gap adjacent a gate of a transistor and a gate contact above the active region of the transistor
Grant 10,211,100 - Xie , et al. Feb | 2019-02-19 |
Methods, Apparatus, And Manufacturing System For Self-aligned Patterning Of A Vertical Transistor
App 20190051563 - Park; Chanro ; et al. | 2019-02-14 |
Methods of forming a semiconductor device with a gate contact positioned above the active region
Grant 10,204,994 - Xie , et al. Feb | 2019-02-12 |
Control Of Length In Gate Region During Processing Of Vfet Structures
App 20190035938 - Park; Chanro ; et al. | 2019-01-31 |
Metal-insulator-metal Capacitors With Dielectric Inner Spacers
App 20190013269 - Zhang; Xunyuan ; et al. | 2019-01-10 |
Contacting Source And Drain Of A Transistor Device
App 20190013241 - Xie; Ruilong ; et al. | 2019-01-10 |
Methods of forming a gate contact for a transistor above the active region and an air gap adjacent the gate of the transistor
Grant 10,177,241 - Park , et al. J | 2019-01-08 |
Fin-type field effect transistors (FINFETS) with replacement metal gates and methods
Grant 10,177,041 - Xie , et al. J | 2019-01-08 |
Replacement metal gate and fabrication process with reduced lithography steps
Grant 10,176,996 - Sung , et al. J | 2019-01-08 |
Forming of marking trenches in structure for multiple patterning lithography
Grant 10,157,796 - Economikos , et al. Dec | 2018-12-18 |
Replacement Metal Gate Patterning For Nanosheet Devices
App 20180342427 - Xie; Ruilong ; et al. | 2018-11-29 |
Methods, apparatus and system for forming source/drain contacts using early trench silicide cut
Grant 10,121,702 - Park , et al. November 6, 2 | 2018-11-06 |
Air gap spacer formation for nano-scale semiconductor devices
Grant 10,115,629 - Cheng , et al. October 30, 2 | 2018-10-30 |
Nanosheet field-effect transistor with full dielectric isolation
Grant 10,103,238 - Zang , et al. October 16, 2 | 2018-10-16 |
Methods Of Forming A Semiconductor Device With A Gate Contact Positioned Above The Active Region
App 20180286956 - Xie; Ruilong ; et al. | 2018-10-04 |
Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates
Grant 10,090,402 - Park , et al. October 2, 2 | 2018-10-02 |
Field Effect Transistor (fet) With A Gate Having A Recessed Work Function Metal Layer And Method Of Forming The Fet
App 20180277652 - Park; Chanro ; et al. | 2018-09-27 |
Gate Cuts After Metal Gate Formation
App 20180277645 - Xie; Ruilong ; et al. | 2018-09-27 |
Methods Of Forming An Air Gap Adjacent A Gate Of A Transistor And A Gate Contact Above The Active Region Of The Transistor
App 20180277430 - Xie; Ruilong ; et al. | 2018-09-27 |
Gate cuts after metal gate formation
Grant 10,084,053 - Xie , et al. September 25, 2 | 2018-09-25 |
Air Gap Spacer Formation For Nano-scale Semiconductor Devices
App 20180261494 - Cheng; Kangguo ; et al. | 2018-09-13 |
Fin-type Field Effect Transistors (finfets) With Replacement Metal Gates And Methods
App 20180261514 - Xie; Ruilong ; et al. | 2018-09-13 |
Semiconductor device configured for avoiding electrical shorting
Grant 10,050,118 - Xie , et al. August 14, 2 | 2018-08-14 |
Method of forming a semiconductor device with a gate contact positioned above the active region
Grant 10,038,065 - Xie , et al. July 31, 2 | 2018-07-31 |
Dual liner CMOS integration methods for FinFET devices
Grant 10,026,655 - Sung , et al. July 17, 2 | 2018-07-17 |
Methods, apparatus and system for local isolation formation for finFET devices
Grant 10,014,209 - Sung , et al. July 3, 2 | 2018-07-03 |
Methods of forming IC products comprising a nano-sheet device and a transistor device having first and second replacement gate structures
Grant 10,014,389 - Xie , et al. July 3, 2 | 2018-07-03 |
Middle Of The Line (mol) Contacts With Two-dimensional Self-alignment
App 20180182668 - XIE; RUILONG ; et al. | 2018-06-28 |
Methods of forming an air-gap spacer on a semiconductor device and the resulting device
Grant 10,008,577 - Xie , et al. June 26, 2 | 2018-06-26 |
Self-aligned contact protection using reinforced gate cap and spacer portions
Grant 10,002,932 - Xie , et al. June 19, 2 | 2018-06-19 |
Air-gap Spacers For Field-effect Transistors
App 20180166319 - Park; Chanro ; et al. | 2018-06-14 |
Dual mandrels to enable variable fin pitch
Grant 9,991,131 - Sung , et al. June 5, 2 | 2018-06-05 |
Inverted damascene interconnect structures
Grant 9,984,919 - Zhang , et al. May 29, 2 | 2018-05-29 |
Transistor-based Semiconductor Device With Air-gap Spacers And Gate Contact Over Active Area
App 20180138279 - XIE; Ruilong ; et al. | 2018-05-17 |
Self-aligned Contact Protection Using Reinforced Gate Cap And Spacer Portions
App 20180130889 - XIE; Ruilong ; et al. | 2018-05-10 |
Methods Of Forming Gate Electrodes On A Vertical Transistor Device
App 20180130895 - Park; Chanro ; et al. | 2018-05-10 |
Methods of forming gate electrodes on a vertical transistor device
Grant 9,966,456 - Park , et al. May 8, 2 | 2018-05-08 |
Methods Of Forming Transistor Devices With Different Threshold Voltages And The Resulting Devices
App 20180122702 - Kim; Hoon ; et al. | 2018-05-03 |
Hard Mask Layer To Reduce Loss Of Isolation Material During Dummy Gate Removal
App 20180122644 - XIE; Ruilong ; et al. | 2018-05-03 |
Methods Of Forming A Gate Contact For A Transistor Above The Active Region And An Air Gap Adjacent The Gate Of The Transistor
App 20180122919 - Park; Chanro ; et al. | 2018-05-03 |
Preventing oxidation defects in strain-relaxed fins by reducing local gap fill voids
Grant 9,953,879 - Sung , et al. April 24, 2 | 2018-04-24 |
Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure
Grant 9,947,804 - Frougier , et al. April 17, 2 | 2018-04-17 |
Methods of forming a gate contact for a transistor above an active region and the resulting device
Grant 9,947,589 - Park , et al. April 17, 2 | 2018-04-17 |
Preventing Oxidation Defects In Strain-relaxed Fins By Reducing Local Gap Fill Voids
App 20180096895 - SUNG; Min Gyu ; et al. | 2018-04-05 |
Composite Isolation Structures For A Fin-type Field Effect Transistor
App 20180096998 - Sung; Min Gyu ; et al. | 2018-04-05 |
Middle of the line (MOL) contacts with two-dimensional self-alignment
Grant 9,929,048 - Xie , et al. March 27, 2 | 2018-03-27 |
Fin cut with alternating two color fin hardmask
Grant 9,911,619 - Xie , et al. March 6, 2 | 2018-03-06 |
Methods, Apparatus And System For Sti Recess Control For Highly Scaled Finfet Devices
App 20180061832 - Sung; Min Gyu ; et al. | 2018-03-01 |
Methods of forming a gate contact for a semiconductor device above the active region
Grant 9,899,321 - Park , et al. February 20, 2 | 2018-02-20 |
Air Gap Spacer Formation For Nano-scale Semiconductor Devices
App 20180047615 - Cheng; Kangguo ; et al. | 2018-02-15 |
Method To Tune Contact Cd And Reduce Mask Count By Tilted Ion Beam
App 20180047564 - Park; Chanro ; et al. | 2018-02-15 |
Air Gap Spacer Formation For Nano-scale Semiconductor Devices
App 20180047617 - Cheng; Kangguo ; et al. | 2018-02-15 |
Air gap spacer formation for nano-scale semiconductor devices
Grant 9,892,961 - Cheng , et al. February 13, 2 | 2018-02-13 |
Methods Of Forming Ic Products Comprising A Nano-sheet Device And A Transistor Device
App 20180033871 - Xie; Ruilong ; et al. | 2018-02-01 |
Methods Of Forming An Air-gap Spacer On A Semiconductor Device And The Resulting Device
App 20180033863 - Xie; Ruilong ; et al. | 2018-02-01 |
Methods for forming transistor devices with different threshold voltages and the resulting devices
Grant 9,875,940 - Kim , et al. January 23, 2 | 2018-01-23 |
Method And Structure Of Forming Self-aligned Rmg Gate For Vfet
App 20180019337 - XIE; Ruilong ; et al. | 2018-01-18 |
Block patterning method enabling merged space in SRAM with heterogeneous mandrel
Grant 9,859,125 - Sung , et al. January 2, 2 | 2018-01-02 |
Methods of forming fin cut regions by oxidizing fin portions
Grant 9,847,418 - Lim , et al. December 19, 2 | 2017-12-19 |
Self-aligned wrap-around contacts for nanosheet devices
Grant 9,847,390 - Xie , et al. December 19, 2 | 2017-12-19 |
Methods, apparatus and system for STI recess control for highly scaled finFET devices
Grant 9,837,404 - Sung , et al. December 5, 2 | 2017-12-05 |
Methods for forming fin structures
Grant 9,831,132 - Park , et al. November 28, 2 | 2017-11-28 |
Methods of forming self-aligned contact structures by work function material layer recessing and the resulting devices
Grant 9,824,920 - Park , et al. November 21, 2 | 2017-11-21 |
Gate cut method for replacement metal gate integration
Grant 9,818,836 - Sung , et al. November 14, 2 | 2017-11-14 |
Dual Liner Cmos Integration Methods For Finfet Devices
App 20170316985 - Sung; Min Gyu ; et al. | 2017-11-02 |
Methods For Forming Fin Structures
App 20170309522 - PARK; Chanro ; et al. | 2017-10-26 |
Method Of Forming A Semiconductor Device With A Gate Contact Positioned Above The Active Region
App 20170309714 - Xie; Ruilong ; et al. | 2017-10-26 |
Method of forming inner spacers on a nano-sheet/wire device
Grant 9,799,748 - Xie , et al. October 24, 2 | 2017-10-24 |
Methods, Apparatus And System For Local Isolation Formation For Finfet Devices
App 20170294338 - Sung; Min Gyu ; et al. | 2017-10-12 |
Methods Of Forming Self-aligned Contact Structures By Work Function Material Layer Recessing And The Resulting Devices
App 20170287780 - Park; Chanro ; et al. | 2017-10-05 |
Method and structure of forming self-aligned RMG gate for VFET
Grant 9,780,208 - Xie , et al. October 3, 2 | 2017-10-03 |
Method of controlling VFET channel length
Grant 9,780,197 - Xie , et al. October 3, 2 | 2017-10-03 |
Methods, Apparatus And System For Sti Recess Control For Highly Scaled Finfet Devices
App 20170278844 - Sung; Min Gyu ; et al. | 2017-09-28 |
Block Patterning Method Enabling Merged Space In Sram With Heterogeneous Mandrel
App 20170271163 - SUNG; Min Gyu ; et al. | 2017-09-21 |
Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devices
Grant 9,761,495 - Xie , et al. September 12, 2 | 2017-09-12 |
Methods To Form Multi Threshold-voltage Dual Channel Without Channel Doping
App 20170256455 - KIM; Hoon ; et al. | 2017-09-07 |
Methods Of Performing Concurrent Fin And Gate Cut Etch Processes For Finfet Semiconductor Devices And The Resulting Devices
App 20170243790 - Xie; Ruilong ; et al. | 2017-08-24 |
Dual liner CMOS integration methods for FinFET devices
Grant 9,741,623 - Sung , et al. August 22, 2 | 2017-08-22 |
Methods to form multi threshold-voltage dual channel without channel doping
Grant 9,735,061 - Kim , et al. August 15, 2 | 2017-08-15 |
Methods for forming fin structures
Grant 9,735,063 - Park , et al. August 15, 2 | 2017-08-15 |
Semiconductor device with a gate contact positioned above the active region
Grant 9,735,242 - Xie , et al. August 15, 2 | 2017-08-15 |
Hybrid fin cut etching processes for products comprising tapered and non-tapered FinFET semiconductor devices
Grant 9,735,060 - Sung , et al. August 15, 2 | 2017-08-15 |
Methods To Form Multi Threshold-voltage Dual Channel Without Channel Doping
App 20170221764 - KIM; Hoon ; et al. | 2017-08-03 |
Methods, apparatus and system for local isolation formation for finFET devices
Grant 9,722,053 - Sung , et al. August 1, 2 | 2017-08-01 |
Hybrid Fin Cut Etching Processes For Products Comprising Tapered And Non-tapered Finfet Semiconductor Devices
App 20170213767 - Sung; Min Gyu ; et al. | 2017-07-27 |
Self-aligned Device Level Contact Structures
App 20170207122 - Park; Chanro ; et al. | 2017-07-20 |
Dual thick EG oxide integration under aggressive SG fin pitch
Grant 9,691,664 - Sung , et al. June 27, 2 | 2017-06-27 |
Methods Of Forming A Protection Layer On A Semiconductor Device And The Resulting Device
App 20170179246 - Xie; Ruilong ; et al. | 2017-06-22 |
Forming uniform WF metal layers in gate areas of nano-sheet structures
Grant 9,685,522 - Kim , et al. June 20, 2 | 2017-06-20 |
Methods of forming self-aligned device level contact structures
Grant 9,653,356 - Park , et al. May 16, 2 | 2017-05-16 |
Block level patterning process
Grant 9,646,884 - Park , et al. May 9, 2 | 2017-05-09 |
Methods of forming a protection layer on a semiconductor device and the resulting device
Grant 9,634,115 - Xie , et al. April 25, 2 | 2017-04-25 |
Semiconductor Device With A Gate Contact Positioned Above The Active Region
App 20170110549 - Xie; Ruilong ; et al. | 2017-04-20 |
Semiconductor devices with an etch stop layer on gate end-portions located above an isolation region
Grant 9,627,535 - Xie , et al. April 18, 2 | 2017-04-18 |
Method of making threshold voltage tuning using self-aligned contact cap
Grant 9,601,387 - Cai , et al. March 21, 2 | 2017-03-21 |
Method for controlled recessing of materials in cavities in IC devices
Grant 9,589,850 - Park , et al. March 7, 2 | 2017-03-07 |
Methods for producing integrated circuits using long and short regions and integrated circuits produced from such methods
Grant 9,583,584 - Park , et al. February 28, 2 | 2017-02-28 |
Methods For Forming Fin Structures
App 20170053836 - PARK; Chanro ; et al. | 2017-02-23 |
Dual Liner Cmos Integration Methods For Finfet Devices
App 20170053835 - Sung; Min Gyu ; et al. | 2017-02-23 |
Methods Of Forming Self-aligned Device Level Contact Structures
App 20170047253 - Park; Chanro ; et al. | 2017-02-16 |
Methods For Forming Transistor Devices With Different Threshold Voltages And The Resulting Devices
App 20170040220 - Kim; Hoon ; et al. | 2017-02-09 |
Co-fabrication of non-planar semiconductor devices having different threshold voltages
Grant 9,552,992 - Kim , et al. January 24, 2 | 2017-01-24 |
Methods For Producing Integrated Circuits Using Long And Short Regions And Integrated Circuits Produced From Such Methods
App 20170012107 - Park; Chanro ; et al. | 2017-01-12 |
Punch-through-stop after partial fin etch
Grant 9,543,215 - Lim , et al. January 10, 2 | 2017-01-10 |
Self-aligned gate-first VFETs using a gate spacer recess
Grant 9,536,793 - Zhang , et al. January 3, 2 | 2017-01-03 |
Methods of forming punch through stop regions on FinFET devices on CMOS-based IC products using doped spacers
Grant 9,508,604 - Sung , et al. November 29, 2 | 2016-11-29 |
Methods of forming self-aligned contact structures on semiconductor devices and the resulting devices
Grant 9,502,286 - Xie , et al. November 22, 2 | 2016-11-22 |
Methods for forming transistor devices with different source/drain contact liners and the resulting devices
Grant 9,502,308 - Park , et al. November 22, 2 | 2016-11-22 |
Block Level Patterning Process
App 20160322260 - PARK; Chanro ; et al. | 2016-11-03 |
Semiconductor Device Structures With Self-aligned Fin Structure(s) And Fabrication Methods Thereof
App 20160315182 - XIE; Ruilong ; et al. | 2016-10-27 |
Semiconductor device structures with self-aligned fin structure(s) and fabrication methods thereof
Grant 9,478,661 - Xie , et al. October 25, 2 | 2016-10-25 |
Methods for forming transistor devices with different threshold voltages and the resulting devices
Grant 9,478,538 - Kim , et al. October 25, 2 | 2016-10-25 |
Punch-through-stop After Partial Fin Etch
App 20160307807 - LIM; Kwan-Yong ; et al. | 2016-10-20 |
Methods of increasing silicide to epi contact areas and the resulting devices
Grant 9,461,171 - Xie , et al. October 4, 2 | 2016-10-04 |
Co-fabrication Of Non-planar Semiconductor Devices Having Different Threshold Voltages
App 20160254158 - KIM; Hoon ; et al. | 2016-09-01 |
Methods of performing fin cut etch processes for taper FinFET semiconductor devices and the resulting devices
Grant 9,425,106 - Xie , et al. August 23, 2 | 2016-08-23 |
Methods of using a metal protection layer to form replacement gate structures for semiconductor devices
Grant 9,425,103 - Xie , et al. August 23, 2 | 2016-08-23 |
Method Of Forming A Semiconductor Structure Including A Plurality Of Fins And An Alignment/overlay Mark
App 20160204034 - Sung; Min Gyu ; et al. | 2016-07-14 |
Method of uniform fin recessing using isotropic etch
Grant 9,391,174 - Sung , et al. July 12, 2 | 2016-07-12 |
Method of forming a semiconductor structure including a plurality of fins and an alignment/overlay mark
Grant 9,379,017 - Sung , et al. June 28, 2 | 2016-06-28 |
Methods Of Forming Epi Semiconductor Material In A Trench Formed Above A Semiconductor Device And The Resulting Devices
App 20160181426 - Xie; Ruilong ; et al. | 2016-06-23 |
Methods Of Forming Self-aligned Contact Structures On Semiconductor Devices And The Resulting Devices
App 20160163585 - Xie; Ruilong ; et al. | 2016-06-09 |
Methods Of Forming Replacement Gate Structures For Semiconductor Devices And The Resulting Devices
App 20160163601 - Xie; Ruilong ; et al. | 2016-06-09 |
Methods Of Forming Diffusion Breaks On Integrated Circuit Products Comprised Of Finfet Devices And The Resulting Products
App 20160163604 - Xie; Ruilong ; et al. | 2016-06-09 |
Low line resistivity and repeatable metal recess using CVD cobalt reflow
Grant 9,362,377 - Kim , et al. June 7, 2 | 2016-06-07 |
Field Effect Transistor And Method Of Fabrication
App 20160099333 - Kim; Hoon ; et al. | 2016-04-07 |
Gate Structures For Semiconductor Devices With A Conductive Etch Stop Layer
App 20160049399 - Park; Chanro ; et al. | 2016-02-18 |
Replacement Metal Gate And Fabrication Process With Reduced Lithography Steps
App 20160042954 - Sung; Min Gyu ; et al. | 2016-02-11 |
Methods Of Forming A Protection Layer On A Semiconductor Device And The Resulting Device
App 20150364326 - Xie; Ruilong ; et al. | 2015-12-17 |
Methods Of Fabricating Semiconductor Fin Structures
App 20150340289 - PARK; Chanro ; et al. | 2015-11-26 |
Methods Of Increasing Silicide To Epi Contact Areas And The Resulting Devices
App 20150340497 - Xie; Ruilong ; et al. | 2015-11-26 |
Methods Of Forming Epi Semiconductor Material In A Trench Formed Above A Semiconductor Device And The Resulting Devices
App 20150318398 - Xie; Ruilong ; et al. | 2015-11-05 |
Semiconductor Device Configured For Avoiding Electrical Shorting
App 20150318345 - XIE; Ruilong ; et al. | 2015-11-05 |
Threshold Voltage Tuning Using Self-aligned Contact Cap
App 20150194350 - CAI; Xiuyu Harry ; et al. | 2015-07-09 |
Euv Pellicle Frame With Holes And Method Of Forming
App 20150168824 - SUN; Lei ; et al. | 2015-06-18 |
Field Effect Transistor And Method Of Fabrication
App 20150001642 - Kim; Hoon ; et al. | 2015-01-01 |
Methods Of Forming A Masking Layer For Patterning Underlying Structures
App 20140273473 - Schmid; Gerard M. ; et al. | 2014-09-18 |
Methods Of Forming Trench/via Features In An Underlying Structure Using A Process That Includes A Masking Layer Formed By A Directed Self-assembly Process
App 20140273469 - Wahl; Jeremy A. ; et al. | 2014-09-18 |
Integrated Circuits And Methods For Fabricating Integrated Circuits Having Metal Gate Electrodes
App 20140231885 - Xie; Ruilong ; et al. | 2014-08-21 |
Field Effect Transistor And Method Of Fabrication
App 20140070283 - Kim; Hoon ; et al. | 2014-03-13 |
Integrated Circuits And Processes For Forming Integrated Circuits Having An Embedded Electrical Interconnect Within A Substrate
App 20130299994 - Park; Chanro ; et al. | 2013-11-14 |
Methods Of Forming Copper-based Conductive Structures On Semiconductor Devices
App 20130244422 - Zhang; Xunyuan ; et al. | 2013-09-19 |
| 