U.S. patent application number 14/865784 was filed with the patent office on 2016-02-18 for gate structures for semiconductor devices with a conductive etch stop layer.
The applicant listed for this patent is GLOBALFOUNDRIES Inc.. Invention is credited to Hoon Kim, Chanro Park, Min Gyu Sung.
Application Number | 20160049399 14/865784 |
Document ID | / |
Family ID | 54434682 |
Filed Date | 2016-02-18 |
United States Patent
Application |
20160049399 |
Kind Code |
A1 |
Park; Chanro ; et
al. |
February 18, 2016 |
GATE STRUCTURES FOR SEMICONDUCTOR DEVICES WITH A CONDUCTIVE ETCH
STOP LAYER
Abstract
One illustrative gate structure of a transistor device disclosed
herein includes a high-k gate insulation layer and a work function
metal layer positioned on the high-k gate insulation layer. The
device further includes a first bulk metal layer positioned on the
work function metal layer. The device further includes a second
bulk metal layer. The first and second bulk metal layers have upper
surfaces that are at substantially the same height level, and the
first and second bulk metal layers are made of substantially the
same material. The device further includes a conductive etch stop
layer between the first and second bulk metal layers.
Inventors: |
Park; Chanro; (Clifton Park,
NY) ; Kim; Hoon; (Clifton Park, NY) ; Sung;
Min Gyu; (Latham, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
GLOBALFOUNDRIES Inc. |
Grand Cayman |
|
KY |
|
|
Family ID: |
54434682 |
Appl. No.: |
14/865784 |
Filed: |
September 25, 2015 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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14458633 |
Aug 13, 2014 |
9190488 |
|
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14865784 |
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Current U.S.
Class: |
257/327 |
Current CPC
Class: |
H01L 29/51 20130101;
H01L 21/2807 20130101; H01L 27/105 20130101; H01L 21/823456
20130101; H01L 29/772 20130101; H01L 21/82345 20130101; H01L
21/28026 20130101; H01L 29/518 20130101; H01L 27/088 20130101; H01L
29/7833 20130101; H01L 29/42364 20130101; H01L 27/092 20130101;
H01L 21/283 20130101; H01L 29/785 20130101; H01L 29/401 20130101;
H01L 29/517 20130101; H01L 29/4238 20130101; H01L 29/66545
20130101; H01L 29/4958 20130101; H01L 27/0922 20130101; H01L
27/0928 20130101 |
International
Class: |
H01L 27/092 20060101
H01L027/092; H01L 29/49 20060101 H01L029/49; H01L 29/51 20060101
H01L029/51; H01L 29/423 20060101 H01L029/423 |
Claims
1. A gate structure of a transistor device, comprising: a high-k
gate insulation layer; a work function metal layer positioned on
said high-k gate insulation layer; a first bulk metal layer
positioned on said work function metal layer; a second bulk metal
layer, said first and second bulk metal layers comprising upper
surfaces that are at substantially the same height level; and a
conductive etch stop layer positioned between said first and second
bulk metal layers.
2. The device of claim 1, further comprising a gate cap layer above
said conductive etch stop layer.
3. The device of claim 1, wherein said conductive etch stop layer
comprises a material selected from the group consisting of
titanium, titanium nitride, tantalum, tantalum nitride, tungsten
nitride, aluminum, ruthenium, titanium silicon nitride and tantalum
silicon nitride.
4. The device of claim 1, wherein said first and second bulk metal
layers comprise tungsten.
5. The device of claim 1, wherein said first and second bulk metal
layers are made of the same material.
6. The device of claim 1, wherein said first bulk metal layer
comprises a different material than said second bulk metal
layer.
7. The device of claim 1, wherein said work function metal layer
comprises titanium nitride.
8. The device of claim 1, wherein said work function metal layer
and said conductive etch stop layer are made of the same
material.
9. The device of claim 1, further comprising a gate cap layer that
is positioned on and in contact with an upper surface of said first
bulk metal layer, an upper surface of said conductive etch stop
layer and an upper surface of said second bulk metal layer.
10. The device of claim 1, wherein an upper surface of said first
bulk metal layer, an upper surface of said conductive etch stop
layer and an upper surface of said second bulk metal layer are all
positioned in a common horizontal plane
11. The device of claim 1, wherein said conductive etch stop layer
comprises a material selected from the group consisting of
titanium, titanium nitride, tantalum, tantalum nitride, tungsten
nitride, aluminum, ruthenium, titanium silicon nitride and tantalum
silicon nitride.
12. The device of claim 11, wherein said first bulk metal layer and
said second bulk metal layer comprise tungsten.
13. The device of claim 1, wherein, in a cross-section taken
through said gate structure in a direction that is parallel to a
gate length direction of said transistor device: each of said
high-k gate insulation layer, said work function metal layer, said
first bulk metal layer, and said conductive etch stop layer have a
generally U-shaped cross-sectional configuration; and said second
bulk metal layer has a generally rectangular cross-sectional
configuration, and said second bulk metal layer is bounded on three
sides by said generally U-shaped conductive etch stop layer.
14. A gate structure of a transistor device, comprising: a high-k
gate insulation layer; a work function metal layer positioned on
said high-k gate insulation layer, said work function metal layer
comprising an upper surface; a first bulk metal layer positioned on
said work function metal layer, said first bulk metal layer
comprising an upper surface; a second bulk metal layer, said second
bulk metal layer comprising an upper surface; a conductive etch
stop layer positioned between said first and second bulk metal
layers, said conductive etch stop layer comprising an upper
surface, wherein said upper surfaces of said conductive etch stop
layer, said work function metal layer, said first bulk metal layer
and said second bulk metal layer are positioned at substantially
the same height level above an upper surface of a semiconductor
substrate; and a gate cap layer that is positioned on and in
contact with said upper surfaces of said first bulk metal layer,
said conductive etch stop layer and said second bulk metal
layer.
15. The device of claim 14, wherein said first and second bulk
metal layers are made of the same material.
16. The device of claim 14, wherein said first bulk metal layer
comprises a different material than said second bulk metal
layer.
17. The device of claim 14, wherein said work function metal layer
and said conductive etch stop layer are made of the same
material.
18. The device of claim 15, wherein, in a cross-section taken
through said gate structure in a direction that is parallel to a
gate length direction of said transistor device: each of said
high-k gate insulation layer, said work function metal layer, said
first bulk metal layer, and said conductive etch stop layer have a
generally U-shaped cross-sectional configuration; and said second
bulk metal layer has a generally rectangular cross-sectional
configuration, and said second bulk metal layer is bounded on three
sides by said generally U-shaped conductive etch stop layer.
19. An integrated circuit device, comprising: a gate structure of a
short channel device comprising: a first high-k gate insulation
layer comprising a high-k material; a first work function metal
layer positioned on said first high-k gate insulation layer, said
first work function metal layer comprising a work function metal
material; and a first bulk metal layer positioned on said first
work function metal layer, said first bulk metal layer comprising a
bulk metal material; and a gate structure of a long channel device
comprising: a second high-k gate insulation layer comprising said
high-k material; a second work function metal layer positioned on
said second high-k gate insulation layer, said second work function
metal layer comprising said work function metal material; another
first bulk metal layer positioned on said second work function
metal layer, said another bulk metal layer comprising said bulk
metal material; a second bulk metal layer; and a conductive etch
stop layer positioned between said another first bulk metal layer
and said second bulk metal layer.
20. The device of claim 19, further comprising: a first gate cap
layer for said short channel device, wherein said first gate cap
layer is positioned on and in contact with an upper surface of said
first work function metal layer and an upper surface of said first
bulk metal layer of said first gate structure; and a second gate
cap layer for said long channel device, wherein the second gate cap
layer is positioned on and in contact with an upper surface of said
another first bulk metal layer, an upper surface of said conductive
etch stop layer and an upper surface of said second bulk metal
layer of said second gate structure.
21. The device of claim 19, wherein said another first bulk metal
layer and said second bulk metal layer of said second gate
structure are made of the same material.
22. The device of claim 19, wherein said another first bulk metal
layer and said second bulk metal layer of said second gate
structure are made of different materials.
23. The device of claim 21, wherein said work function metal
material comprises titanium nitride.
24. The device of claim 19, wherein said second work function metal
layer and said conductive etch stop layer of said second gate
structure are made of the same material.
25. The device of claim 19, wherein an upper surface of said
another first bulk metal layer, an upper surface of said conductive
etch stop layer and an upper surface of said second bulk metal
layer of said second gate structure are all positioned in a common
horizontal plane.
26. The device of claim 19, wherein, in a cross-section taken
through said second gate structure in a direction that is parallel
to a gate length direction of said long channel device: each of
said second high-k gate insulation layer, said second work function
metal layer, said another first bulk metal layer, and said
conductive etch stop layer of said second gate structure have a
generally U-shaped cross-sectional configuration; and said second
bulk metal layer of said second gate structure has a generally
rectangular cross-sectional configuration, and said second bulk
metal layer is bounded on three sides by said generally U-shaped
conductive etch stop layer.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present disclosure generally relates to the formation of
semiconductor devices, and, more specifically, to various novel
gate structures that comprise a conductive etch stop layer
positioned between two bulk metal layers.
[0003] 2. Description of the Related Art
[0004] The fabrication of advanced integrated circuits, such as
CPUs, storage devices, ASICs (application specific integrated
circuits) and the like, requires the formation of a large number of
circuit elements in a given chip area according to a specified
circuit layout, wherein so-called metal oxide semiconductor field
effect transistors (MOSFETs or FETs) represent one important type
of circuit element that substantially determines performance of the
integrated circuits. The transistors are typically either NMOS
(NFET) or PMOS (PFET) type devices wherein the "N" and "P"
designation is based upon the type of dopants used to create the
source/drain regions of the devices. So-called CMOS (Complementary
Metal Oxide Semiconductor) technology or products refers to
integrated circuit products that are manufactured using both NMOS
and PMOS transistor devices.
[0005] Field effect transistors, whether an NMOS or a PMOS device,
typically include a source region, a drain region, a channel region
that is positioned between the source region and the drain region,
and a gate electrode positioned above the channel region. Current
flow through the FET is controlled by controlling the voltage
applied to the gate electrode. For an NMOS device, if there is no
voltage (or a logically low voltage) applied to the gate electrode,
then there is no current flow through the device (ignoring
undesirable leakage currents, which are relatively small). However,
when an appropriate positive voltage (or logically high voltage) is
applied to the gate electrode, the channel region of the NMOS
device becomes conductive, and electrical current is permitted to
flow between the source region and the drain region through the
conductive channel region. For a PMOS device, the control voltages
are reversed. Field effect transistors may come in a variety of
different physical shapes, e.g., so-called planar FET devices or
so-called 3D or FinFET devices.
[0006] For many early device technology generations, the gate
structures of most transistor elements have included a plurality of
silicon-based materials, such as a silicon dioxide and/or silicon
oxynitride gate insulation layer, in combination with a polysilicon
gate electrode. However, as the channel length of aggressively
scaled transistor elements has become increasingly small, many
newer generation devices employ gate structures that contain
alternative materials in an effort to avoid the short channel
effects which may be associated with the use of traditional
silicon-based materials in reduced channel length transistors. For
example, in some aggressively scaled transistor elements, which may
have channel lengths on the order of approximately 10-32 nm or
less, gate structures that include a so-called high-k dielectric
gate insulation layer and one or metal layers that function as the
gate electrode (HK/MG) have been implemented. Such alternative gate
structures have been shown to provide significantly enhanced
operational characteristics over the heretofore more traditional
silicon dioxide/polysilicon gate structure configurations.
[0007] Depending on the specific overall device requirements,
several different high-k materials--i.e., materials having a
dielectric constant, or k-value, of approximately 10 or
greater--have been used with varying degrees of success for the
gate insulation layer in an HK/MG gate structure. For example, in
some transistor element designs, a high-k gate insulation layer may
include tantalum oxide (Ta.sub.2O.sub.5), hafnium oxide
(HfO.sub.2), zirconium oxide (ZrO.sub.2), titanium oxide
(TiO.sub.2), aluminum oxide (Al.sub.2O.sub.3), hafnium silicates
(HfSiO.sub.x) and the like. Furthermore, one or more
non-polysilicon metal gate electrode materials--i.e., a metal gate
stack--may be used in HK/MG configurations to control the work
function of the transistor. These metal gate electrode materials
may include, for example, one or more layers of titanium (Ti),
titanium nitride (TiN), titanium-aluminum (TiAl),
titanium-aluminum-carbon (TiALC), aluminum (Al), aluminum nitride
(AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide
(TaC), tantalum carbonitride (TaCN), tantalum silicon nitride
(TaSiN), tantalum silicide (TaSi) and the like.
[0008] In many cases, the metal-containing gate structures are
formed by performing well-known replacement gate processing
techniques. In general, the replacement gate technique involves
forming a sacrificial gate structure (e.g., a silicon dioxide gate
insulating layer and a polysilicon gate electrode) and a gate cap
layer, followed by forming a protective sidewall spacer adjacent
the gate structure. The sacrificial gate structure is eventually
removed to define a replacement gate cavity between the spacer.
Thereafter, the high-k gate insulating layer and the various layers
of metal that will comprise the gate electrode are sequentially
deposited in the gate cavity. Excess materials positioned outside
of the gate cavity are removed by performing one or more CMP
process operations. Next, one or more recess etching processing
operations are performed to remove some of the materials within the
gate cavity to create a space for the formation of a protective
gate cap layer. The gate cap layer is formed by overfilling the
recessed cavity with a material, such as silicon nitride, and
thereafter performing a CMP process to remove the excess gate cap
materials.
[0009] In modern device fabrication, transistors having relative
short channel lengths and transistors having relatively long
channel lengths are formed on the same substrate. Unfortunately,
some of the metal materials employed in such metal gate structures,
such as tungsten, have different etch characteristics depending
upon the channel length of the transistor device, due to
differences in grain sizes. Accordingly, during the recess etching
process that is performed to make room for the gate cap layer above
the replacement metal-containing gate structure, some of the gate
structure materials may be inadvertently removed or etched, leading
to poor device performance or lower yield. More specifically,
etching the gate structures of devices having different channel
lengths may result in uneven and inadvertent etching of at least
the metal gate materials, such as tungsten or the like, due to the
larger grain size and surface area of the metal material in the
longer channel devices.
[0010] The present disclosure is directed to various novel gate
structures that comprise a conductive etch stop layer positioned
between two bulk metal layers that may solve or reduce one or more
of the problems identified above.
SUMMARY OF THE INVENTION
[0011] The following presents a simplified summary of the invention
in order to provide a basic understanding of some aspects of the
invention. This summary is not an exhaustive overview of the
invention. It is not intended to identify key or critical elements
of the invention or to delineate the scope of the invention. Its
sole purpose is to present some concepts in a simplified form as a
prelude to the more detailed description that is discussed
later.
Generally, the present disclosure is directed to various novel gate
structures that comprise a conductive etch stop layer positioned
between two bulk metal layers. One illustrative gate structure of a
transistor device disclosed herein includes a high-k gate
insulation layer and a work function metal layer positioned on the
high-k gate insulation layer. The device further includes a first
bulk metal layer positioned on the work function metal layer. The
device further includes a second bulk metal layer. The first and
second bulk metal layers have upper surfaces that are at
substantially the same height level, and the first and second bulk
metal layers are made of substantially the same material. The
device further includes a conductive etch stop layer between the
first and second bulk metal layers.
[0012] Another illustrative device disclosed herein includes an
integrated circuit device including a gate structure of a short
channel device including a high-k gate insulation layer, a work
function metal layer positioned on the high-k gate insulation
layer, and a first bulk metal layer positioned on the work function
metal layer. The device further includes a gate structure of a long
channel device including a second high-k gate insulation layer, a
second work function metal layer positioned on the second high-k
gate insulation layer, another first bulk metal layer positioned on
the second work function metal layer, a second bulk metal layer,
and a conductive etch stop layer positioned between the another
first bulk metal layer and the second bulk metal layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The disclosure may be understood by reference to the
following description taken in conjunction with the accompanying
drawings, in which like reference numerals identify like elements,
and in which:
[0014] FIGS. 1A-1K depict various illustrative methods disclosed
herein of forming gate structures of semiconductor devices and the
resulting devices.
[0015] While the subject matter disclosed herein is susceptible to
various modifications and alternative forms, specific embodiments
thereof have been shown by way of example in the drawings and are
herein described in detail. It should be understood, however, that
the description herein of specific embodiments is not intended to
limit the invention to the particular forms disclosed, but on the
contrary, the intention is to cover all modifications, equivalents,
and alternatives falling within the spirit and scope of the
disclosure as defined by the appended claims.
DETAILED DESCRIPTION
[0016] Various illustrative embodiments of the invention are
described below. In the interest of clarity, not all features of an
actual implementation are described in this specification. It will
of course be appreciated that in the development of any such actual
embodiment, numerous implementation-specific decisions must be made
to achieve the developers' specific goals, such as compliance with
system-related and business-related constraints, which will vary
from one implementation to another. Moreover, it will be
appreciated that such a development effort might be complex and
time-consuming, but would nevertheless be a routine undertaking for
those of ordinary skill in the art having the benefit of this
disclosure.
[0017] The present subject matter will now be described with
reference to the attached figures. Various structures, systems, and
devices are schematically depicted in the drawings for purposes of
explanation only and so as to not obscure the present disclosure
with details that are well known to those skilled in the art.
Nevertheless, the attached drawings are included to describe and
explain illustrative examples of the present disclosure. The words
and phrases used herein should be understood and interpreted to
have a meaning consistent with the understanding of those words and
phrases by those skilled in the relevant art. No special definition
of a term or phrase, i.e., a definition that is different from the
ordinary and customary meaning as understood by those skilled in
the art, is intended to be implied by consistent usage of the term
or phrase herein. To the extent that a term or phrase is intended
to have a special meaning, i.e., a meaning other than that
understood by skilled artisans, such a special definition will be
expressly set forth in the specification in a definitional manner
that directly and unequivocally provides the special definition for
the term or phrase.
[0018] The present disclosure relates to various novel gate
structures that comprise a conductive etch stop layer positioned
between two bulk metal layers. The methods and devices disclosed
herein may be employed in manufacturing products using a variety of
technologies, e.g., NMOS, PMOS, CMOS, etc., and they may be
employed in manufacturing a variety of different devices, e.g.,
memory devices, logic devices, ASICs, etc. Of course, the
disclosure should not be considered limited to the illustrative
examples depicted and described herein.
[0019] As will be appreciated by those skilled in the art after a
complete reading of the present application, the disclosure may be
employed in forming integrated circuit products using planar
transistor devices, as well as so-called 3D devices, such as
FinFETs, or a combination of such devices. For purposes of
disclosure, reference will be made to an illustrative process flow
wherein an integrated circuit product 100 is formed with a
plurality of planar transistor devices 10, 11. However, the
disclosure should not be considered limited to such an illustrative
example. With reference to the attached figures, various
illustrative embodiments of the methods and devices disclosed
herein will now be described in more detail.
[0020] FIG. 1A is a simplified view of an illustrative integrated
circuit product 100 at an early stage of manufacturing, wherein a
pair of illustrative semiconductor devices 10, 11 have been formed
in and above the semiconductor substrate 12. The substrate 12 may
have a variety of configurations, such as the depicted bulk silicon
configuration. The substrate 12 may also have a
silicon-on-insulator (SOI) configuration that includes a bulk
silicon layer, a buried insulation layer and an active layer,
wherein the semiconductor devices 10, 11 are formed in and above
the active layer. The substrate 12 may be made of silicon or it may
be made of materials other than silicon. Thus, the terms
"substrate" or "semiconductor substrate" should be understood to
cover all semiconducting materials and all forms of such
materials.
[0021] A replacement gate process may be used when forming the gate
structures of planar devices or 3D devices. As shown in FIG. 1A,
the process includes the formation of structures above an active
area of the substrate 12 that is defined by shallow trench
isolation structures 13. The various components and structures of
the product 100 may be formed using a variety of different
materials and by performing a variety of known techniques. The
layers of material may be formed by any of a variety of different
known techniques, e.g., a chemical vapor deposition (CVD) process,
an atomic layer deposition (ALD) process, a thermal growth process,
spin-coating techniques, etc. At the point of fabrication depicted
in FIG. 1A, the integrated circuit product 100 includes two devices
10, 11 having different channel lengths 10L and 11L. More
specifically, the device 10 is a "short channel" device, which, for
purposes of this disclosure and the attached claims, shall be
understood to be a transistor device wherein the gate length 10L is
40 nm or less. On the other hand, the device 11 is a "long channel"
device, which, for purposes of this disclosure and the attached
claims, shall be understood to be a transistor device wherein the
gate length 11L is greater than 40 nm. Each device 10, 11 includes
a sacrificial gate insulation layer 14, a dummy or sacrificial gate
electrode 15, outermost sidewall spacers 16, a layer of insulating
material 17 and source/drain regions 18 formed in the substrate 12.
For simplicity, the two devices 10, 11 are depicted as being formed
side-by-side on the substrate 12. However, in practice, the devices
10, 11 may be positioned remotely from one another on the substrate
12.
[0022] The various components and structures of the devices 10, 11
may be formed using a variety of different materials and by
performing a variety of known techniques. For example, the
sacrificial gate insulation layers 14 may be made of silicon
dioxide, the sacrificial gate electrodes 15 may be made of
polysilicon, the sidewall spacers 16 may be made of silicon nitride
and the layer of insulating material 17 may be made of silicon
dioxide. The source/drain regions 18 typically include implanted
dopant materials (N-type dopants for NMOS devices and P-type
dopants for PMOS devices) that are implanted into the substrate 12
using known masking and ion implantation techniques. At the point
of fabrication depicted in FIG. 1A, various structures of the
devices 10, 11 have been formed and a chemical mechanical polishing
(CMP) process has been performed to remove any materials above the
sacrificial gate electrodes 15 (such as a protective cap layer (not
shown) made of silicon nitride) so that at least the sacrificial
gate electrodes 15 may be removed.
[0023] As shown in FIG. 1B, one or more etching processes were
performed to remove the sacrificial gate electrodes 15 and the
sacrificial gate insulation layers 14 to thereby define trenches or
gate cavities 19, 20 where replacement gate structures will
subsequently be formed. As shown, due to the difference in channel
lengths 10L and 11L, the gate cavity 19 is narrower than the gate
cavity 20. Typically, the sacrificial gate insulation layers 14 are
removed as part of the replacement gate technique, as depicted
herein. However, the sacrificial gate insulation layers 14 may not
be removed in all applications.
[0024] Next, as shown in FIGS. 1C-1F, various layers of material
that will constitute replacement gate structures 30, 32 (shown in
FIG. 1J) are formed in the gate cavities 19, 20. FIG. 1C
illustrates the product 100 after various deposition processes have
been performed. First, a high-k gate insulation layer 30A was
conformably deposited onto the product 100 and within the gate
cavities 19, 20. As used herein and in the attached claims, high-k
materials have a dielectric constant, or k-value, of 10 or greater.
As described above, the high-k gate insulation layer may 30A be
made of various materials and deposited in various thicknesses in
various embodiments. Next, a work function metal layer 30B was
conformably deposited onto the product 100 and on the high-k gate
insulation layer 30A within the gate cavities 19, 20. As described
above, the work function metal layer 30B may be made of various
materials and deposited in various thicknesses in various
embodiments. In at least one embodiment, the work function metal
layer 30B may be made of titanium nitride.
[0025] As shown in FIG. 1D, a first bulk metal layer 30C was
deposited onto the product 100 and on the work function metal layer
30B. When deposited, the first bulk metal layer 30C overfills the
narrower gate cavity 19, but does not overfill the larger gate
cavity 20. As shown, in one embodiment, the first bulk metal layer
30C may be made of tungsten, and it may be deposited to a thickness
of between 10-20 nm. However, in various other embodiments, the
first bulk metal layer 30C may be made of other metals and it may
be formed to different thicknesses as desired.
[0026] As shown in FIG. 1E, a conductive etch stop layer 30D was
conformably deposited onto the product 100 on the first bulk metal
layer 30C and within the wider gate cavity 20. In general, the
conductive etch stop layer 30D should be made of a conductive
material that provides good etch selectivity relative to another
bulk metal layer that will be formed above the conductive etch stop
layer 30D, as described more fully below. As shown, in one
embodiment, the conductive etch stop layer 30D may be made of
titanium nitride, and it may be deposited such that it has a
thickness between 2 nm and 10 nm. However, in various other
embodiments, the conductive etch stop layer 30D may be made of
other conductive materials, such as titanium, titanium nitride,
tantalum, tantalum nitride, tungsten nitride, aluminum, ruthenium,
titanium silicon nitride and tantalum silicon nitride, and its
thickness may be varied as desired. Since the conductive etch stop
layer 30D is made of a conductive material--and not an insulating
material--any increase in gate resistance is minimized. In at least
one embodiment, the conductive etch stop layer 30D may be made of
the same material as the work function metal layer 30B, e.g.
titanium nitride, but such a situation is not required for all
applications. Because the narrower gate cavity 19 was overfilled
prior to the formation of the etch stop layer 30D, the conductive
etch stop layer 30D is deposited into the wider gate cavity 20 but
not the narrower gate cavity 19.
[0027] FIG. 1F depicts the product 100 after a second bulk metal
layer 30E was deposited on the conductive etch stop layer 30D so as
to overfill the wider gate cavity 20. In at least one embodiment,
the second bulk metal layer 30E may be made of tungsten, and it may
be deposited to any desired thickness. However, in various other
embodiments, the second bulk metal layer 30E may be made of other
conductive materials. As shown in the depicted example, the second
bulk metal layer 30E is deposited thicker than the first bulk metal
layer 30C, and both include tungsten. However, in other
embodiments, the second bulk metal layer 30E may be made of a
different material than the first bulk metal layer 30C.
[0028] FIG. 1G depicts the product 100 after one or more CMP
processes have been performed to planarize the product 100 using
the insulating layer 17 as a polish-stop layer. These operations
result in the removal of portions of the gate insulation layer 30A,
the work function metal layer 30B, the first bulk metal layer 30C,
the conductive etch stop layer 30D and the second bulk metal layer
30E outside of the gate cavities 19, 20. In various other
embodiments, the CMP process may be performed to planarize the
product 100 using the conductive etch stop layer 30D as a
polish-stop layer. Next, the conductive etch stop layer 30D may be
selectively polished. Next, another CMP process is performed using
the work function metal layer 30B as a polish-stop layer. These
operations result in the removal of portions of the first bulk
metal layer 30C, conductive etch stop layer 30D and the second bulk
metal layer 30E outside of the gate cavities 19, 20. In this
embodiment, the high-k gate insulation layer 30A and work function
metal layer 30B are removed from outside the gate cavities 19, 20
after the recessing performed in FIG. 1H and discussed below.
[0029] FIG. 1H depicts the product 100 after one or more recess
etching processes were performed such that the first and second
bulk metal layers 30C, 30E were etched and recessed selectively
relative to the surrounding layers 30B, 30D. As shown, the etching
process was a timed etching process that left a portion of the
second bulk metal layer 30E intact above the conductive etch stop
layer 30D. As noted previously, the etch rate of the first and
second bulk metal layers 30C, 30E in the wider gate cavity 20 will
typically be faster than the etch rate of the first bulk metal
layer 30C in the narrower gate cavity 19 due to the larger grain
size and surface area of tungsten in the wider gate cavity 20.
However, for simplicity, any such difference in etching rates is
not depicted in the resulting structures in the attached
drawings.
[0030] As shown in FIG. 1I, the recessing of the first and second
bulk metal layers 30C, 30E may result in uneven etching within the
second gate cavity 20 causing one or more notches or gouges 40 to
be formed where portions of the second bulk metal layer 30E were
etched faster than the surrounding portions. However, the presence
of the conductive etch stop layer 30D prevented the first bulk
metal layer 30C below the conductive etch stop layer 30D from being
etched. Additionally, the presence of the conductive etch stop
layer 30D allows for a greater window of time for performing the
recess etching process to recess the first and second bulk metal
layers 30C, 30E within both cavities 19, 20. In some applications,
this means that the first and second bulk metal layers 30C, 30E may
be recessed to approximately the same height. The presence of the
conductive etch stop layer 30D also allows for the gate structures
within the narrower gate cavity 19 and wider gate cavity 20 to be
processed simultaneously, i.e., to be subjected to the recess
etching process at the same time. Specifically, the recipe for the
recess etching recipes may be the same for both short and long
channel devices and it need not be adjusted based on the channel
length of the different devices. Accordingly, the short channel
devices and long channel devices do not have to be separately
masked and etched when performing the recess etching process.
[0031] As shown in FIG. 1J (the notches or gouges 40 due to uneven
etching are not shown), one or more etching processes were
performed to selectively remove portions of the conductive etch
stop layer 30D, the work function metal layer 30B and the high-k
gate insulation layer 30A relative to the surrounding first and
second bulk metal layers 30C, 30E and the sidewall spacer 16. In at
least one embodiment, the same etching process may be performed to
recess the conductive etch stop layer 30D and work function metal
layer 30B simultaneously. As such, the replacement gate structures
30 (the narrower completed gate structure), 32 (the wider completed
gate structure) have been defined. In at least one embodiment, the
etching process was performed such that the surfaces of the
completed replacement gate structures 30, 32 are relatively planar
and approximately at the same height level. The wider completed
gate structure 32 includes the recessed conductive etch stop layer
30D between the first bulk metal layer 30C and the recessed second
bulk metal layer 30E in at least one embodiment. Of course, the
materials used for the replacement gate structures may vary
depending upon the application, and the materials for NMOS and PMOS
devices are typically different.
[0032] As shown in FIG. 1K, one or more deposition and CMP
processes were performed to form gate cap layers 31 in the gate
cavities 19, 20. Specifically, a layer of gate cap material, such
as silicon nitride, was deposited onto the product 100 so as to
overfill the cavities 19, 20 above the gate structures 30, 32.
Next, a CMP process was performed to remove any excess material
positioned above the surface of the layer of insulating material 17
and to planarize the surface of the product 100. The gate cap
layers 31 were formed to protect the underlying gate materials
during subsequent processing operations.
[0033] The particular embodiments disclosed above are illustrative
only, as the disclosure may be modified and practiced in different
but equivalent manners apparent to those skilled in the art having
the benefit of the teachings herein. For example, the process steps
set forth above may be performed in a different order. Furthermore,
no limitations are intended to the details of construction or
design herein shown, other than as described in the claims below.
It is therefore evident that the particular embodiments disclosed
above may be altered or modified and all such variations are
considered within the scope and spirit of the disclosure. Note that
the use of terms, such as "first," "second," "third" or "fourth" to
describe various processes or structures in this specification and
in the attached claims is only used as a shorthand reference to
such steps/structures and does not necessarily imply that such
steps/structures are performed/formed in that ordered sequence. Of
course, depending upon the exact claim language, an ordered
sequence of such processes may or may not be required. Accordingly,
the protection sought herein is as set forth in the claims
below.
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