| Patent | Date |
|---|
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
App 20200381429 - Smayling; Michael C. ; et al. | 2020-12-03 |
Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same
App 20200295044 - Becker; Scott T. ; et al. | 2020-09-17 |
Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
Grant 10,734,383 - Smayling , et al. | 2020-08-04 |
Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
Grant 10,727,252 - Becker , et al. | 2020-07-28 |
Cross-coupled transistor circuit defined on four gate electrode tracks
Grant 10,658,385 - Becker , et al. | 2020-05-19 |
Cross-coupled transistor circuit defined on three gate electrode tracks
Grant 10,651,200 - Becker , et al. | 2020-05-12 |
Cell Circuit and Layout with Linear Finfet Structures
App 20200035663 - Becker; Scott T. | 2020-01-30 |
Cell circuit and layout with linear finfet structures
Grant 10,446,536 - Becker Oc | 2019-10-15 |
Circuitry and layouts for XOR and XNOR logic
Grant 10,230,377 - Becker | 2019-03-12 |
Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid
Grant 10,217,763 - Becker , et al. Feb | 2019-02-26 |
Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid
Grant 10,186,523 - Becker , et al. Ja | 2019-01-22 |
Semiconductor Chip Having Region Including Gate Electrode Features Formed In Part from Rectangular Layout Shapes on Gate Horizontal Grid and First-Metal Structures Formed In Part from Rectangular Layout Shapes on First-Metal Vertical Grid
App 20190019810 - Becker; Scott T. ; et al. | 2019-01-17 |
Semiconductor Chip Having Region Including Gate Electrode Features of Rectangular Shape on Gate Horizontal Grid and First-Metal Structures of Rectangular Shape on At Least Eight First-Metal Gridlines of First-Metal Vertical Grid
App 20180374872 - Becker; Scott T. ; et al. | 2018-12-27 |
Semiconductor Chip Having Region Including Gate Electrode Features of Rectangular Shape on Gate Horizontal Grid and First-Metal Structures of Rectangular Shape on First-Metal Vertical Grid
App 20180374871 - Becker; Scott T. ; et al. | 2018-12-27 |
Semiconductor Chip Having Region Including Gate Electrode Features Formed In Part from Rectangular Layout Shapes on Gate Horizontal Grid and First-Metal Structures Formed In Part from Rectangular Layout Shapes on At Least Eight First-Metal Gridlines of First-Metal Vertical Grid
App 20180374873 - Becker; Scott T. ; et al. | 2018-12-27 |
Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures
Grant 10,141,334 - Becker , et al. Nov | 2018-11-27 |
Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures
Grant 10,141,335 - Becker , et al. Nov | 2018-11-27 |
Integrated circuit cell library for multiple patterning
Grant 10,074,640 - Smayling , et al. September 11, 2 | 2018-09-11 |
Coarse Grid Design Methods and Structures
App 20180204795 - Smayling; Michael C. ; et al. | 2018-07-19 |
Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same
App 20180196909 - Quandt; Jonathan R. ; et al. | 2018-07-12 |
Cross-coupled transistor circuit defined on two gate electrode tracks
Grant 10,020,321 - Becker , et al. July 10, 2 | 2018-07-10 |
Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same
App 20180175061 - Becker; Scott T. ; et al. | 2018-06-21 |
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
App 20180145075 - Smayling; Michael C. ; et al. | 2018-05-24 |
Coarse grid design methods and structures
Grant 9,917,056 - Smayling , et al. March 13, 2 | 2018-03-13 |
Methods for cell phasing and placement in dynamic array architecture and implementation of the same
Grant 9,910,950 - Quandt , et al. March 6, 2 | 2018-03-06 |
Semiconductor chip including region having rectangular-shaped gate structures and first metal structures
Grant 9,905,576 - Becker , et al. February 27, 2 | 2018-02-27 |
Methods for Multi-Wire Routing and Apparatus Implementing Same
App 20180046745 - Fox; Daryl ; et al. | 2018-02-15 |
Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
Grant 9,871,056 - Becker , et al. January 16, 2 | 2018-01-16 |
Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
Grant 9,859,277 - Smayling , et al. January 2, 2 | 2018-01-02 |
Semiconductor Chip and Method for Manufacturing the Same
App 20170365621 - Becker; Scott T. ; et al. | 2017-12-21 |
Optimizing Layout of Irregular Structures in Regular Layout Context
App 20170365548 - Kornachuk; Stephen ; et al. | 2017-12-21 |
Semiconductor Chip and Method for Manufacturing the Same
App 20170365620 - Becker; Scott T. ; et al. | 2017-12-21 |
Semiconductor Chip and Method for Manufacturing the Same
App 20170358600 - Becker; Scott T. ; et al. | 2017-12-14 |
Oversized Contacts and Vias in Layout Defined by Linearly Constrained Topology
App 20170317064 - Becker; Scott T. | 2017-11-02 |
Methods for Linewidth Modification and Apparatus Implementing the Same
App 20170309609 - Smayling; Michael C. ; et al. | 2017-10-26 |
Methods for multi-wire routing and apparatus implementing same
Grant 9,779,200 - Fox , et al. October 3, 2 | 2017-10-03 |
Circuitry and Layouts for XOR and XNOR Logic
App 20170272080 - Becker; Scott T. | 2017-09-21 |
Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires
Grant 9,754,878 - Kornachuk , et al. September 5, 2 | 2017-09-05 |
Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
Grant 9,741,719 - Smayling , et al. August 22, 2 | 2017-08-22 |
Integrated Circuit Cell Library for Multiple Patterning
App 20170229441 - Smayling; Michael C. ; et al. | 2017-08-10 |
Oversized contacts and vias in layout defined by linearly constrained topology
Grant 9,711,495 - Becker July 18, 2 | 2017-07-18 |
Methods for linewidth modification and apparatus implementing the same
Grant 9,704,845 - Smayling , et al. July 11, 2 | 2017-07-11 |
Semiconductor Chip Including Integrated Circuit Defined Within Dynamic Array Section
App 20170186772 - Becker; Scott T. ; et al. | 2017-06-29 |
Semiconductor Chip and Method for Manufacturing the Same
App 20170186771 - Becker; Scott T. ; et al. | 2017-06-29 |
Integrated Circuit Implementing Scalable Meta-Data Objects
App 20170177779 - Smayling; Michael C. ; et al. | 2017-06-22 |
Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same
App 20170170194 - Becker; Scott T. ; et al. | 2017-06-15 |
Circuitry and layouts for XOR and XNOR logic
Grant 9,673,825 - Becker June 6, 2 | 2017-06-06 |
Cell Circuit and Layout with Linear Finfet Structures
App 20170148779 - Becker; Scott T. | 2017-05-25 |
Integrated circuit cell library for multiple patterning
Grant 9,633,987 - Smayling , et al. April 25, 2 | 2017-04-25 |
Methods for Cell Boundary Encroachment and Semiconductor Devices Implementing the Same
App 20170104004 - Quandt; Jonathan R. ; et al. | 2017-04-13 |
Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect
App 20170098602 - Kornachuk; Stephen ; et al. | 2017-04-06 |
Semiconductor chip including integrated circuit defined within dynamic array section
Grant 9,595,515 - Becker , et al. March 14, 2 | 2017-03-14 |
Scalable meta-data objects
Grant 9,589,091 - Smayling , et al. March 7, 2 | 2017-03-07 |
Semiconductor Chip and Method for Manufacturing the Same
App 20170053937 - Becker; Scott T. ; et al. | 2017-02-23 |
Cell circuit and layout with linear finfet structures
Grant 9,563,733 - Becker February 7, 2 | 2017-02-07 |
Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
Grant 9,536,899 - Becker , et al. January 3, 2 | 2017-01-03 |
Semiconductor Chip and Method for Manufacturing the Same
App 20160379991 - Becker; Scott T. ; et al. | 2016-12-29 |
Methods for cell boundary encroachment and semiconductor devices implementing the same
Grant 9,530,795 - Quandt , et al. December 27, 2 | 2016-12-27 |
Enforcement of semiconductor structure regularity for localized transistors and interconnect
Grant 9,530,734 - Kornachuk , et al. December 27, 2 | 2016-12-27 |
Oversized Contacts and Vias in Layout Defined by Linearly Constrained Topology
App 20160358903 - Becker; Scott T. | 2016-12-08 |
Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same
App 20160357897 - Quandt; Jonathan R. ; et al. | 2016-12-08 |
Methods for Multi-Wire Routing and Apparatus Implementing Same
App 20160300007 - Fox; Daryl ; et al. | 2016-10-13 |
Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same
Grant 9,443,947 - Becker , et al. September 13, 2 | 2016-09-13 |
Coarse Grid Design Methods and Structures
App 20160254223 - Smayling; Michael C. ; et al. | 2016-09-01 |
Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same
Grant 9,425,273 - Becker , et al. August 23, 2 | 2016-08-23 |
Methods for cell phasing and placement in dynamic array architecture and implementation of the same
Grant 9,424,387 - Quandt , et al. August 23, 2 | 2016-08-23 |
Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same
Grant 9,425,272 - Becker , et al. August 23, 2 | 2016-08-23 |
Oversized contacts and vias in layout defined by linearly constrained topology
Grant 9,425,145 - Becker August 23, 2 | 2016-08-23 |
Methods for multi-wire routing and apparatus implementing same
Grant 9,390,215 - Fox , et al. July 12, 2 | 2016-07-12 |
Methods for Cell Boundary Encroachment and Semiconductor Devices Implementing the Same
App 20160172375 - Quandt; Jonathan R. ; et al. | 2016-06-16 |
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
App 20160133625 - Smayling; Michael C. ; et al. | 2016-05-12 |
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
App 20160133626 - Smayling; Michael C. ; et al. | 2016-05-12 |
Coarse grid design methods and structures
Grant 9,336,344 - Smayling , et al. May 10, 2 | 2016-05-10 |
Oversized Contacts and Vias in Layout Defined by Linearly Constrained Topology
App 20160118344 - Becker; Scott T. | 2016-04-28 |
Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same
App 20160079276 - Becker; Scott T. ; et al. | 2016-03-17 |
Semiconductor Chip Including Integrated Circuit Including At Least Five Gate Level Conductive Structures Having Particular Spatial and Electrical Relationship and Method for Manufacturing the Same
App 20160079381 - Becker; Scott T. ; et al. | 2016-03-17 |
Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect
App 20160079159 - Kornachuk; Stephen ; et al. | 2016-03-17 |
Methods for cell boundary encroachment and layouts implementing the same
Grant 9,269,702 - Quandt , et al. February 23, 2 | 2016-02-23 |
Solar device charging unit
Grant D748,572 - Becker , et al. February 2, 2 | 2016-02-02 |
Solar device charging unit
Grant D748,573 - Becker , et al. February 2, 2 | 2016-02-02 |
Methods for Linewidth Modification and Apparatus Implementing the Same
App 20160027770 - Smayling; Michael C. ; et al. | 2016-01-28 |
Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
Grant 9,245,081 - Becker , et al. January 26, 2 | 2016-01-26 |
Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
Grant 9,240,413 - Smayling , et al. January 19, 2 | 2016-01-19 |
Oversized contacts and vias in layout defined by linearly constrained topology
Grant 9,230,910 - Becker January 5, 2 | 2016-01-05 |
Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication
App 20150363542 - Reed; Brian ; et al. | 2015-12-17 |
Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
Grant 9,213,792 - Becker , et al. December 15, 2 | 2015-12-15 |
Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods
Grant 9,208,279 - Becker , et al. December 8, 2 | 2015-12-08 |
Enforcement of semiconductor structure regularity for localized transistors and interconnect
Grant 9,202,779 - Kornachuk , et al. December 1, 2 | 2015-12-01 |
Methods for linewidth modification and apparatus implementing the same
Grant 9,159,627 - Smayling , et al. October 13, 2 | 2015-10-13 |
Semiconductor Chip Including Integrated Circuit Including Four Transistors of First Transistor Type and Four Transistors of Second Transistor Type with Electrical Connections Between Various Transistors and Methods for Manufacturing the Same
App 20150270218 - Becker; Scott T. ; et al. | 2015-09-24 |
Semiconductor Chip Including Region Having Integrated Circuit Transistor Gate Electrodes Formed by Various Conductive Structures of Specified Shape and Position and Method for Manufacturing the Same
App 20150249041 - Becker; Scott T. ; et al. | 2015-09-03 |
Methods for controlling microloading variation in semiconductor wafer layout and fabrication
Grant 9,122,832 - Reed , et al. September 1, 2 | 2015-09-01 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications
Grant 9,117,050 - Becker , et al. August 25, 2 | 2015-08-25 |
Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer
Grant 9,081,931 - Becker , et al. July 14, 2 | 2015-07-14 |
Semiconductor Chip Including Digital Logic Circuit Including At Least Six Transistors with Some Transistors Forming Cross-Coupled Transistor Configuration and Associated Methods
App 20150187769 - Becker; Scott T. ; et al. | 2015-07-02 |
Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same
App 20150143321 - Quandt; Jonathan R. ; et al. | 2015-05-21 |
Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
Grant 9,035,359 - Becker , et al. May 19, 2 | 2015-05-19 |
Circuits with linear finfet structures
Grant 9,009,641 - Becker , et al. April 14, 2 | 2015-04-14 |
Methods for cell phasing and placement in dynamic array architecture and implementation of the same
Grant 8,966,424 - Quandt , et al. February 24, 2 | 2015-02-24 |
Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length
Grant 8,952,425 - Becker , et al. February 10, 2 | 2015-02-10 |
Integrated circuit including gate electrode conductive structures with different extension distances beyond contact
Grant 8,946,781 - Becker , et al. February 3, 2 | 2015-02-03 |
Integrated circuit including linear gate electrode structures having different extension distances beyond contact
Grant 08921896 - | 2014-12-30 |
Integrated circuit with gate electrode conductive structures having offset ends
Grant 8,921,897 - Becker , et al. December 30, 2 | 2014-12-30 |
Integrated circuit including linear gate electrode structures having different extension distances beyond contact
Grant 8,921,896 - Becker , et al. December 30, 2 | 2014-12-30 |
Scalable Meta-Data Objects
App 20140380260 - Smayling; Michael C. ; et al. | 2014-12-25 |
Semiconductor Chip Including Digital Logic Circuit Including At Least Nine Linear-Shaped Conductive Structures Collectively Forming Gate Electrodes of At Least Six Transistors with Some Transistors Forming Cross-Coupled Transistor Configuration and Associated Methods
App 20140367799 - Becker; Scott T. ; et al. | 2014-12-18 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature
Grant 8,872,283 - Becker , et al. October 28, 2 | 2014-10-28 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature
Grant 8,866,197 - Becker , et al. October 21, 2 | 2014-10-21 |
Finfet transistor circuit
Grant 8,863,063 - Becker , et al. October 14, 2 | 2014-10-14 |
Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends
Grant 8,853,793 - Becker , et al. October 7, 2 | 2014-10-07 |
Integrated circuit within semiconductor chip including cross-coupled transistor configuration
Grant 8,853,794 - Becker , et al. October 7, 2 | 2014-10-07 |
Semiconductor Chip Including Digital Logic Circuit Including Linear-Shaped Conductive Structures Having Electrical Connection Areas Located Within Inner Region Between Transistors of Different Type and Associated Methods
App 20140291730 - Becker; Scott T. ; et al. | 2014-10-02 |
Semiconductor Chip Including Region Including Linear-Shaped Conductive Structures Forming Gate Electrodes and Having Electrical Connection Areas Arranged Relative to Inner Region Between Transistors of Different Types and Associated Methods
App 20140291731 - Becker; Scott T. ; et al. | 2014-10-02 |
Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures
Grant 8,847,331 - Becker , et al. September 30, 2 | 2014-09-30 |
Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts
Grant 8,847,329 - Becker , et al. September 30, 2 | 2014-09-30 |
Methods for Multi-Wire Routing and Apparatus Implementing Same
App 20140284811 - Fox; Daryl ; et al. | 2014-09-25 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications
Grant 8,835,989 - Becker , et al. September 16, 2 | 2014-09-16 |
Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track
Grant 8,836,045 - Becker , et al. September 16, 2 | 2014-09-16 |
Scalable meta-data objects
Grant 8,839,175 - Smayling , et al. September 16, 2 | 2014-09-16 |
Semiconductor Chip Including Integrated Circuit Defined Within Dynamic Array Section
App 20140246733 - Becker; Scott T. ; et al. | 2014-09-04 |
Integrated circuit with offset line end spacings in linear gate electrode level
Grant 8,823,062 - Becker , et al. September 2, 2 | 2014-09-02 |
Semiconductor Chip Including Region Having Cross-coupled Transistor Configuration With Offset Electrical Connection Areas On Gate Electrode Forming Conductive Structures And At Least Two Different Inner Extension Distances Of Gate Electrode Forming Conductive Struc
App 20140239408 - Becker; Scott T. ; et al. | 2014-08-28 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor
Grant 8,816,402 - Becker , et al. August 26, 2 | 2014-08-26 |
Integrated Circuit Within Semiconductor Chip Including Cross-Coupled Transistor Configuration
App 20140210015 - Becker; Scott T. ; et al. | 2014-07-31 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer
Grant 8,785,979 - Becker , et al. July 22, 2 | 2014-07-22 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer
Grant 8,785,978 - Becker , et al. July 22, 2 | 2014-07-22 |
Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect
App 20140197543 - Kornachuk; Stephen ; et al. | 2014-07-17 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in sin
Grant 8,772,839 - Becker , et al. July 8, 2 | 2014-07-08 |
Integrated Circuit Cell Library for Multiple Patterning
App 20140175565 - Smayling; Michael C. ; et al. | 2014-06-26 |
Methods for multi-wire routing and apparatus implementing same
Grant 8,759,985 - Fox , et al. June 24, 2 | 2014-06-24 |
Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
Grant 8,759,882 - Becker , et al. June 24, 2 | 2014-06-24 |
Methods for Cell Boundary Encroachment and Layouts Implementing the Same
App 20140167117 - Quandt; Jonathan R. ; et al. | 2014-06-19 |
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
App 20140167185 - Smayling; Michael C. ; et al. | 2014-06-19 |
Coarse Grid Design Methods and Structures
App 20140167183 - Smayling; Michael C. ; et al. | 2014-06-19 |
Methods for designing semiconductor device with dynamic array section
Grant 8,756,551 - Becker , et al. June 17, 2 | 2014-06-17 |
Circuitry and Layouts for XOR and XNOR Logic
App 20140159772 - Becker; Scott T. | 2014-06-12 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with outer positioned gate contacts
Grant 8,742,463 - Becker , et al. June 3, 2 | 2014-06-03 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specifications
Grant 8,742,462 - Becker , et al. June 3, 2 | 2014-06-03 |
Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track
Grant 8,735,995 - Becker , et al. May 27, 2 | 2014-05-27 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors
Grant 8,735,944 - Becker , et al. May 27, 2 | 2014-05-27 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels
Grant 8,729,606 - Becker , et al. May 20, 2 | 2014-05-20 |
Cross-coupled transistor circuit including offset inner gate contacts
Grant 8,729,643 - Becker , et al. May 20, 2 | 2014-05-20 |
Enforcement of semiconductor structure regularity for localized transistors and interconnect
Grant 8,701,071 - Kornachuk , et al. April 15, 2 | 2014-04-15 |
Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
Grant 8,680,626 - Smayling , et al. March 25, 2 | 2014-03-25 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within at least nine gate level feature layout channels
Grant 8,680,583 - Becker , et al. March 25, 2 | 2014-03-25 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channels
Grant 8,669,594 - Becker , et al. March 11, 2 | 2014-03-11 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position, alignment, and offset specifications
Grant 8,669,595 - Becker , et al. March 11, 2 | 2014-03-11 |
Integrated circuit cell library for multiple patterning
Grant 8,667,443 - Smayling , et al. March 4, 2 | 2014-03-04 |
Coarse grid design methods and structures
Grant 8,658,542 - Smayling , et al. February 25, 2 | 2014-02-25 |
Methods for cell boundary encroachment and layouts implementing the Same
Grant 8,661,392 - Quandt , et al. February 25, 2 | 2014-02-25 |
Circuitry and layouts for XOR and XNOR logic
Grant 8,653,857 - Becker February 18, 2 | 2014-02-18 |
Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same
App 20140035152 - Quandt; Jonathan R. ; et al. | 2014-02-06 |
Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature
Grant 8,592,872 - Becker , et al. November 26, 2 | 2013-11-26 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
Grant 8,587,034 - Becker , et al. November 19, 2 | 2013-11-19 |
Integrated circuit including cross-coupled trasistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset relationships and electrical connection of cross-coupled transistors through same interconnect layer
Grant 8,581,303 - Becker , et al. November 12, 2 | 2013-11-12 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships
Grant 8,581,304 - Becker , et al. November 12, 2 | 2013-11-12 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode
Grant 8,575,706 - Becker , et al. November 5, 2 | 2013-11-05 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel
Grant 8,569,841 - Becker , et al. October 29, 2 | 2013-10-29 |
Methods for Multi-Wire Routing and Apparatus Implementing Same
App 20130277866 - Fox; Daryl ; et al. | 2013-10-24 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contact
Grant 8,564,071 - Becker , et al. October 22, 2 | 2013-10-22 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level feature
Grant 8,558,322 - Becker , et al. October 15, 2 | 2013-10-15 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conduc
Grant 8,552,508 - Becker , et al. October 8, 2 | 2013-10-08 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors
Grant 8,552,509 - Becker , et al. October 8, 2 | 2013-10-08 |
Optimizing Layout of Irregular Structures in Regular Layout Context
App 20130256898 - Kornachuk; Stephen ; et al. | 2013-10-03 |
Methods for cell phasing and placement in dynamic array architecture and implementation of the same
Grant 8,549,455 - Quandt , et al. October 1, 2 | 2013-10-01 |
Integrated Circuit Including Linear Gate Electrode Structures Having Different Extension Distances Beyond Contact
App 20130249013 - Becker; Scott T. ; et al. | 2013-09-26 |
Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect
App 20130254732 - Kornachuk; Stephen ; et al. | 2013-09-26 |
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Gate Contact Position and Offset Specifications
App 20130214361 - Becker; Scott T. ; et al. | 2013-08-22 |
Integrated Circuit Including Gate Electrode Conductive Structures With Different Extension Distances Beyond Contact
App 20130207165 - Becker; Scott T. ; et al. | 2013-08-15 |
Cross-Coupled Transistor Circuit Defined on Four Gate Electrode Tracks
App 20130207196 - Becker; Scott T. ; et al. | 2013-08-15 |
Cross-Coupled Transistor Circuit Including Offset Inner Gate Contacts
App 20130207197 - Becker; Scott T. ; et al. | 2013-08-15 |
Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track
App 20130207198 - Becker; Scott T. ; et al. | 2013-08-15 |
Finfet Transistor Circuit
App 20130207199 - Becker; Scott T. ; et al. | 2013-08-15 |
Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks
App 20130200464 - Becker; Scott T. ; et al. | 2013-08-08 |
Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks With Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track
App 20130200469 - Becker; Scott T. ; et al. | 2013-08-08 |
Cross-Coupled Transistor Circuit Defined on Two Gate Electrode Tracks
App 20130200463 - Becker; Scott T. ; et al. | 2013-08-08 |
Cross-Coupled Transistor Circuit Defined Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track with At Least Two Non-Inner Positioned Gate Contacts
App 20130200465 - Becker; Scott T. ; et al. | 2013-08-08 |
Integrated Circuit with Gate Electrode Conductive Structures Having Offset Ends
App 20130200436 - Becker; Scott T. ; et al. | 2013-08-08 |
Integrated Circuit with Offset Line End Spacings in Linear Gate Electrode Level
App 20130200462 - Becker; Scott T. ; et al. | 2013-08-08 |
Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track and Gate Node Connection Through Single Interconnect Layer
App 20130193524 - Becker; Scott T. ; et al. | 2013-08-01 |
Integrated Circuit Including At Least Four Linear-Shaped Conductive Structures Having Extending Portions of Different Length
App 20130175639 - Becker; Scott T. ; et al. | 2013-07-11 |
Integrated Circuit Including Gate Electrode Tracks Forming Gate Electrodes of Different Transistor Types and Linear Shaped Conductor Electrically Connecting Gate Electrodes
App 20130168777 - Becker; Scott T. ; et al. | 2013-07-04 |
Integrated Circuit Including Gate Electrode Tracks That Each Form Gate Electrodes of Different Transistor Types With Intervening Non-Gate-Forming Gate Electrode Track
App 20130168778 - Becker; Scott T. ; et al. | 2013-07-04 |
Integrated Circuit Including Gate Electrode Tracks Including Offset End-to-End Spacings
App 20130161760 - Becker; Scott T. ; et al. | 2013-06-27 |
Methods for multi-wire routing and apparatus implementing same
Grant 8,471,391 - Fox , et al. June 25, 2 | 2013-06-25 |
Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Shared Diffusion Regions on Opposite Sides of Two-Transistor-Forming Gate Level Feature
App 20130146988 - Becker; Scott T. ; et al. | 2013-06-13 |
Enforcement of semiconductor structure regularity for localized transistors and interconnect
Grant 8,453,094 - Kornachuk , et al. May 28, 2 | 2013-05-28 |
Coarse Grid Design Methods and Structures
App 20130130511 - Smayling; Michael C. ; et al. | 2013-05-23 |
Circuits With Linear Finfet Structures
App 20130126978 - Becker; Scott T. ; et al. | 2013-05-23 |
Optimizing layout of irregular structures in regular layout context
Grant 8,448,102 - Kornachuk , et al. May 21, 2 | 2013-05-21 |
Integrated Circuit Including Gate Electrode Level Region Including Cross-Coupled Transistors Having Gate Contacts Located Over Inner Portion of Gate Electrode Level Region and Offset Gate Level Feature Line Ends
App 20130119476 - Becker; Scott T. ; et al. | 2013-05-16 |
Semiconductor device with gate level including gate electrode conductors for transistors of first type and transistors of second type with some gate electrode conductors of different length
Grant 8,436,400 - Becker , et al. May 7, 2 | 2013-05-07 |
Integrated circuit including gate electrode level region including cross-coupled transistors having at least one gate contact located over outer portion of gate electrode level region
Grant 8,405,162 - Becker , et al. March 26, 2 | 2013-03-26 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature
Grant 8,405,163 - Becker , et al. March 26, 2 | 2013-03-26 |
Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes
Grant 8,395,224 - Becker , et al. March 12, 2 | 2013-03-12 |
Integrated circuit device including dynamic array section with gate level having linear conductive features on at least three side-by-side lines and uniform line end spacings
Grant 8,356,268 - Becker , et al. January 15, 2 | 2013-01-15 |
Integrated Circuit Including Cross-Coupled Transistors with Two Transistors of Different Type Having Gate Electrodes Formed by Common Gate Level Feature with Shared Diffusion Regions on Opposite Sides of Common Gate Level Feature
App 20120306025 - Becker; Scott T. | 2012-12-06 |
Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same
App 20120273841 - Quandt; Jonathan R. ; et al. | 2012-11-01 |
Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
Grant 8,283,701 - Becker , et al. October 9, 2 | 2012-10-09 |
Methods and systems for process compensation technique acceleration
Grant 8,286,107 - Smayling , et al. October 9, 2 | 2012-10-09 |
Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications
Grant 8,274,099 - Becker September 25, 2 | 2012-09-25 |
Semiconductor device with linearly restricted gate level region including four transistors of first type and four transistors of second type with gate defining shapes of different length
Grant 8,264,009 - Becker , et al. September 11, 2 | 2012-09-11 |
Semiconductor device including transistor forming linear shapes including gate portions and extending portions of different size
Grant 8,264,008 - Becker , et al. September 11, 2 | 2012-09-11 |
Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature
Grant 8,264,049 - Becker September 11, 2 | 2012-09-11 |
Integrated circuit including cross-coupled transistors having two complementary pairs of co-aligned gate electrodes with offset contacting structures positioned between transistors of different type
Grant 8,264,044 - Becker September 11, 2 | 2012-09-11 |
Semiconductor device including at least six transistor forming linear shapes including at least two different gate contact connection distances
Grant 8,264,007 - Becker , et al. September 11, 2 | 2012-09-11 |
Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region with restricted gate contact placement over separating non-diffusion region
Grant 8,258,548 - Becker , et al. September 4, 2 | 2012-09-04 |
Semiconductor device with gate level including transistors of first type and transistors of second type with corresponding gate contact placement restriction
Grant 8,258,551 - Becker , et al. September 4, 2 | 2012-09-04 |
Integrated circuit including cross-coupled transistors with two transistors of different type formed by same gate level structure and two transistors of different type formed by separate gate level structures
Grant 8,258,581 - Becker September 4, 2 | 2012-09-04 |
Semiconductor device including two transistors of first type having gates formed by conductors of different length respectively aligned with two transistors of second type having gates formed by conductors of different length
Grant 8,258,549 - Becker , et al. September 4, 2 | 2012-09-04 |
Semiconductor device including at least six transistor forming linear shapes including at least two transistor forming linear shapes having different extension distances beyond gate contact
Grant 8,258,550 - Becker , et al. September 4, 2 | 2012-09-04 |
Semiconductor device with linearly restricted gate level region including two transistors of first type and two transistors of second type with offset gate contacts
Grant 8,258,547 - Becker , et al. September 4, 2 | 2012-09-04 |
Semiconductor device including at least six transistor forming linear shapes with at least two transistor forming linear shapes having offset ends
Grant 8,258,552 - Becker , et al. September 4, 2 | 2012-09-04 |
Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region and having at least two gate contacts positioned outside separating non-diffusion region
Grant 8,253,173 - Becker , et al. August 28, 2 | 2012-08-28 |
Semiconductor device with linearly restricted gate level region including four serially connected transistors of first type and four serially connected transistors of second type separated by non-diffusion region
Grant 8,253,172 - Becker , et al. August 28, 2 | 2012-08-28 |
Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
Grant 8,247,846 - Becker August 21, 2 | 2012-08-21 |
Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
Grant 8,245,180 - Smayling , et al. August 14, 2 | 2012-08-14 |
Methods for defining and utilizing sub-resolution features in linear topology
Grant 8,225,239 - Reed , et al. July 17, 2 | 2012-07-17 |
Methods for defining contact grid in dynamic array architecture
Grant 8,225,261 - Hong , et al. July 17, 2 | 2012-07-17 |
Integrated circuit including gate electrode level region including at least three linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type
Grant 8,217,428 - Becker , et al. July 10, 2 | 2012-07-10 |
Methods for cell phasing and placement in dynamic array architecture and implementation of the same
Grant 8,214,778 - Quandt , et al. July 3, 2 | 2012-07-03 |
Electrodes of transistors with at least two linear-shaped conductive structures of different length
Grant 8,207,053 - Becker , et al. June 26, 2 | 2012-06-26 |
Integrated circuit including gate electrode level region including at least four linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type
Grant 8,198,656 - Becker , et al. June 12, 2 | 2012-06-12 |
Scalable Meta-Data Objects
App 20120144360 - Smayling; Michael C. ; et al. | 2012-06-07 |
Methods for linewidth modification and apparatus implementing the same
App 20120118854 - Smayling; Michael C. ; et al. | 2012-05-17 |
Integrated circuit including at least three linear-shaped conductive structures of different length each forming gate of different transistor
Grant 8,138,525 - Becker , et al. March 20, 2 | 2012-03-20 |
Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned ends
Grant 8,134,185 - Becker , et al. March 13, 2 | 2012-03-13 |
Integrated circuit including linear-shaped conductive structures that have gate portions and extending portions of different size
Grant 8,134,183 - Becker , et al. March 13, 2 | 2012-03-13 |
Integrated circuit including at least three linear-shaped conductive structures at equal pitch including linear-shaped conductive structure having non-gate portion length greater than gate portion length
Grant 8,134,186 - Becker , et al. March 13, 2 | 2012-03-13 |
Integrated circuit having gate electrode level region including at least four linear-shaped conductive structures with some outer-contacted linear-shaped conductive structures having larger outer extending portion than inner extending portion
Grant 8,134,184 - Becker , et al. March 13, 2 | 2012-03-13 |
Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two linear-shaped conductive structures of different length
Grant 8,129,750 - Becker , et al. March 6, 2 | 2012-03-06 |
Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two different extension distances beyond conductive contacting structures
Grant 8,129,756 - Becker , et al. March 6, 2 | 2012-03-06 |
Integrated circuit including at least six linear-shaped conductive structive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length
Grant 8,129,757 - Becker , et al. March 6, 2 | 2012-03-06 |
Integrated circuit with gate electrode level including at least six linear-shaped conductive structures forming gate electrodes of transisters with at least one pair of linear-shaped conductive structures having offset ends
Grant 8,129,754 - Becker , et al. March 6, 2 | 2012-03-06 |
Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes and including four conductive contacting structures having at least two different connection distances
Grant 8,129,751 - Becker , et al. March 6, 2 | 2012-03-06 |
Integrated circuit including gate electrode level region including at least seven linear-shaped conductive structures of equal length positioned at equal pitch with at least two linear-shaped conductive structures each forming one transistor and having extending portion sized greater than gate porti
Grant 8,129,753 - Becker , et al. March 6, 2 | 2012-03-06 |
Methods, Structures, and Designs for Self-Aligning Local Interconnects used in Integrated Circuits
App 20110278681 - Smayling; Michael C. ; et al. | 2011-11-17 |
Methods for Multi-Wire Routing and Apparatus Implementing Same
App 20110198761 - Fox; Daryl ; et al. | 2011-08-18 |
Integrated Circuit Device Including Dynamic Array Section with Gate Level Having Linear Conductive Features on at Least Three Side-by-Side Lines and Uniform Line End Spacings
App 20110175144 - BECKER; SCOTT T. ; et al. | 2011-07-21 |
Methods for Designing Semiconductor Device with Dynamic Array Section
App 20110161909 - Becker; Scott T. ; et al. | 2011-06-30 |
Semiconductor Device with Dynamic Array Sections Defined and Placed According to Manufacturing Assurance Halos
App 20110108891 - Becker; Scott T. ; et al. | 2011-05-12 |
Semiconductor Device with Dynamic Array Sections Defined and Placed According to Manufacturing Assurance Halos
App 20110108890 - Becker; Scott T. ; et al. | 2011-05-12 |
Methods for Cell Boundary Encroachment and Layouts Implementing the Same
App 20110084312 - Quandt; Jonathan R. ; et al. | 2011-04-14 |
Cell Circuit and Layout with Linear Finfet Structures
App 20100287518 - Becker; Scott T. | 2010-11-11 |
Circuitry and Layouts for XOR and XNOR Logic
App 20100277202 - Becker; Scott T. | 2010-11-04 |
Channelized Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistor Gate Electrode Connections Made Using Linear First Interconnect Level above Gate Electrode Level
App 20100258879 - Becker; Scott T. | 2010-10-14 |
Channelized Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Three Gate Electrode Tracks with Crossing Gate Electrode Connections
App 20100252893 - Becker; Scott T. | 2010-10-07 |
Linear Gate Level Cross-Coupled Transistor Device with Non-Overlapping PMOS Transistors and Non-Overlapping NMOS Transistors Relative to Direction of Gate Electrodes
App 20100252890 - Becker; Scott T. | 2010-10-07 |
Channelized Gate Level Cross-Coupled Transistor Device with Different Width PMOS Transistors and Different Width NMOS Transistors
App 20100252892 - Becker; Scott T. | 2010-10-07 |
Linear Gate Level Cross-Coupled Transistor Device with Equal Width PMOS Transistors and Equal Width NMOS Transistors
App 20100252891 - Becker; Scott T. | 2010-10-07 |
Methods, Structures, and Designs for Self-Aligning Local Interconnects used in Integrated Circuits
App 20100252896 - Smayling; Michael C. ; et al. | 2010-10-07 |
Linear Gate Level Cross-Coupled Transistor Device with Contiguous p-type Diffusion Regions and Contiguous n-type Diffusion Regions
App 20100252889 - Becker; Scott T. | 2010-10-07 |
Channelized Gate Level Cross-Coupled Transistor Device with Non-Overlapping PMOS Transistors and Non-Overlapping NMOS Transistors Relative to Direction of Gate Electrodes
App 20100237429 - Becker; Scott T. | 2010-09-23 |
Channelized Gate Level Cross-Coupled Transistor Device with Equal Width PMOS Transistors and Equal Width NMOS Transistors
App 20100237430 - Becker; Scott T. | 2010-09-23 |
Channelized Gate Level Cross-Coupled Transistor Device with Contiguous p-type Diffusion Regions and Contiguous n-type Diffusion Regions
App 20100237427 - Becker; Scott T. | 2010-09-23 |
Linear Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistor Gate Electrode Connections Made Using Linear First Interconnect Level above Gate Electrode Level
App 20100237426 - Becker; Scott T. | 2010-09-23 |
Channelized Gate Level Cross-Coupled Transistor Device with Non-Overlapping PMOS Transistors and Overlapping NMOS Transistors Relative to Direction of Gate Electrodes
App 20100237428 - Becker; Scott T. | 2010-09-23 |
Linear Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Two Gate Electrode Tracks with Crossing Gate Electrode Connections
App 20100187623 - Becker; Scott T. | 2010-07-29 |
Channelized Gate Level Cross-Coupled Transistor Device with Overlapping PMOS Transistors and Non-Overlapping NMOS Transistors Relative to Direction of Gate Electrodes
App 20100187628 - Becker; Scott T. | 2010-07-29 |
Linear Gate Level Cross-Coupled Transistor Device with Overlapping PMOS Transistors and Overlapping NMOS Transistors Relative to Direction of Gate Electrodes
App 20100187616 - Becker; Scott T. | 2010-07-29 |
Linear Gate Level Cross-Coupled Transistor Device with Overlapping PMOS Transistors and Non-Overlapping NMOS Transistors Relative to Direction of Gate Electrodes
App 20100187618 - Becker; Scott T. | 2010-07-29 |
Linear Gate Level Cross-Coupled Transistor Device with Direct Electrical Connection of Cross-Coupled Transistors to Common Diffusion Node
App 20100187615 - Becker; Scott T. | 2010-07-29 |
Linear Gate Level Cross-Coupled Transistor Device with Constant Gate Electrode Pitch
App 20100187621 - Becker; Scott T. | 2010-07-29 |
Linear Gate Level Cross-Coupled Transistor Device with Connection Between Cross-Coupled Transistor Gate Electrodes Made Utilizing Interconnect Level Other than Gate Electrode Level
App 20100187620 - Becker; Scott T. | 2010-07-29 |
Linear Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Four Gate Electrode Tracks with Crossing Gate Electrode Connections
App 20100187625 - Becker; Scott T. | 2010-07-29 |
Channelized Gate Level Cross-Coupled Transistor Device with Constant Gate Electrode Pitch
App 20100187631 - Becker; Scott T. | 2010-07-29 |
Channelized Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Four Gate Electrode Tracks with Crossing Gate Electrode Connections
App 20100187634 - Becker; Scott T. | 2010-07-29 |
Linear Gate Level Cross-Coupled Transistor Device with Non-Overlapping PMOS Transistors and Overlapping NMOS Transistors Relative to Direction of Gate Electrodes
App 20100187617 - Becker; Scott T. | 2010-07-29 |
Linear Gate Level Cross-Coupled Transistor Device with Complimentary Pairs of Cross-Coupled Transistors Defined by Physically Separate Gate Electrodes within Gate Electrode Level
App 20100187622 - Becker; Scott T. | 2010-07-29 |
Channelized Gate Level Cross-Coupled Transistor Device with Overlapping PMOS Transistors and Overlapping NMOS Transistors Relative to Direction of Gate Electrodes
App 20100187627 - Becker; Scott T. | 2010-07-29 |
Channelized Gate Level Cross-Coupled Transistor Device with Connection Between Cross-Coupled Transistor Gate Electrodes Made Utilizing Interconnect Level Other than Gate Electrode Level
App 20100187630 - Becker; Scott T. | 2010-07-29 |
Linear Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Three Gate Electrode Tracks with Crossing Gate Electrode Connections
App 20100187624 - Becker; Scott T. | 2010-07-29 |
Channelized Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Two Gate Electrode Tracks with Crossing Gate Electrode Connections
App 20100187633 - Becker; Scott T. | 2010-07-29 |
Channelized Gate Level Cross-Coupled Transistor Device with Complimentary Pairs of Cross-Coupled Transistors Defined by Physically Separate Gate Electrodes within Gate Electrode Level
App 20100187632 - Becker; Scott T. | 2010-07-29 |
Linear Gate Level Cross-Coupled Transistor Device with Different Width PMOS Transistors and Different Width NMOS Transistors
App 20100187619 - Becker; Scott T. | 2010-07-29 |
Channelized Gate Level Cross-Coupled Transistor Device with Direct Electrical Connection of Cross-Coupled Transistors to Common Diffusion Node
App 20100187626 - Becker; Scott T. | 2010-07-29 |
Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors
App 20100096671 - Becker; Scott T. ; et al. | 2010-04-22 |
Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors
App 20100032722 - Becker; Scott T. ; et al. | 2010-02-11 |
Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors
App 20100032724 - Becker; Scott T. ; et al. | 2010-02-11 |
Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors
App 20100037194 - Becker; Scott T. ; et al. | 2010-02-11 |
Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions
App 20100032726 - Becker; Scott T. ; et al. | 2010-02-11 |
Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors
App 20100032723 - Becker; Scott T. ; et al. | 2010-02-11 |
Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors and Having Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region
App 20100037195 - Becker; Scott T. ; et al. | 2010-02-11 |
Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors
App 20100032721 - Becker; Scott T. ; et al. | 2010-02-11 |
Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors
App 20100025736 - Becker; Scott T. ; et al. | 2010-02-04 |
Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors
App 20100025733 - Becker; Scott T. ; et al. | 2010-02-04 |
Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors
App 20100025731 - Becker; Scott T. ; et al. | 2010-02-04 |
Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors
App 20100025734 - Becker; Scott T. ; et al. | 2010-02-04 |
Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors
App 20100025735 - Becker; Scott T. ; et al. | 2010-02-04 |
Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors
App 20100025732 - Becker; Scott T. ; et al. | 2010-02-04 |
Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing
App 20100019288 - Becker; Scott T. ; et al. | 2010-01-28 |
Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing
App 20100019286 - Becker; Scott T. ; et al. | 2010-01-28 |
Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors
App 20100019283 - Becker; Scott T. ; et al. | 2010-01-28 |
Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks
App 20100019280 - Becker; Scott T. ; et al. | 2010-01-28 |
Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors
App 20100019284 - Becker; Scott T. ; et al. | 2010-01-28 |
Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors
App 20100019285 - Becker; Scott T. ; et al. | 2010-01-28 |
Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks
App 20100019281 - Becker; Scott T. ; et al. | 2010-01-28 |
Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks
App 20100019282 - Becker; Scott T. ; et al. | 2010-01-28 |
Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors
App 20100023911 - Becker; Scott T. ; et al. | 2010-01-28 |
Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors and Having Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region
App 20100023908 - Becker; Scott T. ; et al. | 2010-01-28 |
Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing
App 20100023906 - Becker; Scott T. ; et al. | 2010-01-28 |
Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region
App 20100023907 - Becker; Scott T. ; et al. | 2010-01-28 |
Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing
App 20100019287 - Becker; Scott T. ; et al. | 2010-01-28 |
Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors
App 20100012983 - Becker; Scott T. ; et al. | 2010-01-21 |
Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions
App 20100012981 - Becker; Scott T. ; et al. | 2010-01-21 |
Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors
App 20100012985 - Becker; Scott T. ; et al. | 2010-01-21 |
Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions
App 20100012982 - Becker; Scott T. ; et al. | 2010-01-21 |
Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors
App 20100012984 - Becker; Scott T. ; et al. | 2010-01-21 |
Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors
App 20100012986 - Becker; Scott T. ; et al. | 2010-01-21 |
Layout of Cell of Semiconductor Device Having Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks
App 20100017767 - Becker; Scott T. ; et al. | 2010-01-21 |
Layout of Cell of Semiconductor Device Having Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors with Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region
App 20100017770 - Becker; Scott T. ; et al. | 2010-01-21 |
Layout of Cell of Semiconductor Device Having Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region
App 20100017768 - Becker; Scott T. ; et al. | 2010-01-21 |
Layout of Cell of Semiconductor Device Having Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors
App 20100017769 - Becker; Scott T. ; et al. | 2010-01-21 |
Layout of Cell of Semiconductor Device Having Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors with Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region
App 20100017772 - Becker; Scott T. ; et al. | 2010-01-21 |
Layout of Cell of Semiconductor Device Having Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors
App 20100017771 - Becker; Scott T. ; et al. | 2010-01-21 |
Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors
App 20100017766 - Becker; Scott T. ; et al. | 2010-01-21 |
Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors
App 20100011328 - Becker; Scott T. ; et al. | 2010-01-14 |
Semiconductor Device Layout Having Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing with Corresponding Non-Symmetric Diffusion Regions
App 20100011330 - Becker; Scott T. ; et al. | 2010-01-14 |
Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors
App 20100006947 - Becker; Scott T. ; et al. | 2010-01-14 |
Semiconductor Device Layout Having Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors
App 20100011333 - Becker; Scott T. ; et al. | 2010-01-14 |
Semiconductor Device Layout Having Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors
App 20100011332 - Becker; Scott T. ; et al. | 2010-01-14 |
Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors
App 20100011327 - Becker; Scott T. ; et al. | 2010-01-14 |
Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors
App 20100011329 - Becker; Scott T. ; et al. | 2010-01-14 |
Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing with Corresponding Non-Symmetric Diffusion Regions
App 20100011331 - Becker; Scott T. ; et al. | 2010-01-14 |
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