U.S. patent application number 15/651801 was filed with the patent office on 2017-11-02 for oversized contacts and vias in layout defined by linearly constrained topology.
The applicant listed for this patent is Tela Innovations, Inc.. Invention is credited to Scott T. Becker.
Application Number | 20170317064 15/651801 |
Document ID | / |
Family ID | 41315405 |
Filed Date | 2017-11-02 |
United States Patent
Application |
20170317064 |
Kind Code |
A1 |
Becker; Scott T. |
November 2, 2017 |
Oversized Contacts and Vias in Layout Defined by Linearly
Constrained Topology
Abstract
A rectangular-shaped interlevel connection layout structure is
defined to electrically connect a first layout structure in a first
chip level with a second layout structure in a second chip level.
The rectangular-shaped interlevel connection layout structure is
defined by an as-drawn cross-section having at least one dimension
larger than a corresponding dimension of either the first layout
structure, the second layout structure, or both the first and
second layout structures. A dimension of the rectangular-shaped
interlevel connection layout structure can exceed a normal maximum
size in one direction in exchange for a reduced size in another
direction. The rectangular-shaped interlevel connection layout
structure can be placed in accordance with a gridpoint of a virtual
grid defined by two perpendicular sets of virtual lines. Also, the
first and/or second layout structures can be spatially oriented
and/or placed in accordance with one or both of the two
perpendicular sets of virtual lines.
Inventors: |
Becker; Scott T.; (Scotts
Valley, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Tela Innovations, Inc. |
Los Gatos |
CA |
US |
|
|
Family ID: |
41315405 |
Appl. No.: |
15/651801 |
Filed: |
July 17, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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15243886 |
Aug 22, 2016 |
9711495 |
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15651801 |
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14987723 |
Jan 4, 2016 |
9425145 |
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15243886 |
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12466335 |
May 14, 2009 |
9230910 |
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14987723 |
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12013342 |
Jan 11, 2008 |
7917879 |
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12466335 |
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12212562 |
Sep 17, 2008 |
7842975 |
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12466335 |
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11683402 |
Mar 7, 2007 |
7446352 |
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12212562 |
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61127727 |
May 14, 2008 |
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60963364 |
Aug 2, 2007 |
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60972394 |
Sep 14, 2007 |
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60781288 |
Mar 9, 2006 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/42376 20130101;
H01L 23/5226 20130101; H01L 27/0203 20130101; H01L 23/528 20130101;
H01L 27/0207 20130101; H01L 2924/0001 20130101; G03F 1/36 20130101;
H01L 2924/0002 20130101; H01L 21/823475 20130101; H01L 27/088
20130101; H01L 23/5283 20130101; H01L 2924/0002 20130101; H01L
21/76816 20130101; H01L 21/76897 20130101; H01L 2924/00 20130101;
H01L 21/823437 20130101; H01L 2924/0002 20130101 |
International
Class: |
H01L 27/02 20060101
H01L027/02; H01L 29/423 20060101 H01L029/423; H01L 27/088 20060101
H01L027/088; H01L 27/02 20060101 H01L027/02; H01L 21/768 20060101
H01L021/768; G03F 1/36 20120101 G03F001/36; H01L 23/522 20060101
H01L023/522; H01L 21/8234 20060101 H01L021/8234; H01L 21/8234
20060101 H01L021/8234; H01L 21/768 20060101 H01L021/768; H01L
23/528 20060101 H01L023/528; H01L 23/528 20060101 H01L023/528 |
Claims
1. A semiconductor device, comprising: a first conductive structure
including a portion having a rectangular-shaped horizontal
cross-section defined by a first size measured in a first direction
and a second size measured in a second direction perpendicular to
the first direction, the first size of the portion of the first
conductive structure greater than the second size of the portion of
the first conductive structure; a second conductive structure
including a portion having a rectangular-shaped horizontal
cross-section defined by a first size measured in the first
direction and a second size measured in the second direction, the
portion of the second conductive structure formed to extend over
the portion of the first conductive structure, the first size of
the portion of the second conductive structure less than the second
size of the portion of the second conductive structure; and an
interlevel connection structure formed to extend between the
portion of the first conductive structure and the portion of the
second conductive structure, the interlevel connection structure
formed to physically contact both the portion of the first
conductive structure and the portion of the second conductive
structure, the interlevel connection structure having a
rectangular-shaped horizontal cross-section defined by a first size
measured in the first direction and a second size measured in the
second direction, the first size of the interlevel connection
structure less than the second size of the interlevel connection
structure, the second size of the interlevel connection structure
greater than the second size of the portion of the first conductive
structure.
2. The semiconductor device as recited in claim 1, wherein the
interlevel connection structure is substantially centered in the
second direction on the portion of the first conductive
structure.
3. The semiconductor device as recited in claim 2, wherein the
interlevel connection structure is substantially centered in the
first direction on the portion of the second conductive
structure.
4. The semiconductor device as recited in claim 1, wherein the
first conductive structure is a gate electrode level structure, and
wherein the second conductive structure is an interconnect level
structure.
5. The semiconductor device as recited in claim 4, wherein the
interlevel connection structure is substantially centered in the
second direction on the portion of the first conductive
structure.
6. The semiconductor device as recited in claim 5, wherein the
interlevel connection structure is substantially centered in the
first direction on the portion of the second conductive
structure.
7. The semiconductor device as recited in claim 1, wherein the
first conductive structure is a first interconnect level structure,
and wherein the second conductive structure is a second
interconnect level structure.
8. The semiconductor device as recited in claim 7, wherein the
interlevel connection structure is substantially centered in the
second direction on the portion of the first conductive
structure.
9. The semiconductor device as recited in claim 8, wherein the
interlevel connection structure is substantially centered in the
first direction on the portion of the second conductive
structure.
10. The semiconductor device as recited in claim 1, wherein the
interlevel connection structure is a first interlevel connection
structure, the semiconductor device including a second interlevel
connection structure having a rectangular-shaped horizontal
cross-section defined by a first size measured in the first
direction and a second size measured in the second direction, the
first size of the second interlevel connection structure
substantially equal to the first size of the first interlevel
connection structure, the second size of the second interlevel
connection structure substantially equal to the second size of the
first interlevel connection structure.
11. The semiconductor device as recited in claim 10, further
comprising: a third conductive structure including a portion having
a rectangular-shaped horizontal cross-section defined by a first
size measured in the first direction and a second size measured in
the second direction, the first size of the portion of the third
conductive structure greater than the second size of the portion of
the third conductive structure; and a fourth conductive structure
including a portion having a rectangular-shaped horizontal
cross-section defined by a first size measured in the first
direction and a second size measured in the second direction, the
portion of the fourth conductive structure formed to extend over
the portion of the third conductive structure, the first size of
the portion of the fourth conductive structure less than the second
size of the portion of the fourth conductive structure, wherein the
second interlevel connection structure is formed to extend between
the portion of the third conductive structure and the portion of
the fourth conductive structure, the second interlevel connection
structure formed to physically contact both the portion of the
third conductive structure and the portion of the fourth conductive
structure.
12. The semiconductor device as recited in claim 11, wherein the
first interlevel connection structure is substantially centered in
the second direction on the portion of the first conductive
structure.
13. The semiconductor device as recited in claim 12, wherein the
first interlevel connection structure is substantially centered in
the first direction on the portion of the second conductive
structure.
14. The semiconductor device as recited in claim 13, wherein the
second interlevel connection structure is substantially centered in
the second direction on the portion of the third conductive
structure.
15. The semiconductor device as recited in claim 14, wherein the
second interlevel connection structure is substantially centered in
the first direction on the portion of the fourth conductive
structure.
16. The semiconductor device as recited in claim 11, wherein the
third conductive structure is formed in a same level of the
semiconductor device as the first conductive structure.
17. The semiconductor device as recited in claim 16, wherein the
fourth conductive structure is formed in a same level of the
semiconductor device as the second conductive structure.
18. The semiconductor device as recited in claim 11, wherein the
first conductive structure is a first gate electrode level
structure, wherein the second conductive structure is a first
interconnect level structure, wherein the third conductive
structure is a second gate electrode level structure, and wherein
the fourth conductive structure is a second interconnect level
structure.
19. The semiconductor device as recited in claim 18, wherein the
first interlevel connection structure is substantially centered in
the second direction on the portion of the first conductive
structure, wherein the first interlevel connection structure is
substantially centered in the first direction on the portion of the
second conductive structure, wherein the second interlevel
connection structure is substantially centered in the second
direction on the portion of the third conductive structure, and
wherein the second interlevel connection structure is substantially
centered in the first direction on the portion of the fourth
conductive structure.
20. The semiconductor device as recited in claim 11, wherein the
first conductive structure is a first interconnect level structure,
wherein the second conductive structure is a second interconnect
level structure, wherein the third conductive structure is a third
interconnect level structure, and wherein the fourth conductive
structure is a fourth interconnect level structure.
21. The semiconductor device as recited in claim 20, wherein the
first interlevel connection structure is substantially centered in
the second direction on the portion of the first conductive
structure, wherein the first interlevel connection structure is
substantially centered in the first direction on the portion of the
second conductive structure, wherein the second interlevel
connection structure is substantially centered in the second
direction on the portion of the third conductive structure, and
wherein the second interlevel connection structure is substantially
centered in the first direction on the portion of the fourth
conductive structure.
Description
CLAIM OF PRIORITY
[0001] This application is a continuation application under 35
U.S.C. 120 of prior U.S. application Ser. No. 15/243,886, filed on
Aug. 22, 2016, which is a continuation application under 35 U.S.C.
120 of prior U.S. application Ser. No. 14/987,723, filed on Jan. 4,
2016, issued as U.S. Pat. No. 9,425,145, on Aug. 23, 2016, which is
a continuation application under 35 U.S.C. 120 of prior U.S.
application Ser. No. 12/466,335, filed on May 14, 2009, issued as
U.S. Pat. No. 9,230,910, on Jan. 5, 2016, which: [0002] claims
priority under 35 U.S.C. 119(e) to U.S. Provisional Patent
Application No. 61/127,727, filed May 14, 2008, and [0003] is a
continuation-in-part application under 35 U.S.C. 120 of prior U.S.
application Ser. No. 12/013,342, filed Jan. 11, 2008, issued as
U.S. Pat. No. 7,917,879, on Mar. 29, 2011, which claims priority
under 35 U.S.C. 119(e) to both U.S. Provisional Patent Application
No. 60/963,364, filed Aug. 2, 2007, and to prior U.S. Provisional
Patent Application No. 60/972,394, filed Sep. 14, 2007, and [0004]
is a continuation-in-part application under 35 U.S.C. 120 of prior
U.S. Application No. 12/212,562, filed Sep. 17, 2008, issued as
U.S. Pat. No. 7,842,975, on Nov. 30, 2010, which is a continuation
application under 35 U.S.C. 120 of prior U.S. application Ser. No.
11/683,402, filed Mar. 7, 2007, issued as U.S. Pat. No. 7,446,352,
on Nov. 4, 2008, which claims priority under 35 U.S.C. 119(e) to
U.S. Provisional Patent Application No. 60/781,288, filed Mar. 9,
2006.
[0005] The disclosure of each above-identified patent application
and patent is incorporated herein by reference in its entirety.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0006] This application is also related to co-pending U.S. patent
application Ser. No. 12/466,341, filed on May 14, 2009, issued as
U.S. Pat. No. 8,247,846, on Aug. 21, 2012. The disclosure of the
above-identified patent application is incorporated herein by
reference in its entirety.
BACKGROUND
[0007] A push for higher performance and smaller die size drives
the semiconductor industry to reduce circuit chip area by
approximately 50% every two years. The chip area reduction provides
an economic benefit for migrating to newer technologies. The 50%
chip area reduction is achieved by reducing the feature sizes
between 25% and 30%. The reduction in feature size is enabled by
improvements in manufacturing equipment and materials. For example,
improvement in the lithographic process has enabled smaller feature
sizes to be achieved, while improvement in chemical mechanical
polishing (CMP) has in-part enabled a higher number of interconnect
layers.
[0008] In the evolution of lithography, as the minimum feature size
approached the wavelength of the light source used to expose the
feature shapes, unintended interactions occurred between
neighboring features. Today minimum feature sizes are being reduced
below 45 nm (nanometers), while the wavelength of the light source
used in the photolithography process remains at 193 nm. The
difference between the minimum feature size and the wavelength of
light used in the photolithography process is defined as the
lithographic gap. As the lithographic gap grows, the resolution
capability of the lithographic process decreases.
[0009] An interference pattern occurs as each shape on the mask
interacts with the light. The interference patterns from
neighboring shapes can create constructive or destructive
interference. In the case of constructive interference, unwanted
shapes may be inadvertently created. In the case of destructive
interference, desired shapes may be inadvertently removed. In
either case, a particular shape is printed in a different manner
than intended, possibly causing a device failure. Correction
methodologies, such as optical proximity correction (OPC), attempt
to predict the impact from neighboring shapes and modify the mask
such that the printed shape is fabricated as desired. The quality
of the light interaction prediction is declining as process
geometries shrink and as the light interactions become more
complex.
[0010] In view of the foregoing, solutions are sought for
improvements in circuit design and layout that can improve
management of lithographic gap issues as technology continues to
progress toward smaller semiconductor device features sizes.
SUMMARY
[0011] In one embodiment, a semiconductor chip layout is disclosed.
The semiconductor chip layout includes a rectangular-shaped
interlevel connection layout structure defined to electrically
connect a first layout structure in a first chip level with a
second layout structure in a second chip level. The
rectangular-shaped interlevel connection layout structure is
defined by an as-drawn cross-section having at least one dimension
larger than a corresponding dimension of either the first layout
structure, the second layout structure, or both the first and
second layout structures.
[0012] In one embodiment, a semiconductor chip is disclosed. The
semiconductor chip includes a rectangular-shaped interlevel
connection structure defined to electrically connect a first
structure in a first chip level with a second structure in a second
chip level. The rectangular-shaped interlevel connection structure
is defined by a horizontal cross-section having at least one
dimension larger than a corresponding dimension of either the first
structure, the second structure, or both the first and second
structures. The horizontal cross-section is defined within a plane
substantially parallel to a substrate of the semiconductor
chip.
[0013] Other aspects and advantages of the invention will become
more apparent from the following detailed description, taken in
conjunction with the accompanying drawings, illustrating by way of
example the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1 is an illustration showing a portion of a layout that
utilizes oversized diffusion contacts and gate contacts, in
accordance with one embodiment of the present invention;
[0015] FIG. 2 is an illustration showing the rectangular contact
layout of FIG. 1 with rectangular diffusion contacts rotated so
that their long dimension extends in the same direction as the long
dimension of the rectangular gate contact, and hence extends in a
direction substantially perpendicular to the centerline of the gate
electrode features, thereby forming rectangular diffusion contacts,
in accordance with one embodiment of the present invention;
[0016] FIG. 3 is an illustration showing the rectangular contact
and linear gate level layout of FIG. 1 defined in conjunction with
a non-linear interconnect level, in accordance with one embodiment
of the present invention;
[0017] FIG. 4 is an illustration showing placement of rectangular
VIAs to make connections between two interconnect levels, in
accordance with one embodiment of the present invention;
[0018] FIG. 5A is an illustration showing a variation of the
exemplary layout of FIG. 4, in which one of the interconnect levels
is defined as a non-linear interconnect level, and another of the
interconnect levels is defined as a linear interconnect level;
[0019] FIG. 5B is an illustration showing a variation of the
exemplary layout of FIG. 5A, in which the non-linear interconnect
level is constrained in the y-direction by the virtual grate, but
is unconstrained in the x-direction;
[0020] FIG. 5C is an illustration showing a variation of the
exemplary layout of FIG. 5A, in which the non-linear interconnect
level is constrained in the x-direction by the virtual grate, but
is unconstrained in the y-direction;
[0021] FIG. 5D is an illustration showing a variation of the
exemplary layout of FIG. 5A, in which the non-linear interconnect
level is constrained in both the x- and y-directions by the virtual
grates; and
[0022] FIG. 6 shows an exemplary chip level layout based on the
linearly constrained topology, in accordance with one embodiment of
the present invention.
DETAILED DESCRIPTION
[0023] In the following description, numerous specific details are
set forth in order to provide a thorough understanding of the
present invention. It will be apparent, however, to one skilled in
the art that the present invention may be practiced without some or
all of these specific details. In other instances, well known
process operations have not been described in detail in order not
to unnecessarily obscure the present invention.
Linearly Constrained Topology
[0024] In deep sub-micron VLSI (Very-Large-Scale Integration)
design, process compensation techniques (PCTs) such as Optical
Proximity Correction (OPC) or sub-resolution feature utilization,
among others, enhance the printing of layout features. PCTs are
easier to develop and implement when the layout is highly regular
and when the quantity and diversity of lithographic interactions
are minimized across the layout.
[0025] The linearly constrained topology represents a semiconductor
device design paradigm capable of enhancing PCT development and
implementation. In the linearly constrained topology, layout
features are defined along a regular-spaced virtual grate (or
regular-spaced virtual grid) in a number of levels of a cell, i.e.,
in a number of levels of a semiconductor chip. The virtual grate is
defined by a set of equally spaced, parallel virtual lines
extending across a portion of a given level in a given chip area.
The virtual grid is defined by a first set of equally spaced,
parallel virtual lines extending across a given level in a given
chip area in a first direction, and by a second set of equally
spaced, parallel virtual lines extending across the given level in
the given chip area in a second direction, where the second
direction is perpendicular to the first direction. A spacing
between adjacent virtual lines of the first set of virtual lines
may or may not be equal to a spacing between adjacent virtual lines
of the second set of virtual lines. In various embodiments, the
virtual grate of a given level can be oriented either substantially
perpendicular of substantially parallel to the virtual grate of an
adjacent level.
[0026] A layout feature is defined as a layout shape that extends
along a virtual line of a virtual grate without contacting a
neighboring layout feature that extends along a different virtual
line of the virtual grate. In one embodiment, a layout feature can
be defined to have a substantially rectangular cross-section when
viewed in an as-drawn state. In another embodiment, a layout
feature can be defined to have a primarily rectangular
cross-section defined by a width and length, with some allowable
variation in width along its length. It should be understood,
however, that in this embodiment, the layout feature of varying
width may not contact a neighboring layout feature that extends
along a different virtual line of the same virtual grate within the
same chip level. For example, some layout features may have one or
more variations in width at any number of locations along their
length, wherein "width" is defined across the substrate in a
direction perpendicular to the virtual line along which the layout
feature is disposed. Such a variation in width may be used to
define a contact head upon which a contact is to connect, or may
serve some other purpose. Additionally, different layout features
within a given chip level can be defined to have the same width or
different widths, so long as the width variation is predictable
from a manufacturing perspective and does not adversely impact the
manufacture of the layout feature or its neighboring layout
features.
[0027] In the linearly constrained topology, variations in a
vertical cross-section shape of an as-fabricated layout feature can
be tolerated to an extent, so long as the variation in the vertical
cross-section shape is predictable from a manufacturing perspective
and does not adversely impact the manufacture of the given layout
feature or its neighboring layout features. In this regard, the
vertical cross-section shape corresponds to a cut of the
as-fabricated layout feature in a plane perpendicular to the
centerline of the layout feature.
[0028] FIG. 6 shows an exemplary chip level layout based on the
linearly constrained topology, in accordance with one embodiment of
the present invention. A number of virtual lines 601, 603, 605,
607, 609 are each defined to extend across the substrate, i.e.,
across the chip level layout of the portion of the chip, in a
single common direction (y direction). Each of layout features 611,
613, 615, 617, 619, 621 is defined to extend along a single virtual
line (601, 603, 605, 605, 607, 609, respectively), without
contacting a neighboring layout feature that extends along a
different virtual grate line. Some layout features, such as 611,
615, 617, 621, are defined to have a substantially rectangular
cross-section when viewed in their as-drawn state. Whereas other
layout features, such as 613 and 619, are defined to have some
variation in width (in x direction) along their length (in y
direction). It should be appreciated that although layout features
613 and 619 vary in width along their length, neither of layout
features 613 and 619 contacts a neighboring layout feature that
extends along a different virtual grate line.
[0029] In one embodiment, each layout feature of a given chip level
is substantially centered upon one of the virtual lines of the
virtual grate associated with the given chip level. A layout
feature is considered to be substantially centered upon a
particular virtual grate line when a deviation in alignment between
of the centerline of the layout feature and the particular virtual
grate line is sufficiently small so as to not reduce a
manufacturing process window from what would be achievable with a
true alignment between of the centerline of the layout feature and
the virtual grate line. In one embodiment, the above-mentioned
manufacturing process window is defined by a lithographic domain of
focus and exposure that yields an acceptable fidelity of the layout
feature. In one embodiment, the fidelity of a layout feature is
defined by a characteristic dimension of the layout feature.
[0030] In another embodiment, some layout features in a given chip
level may not be centered upon a virtual grate line. However, in
this embodiment, the layout features remain parallel to the virtual
lines of the virtual grate, and hence parallel to the other layout
features in the given chip level. Therefore, it should be
understood that the various layout features defined in a layout of
a given chip level are oriented to extend across the given chip
level in a parallel manner.
[0031] In one embodiment, within a given chip level defined
according to the linearly constrained topology, proximate ends of
adjacent, co-aligned layout features may be separated from each
other by a substantially uniform gap. More specifically, adjacent
ends of layout features defined along a common virtual grate line
are separated by an end gap, and such end gaps within the chip
level associated with the virtual grate may be defined to span a
substantially uniform distance. Additionally, in one embodiment, a
size of the end gaps is minimized within a manufacturing process
capability so as to optimize filling of a given chip level with
layout features. In yet another embodiment, the end gaps, i.e.,
line end spacings, span multiple (different) distances.
[0032] Also, in the linearly constrained topology, a portion of a
chip level can be defined to have any number of virtual grate lines
occupied by any number of layout features. In one example, a
portion of a given chip level can be defined such that all lines of
its virtual grate are occupied by at least one layout feature. In
another example, a portion of a given chip level can be defined
such that some lines of its virtual grate are occupied by at least
one layout feature, and other lines of its virtual grate are
vacant, i.e., not occupied by any layout features. Furthermore, in
a portion of a given chip level, any number of successively
adjacent virtual grate lines can be left vacant. Also, the
occupancy versus vacancy of virtual grate lines by layout features
in a portion of a given chip level may be defined according to a
pattern or repeating pattern across the given chip level.
[0033] In a given chip level, some of the layout features may form
functional structures within an integrated circuit, and other
layout features may be non-functional with respect to integrated
circuit operation. It should be understood that each of the layout
features, regardless of function, is defined such that no layout
feature along a given virtual grate line is configured to connect
directly within the same chip level to another layout feature
defined along a different virtual grate line.
[0034] Additionally, within the linearly constrained topology, vias
and contacts are defined to interconnect a number of layout
features in various levels so as to form a number of functional
electronic devices, e.g., transistors, and electronic circuits.
Layout features for the vias and contacts can be aligned to a
virtual grid. In one embodiment, a virtual grid is defined as a
combination of virtual grates associated with a plurality of levels
to which the vias and contacts will connect. Also, in one
embodiment, a combination of virtual grates used to define a
virtual grid can include one or more virtual grates defined
independent from a particular chip level.
[0035] In the linearly constrained topology, a number of layout
features in various chip levels form functional components of an
electronic circuit. Additionally, some of layout features within
various chip levels may be non-functional with respect to an
electronic circuit, but are manufactured nonetheless so as to
reinforce manufacturing of neighboring layout features.
Exemplary Embodiments
[0036] FIG. 1 is an illustration showing a portion of a layout that
utilizes oversized diffusion contacts and gate contacts, in
accordance with one embodiment of the present invention. The layout
of FIG. 1 includes a diffusion region 116 defined within a
substrate. The diffusion region 116 may be of either N-type or
P-type in different embodiments. A linear gate electrode level is
defined over the substrate and diffusion region 116 therein. The
linear gate electrode level is defined to include a number of
linear gate electrode features 114 and 118. Generally speaking,
each linear gate electrode feature (e.g., 114 and 118), regardless
of function, is defined to extend across the linear gate electrode
level in a common direction, such that no direct connection exists
within the linear gate electrode level between any two linear gate
electrode features. In other words, a direct electrical connection
is not made solely within the linear gate electrode level between
separate linear gate electrode features.
[0037] In the exemplary embodiment of FIG. 1, layout features
within the linear gate electrode level are placed according to a
linear gate electrode level virtual grate as defined by virtual
lines 126. The virtual lines 126 are parallel and are spaced at a
gate electrode half-pitch, i.e., at one-half of the
center-to-center pitch 130 between adjacent linear gate electrodes.
Thus, in this embodiment, linear gate electrode features 114 and
118 are placed on every other virtual line 126. It should be
understood, however, that in other embodiments the linear gate
electrode level virtual grate and corresponding linear gate
electrode placements can be defined in different ways, e.g., at
different spacings, so long as the linear gate electrode features
extend in a common direction and are not directly connected to each
other within the linear gate electrode level.
[0038] FIG. 1 also shows an interconnect level defined by
interconnect level features 102, 104, and 106. In one embodiment,
interconnect level features 102, 104, and 106 are defined within a
first interconnect level, i.e., a "metal 1" level. In one
embodiment, the interconnect level features 102, 104, and 106 are
placed according to a virtual grate defined by a number of equally
spaced parallel virtual lines 124. The embodiment of FIG. 1 shows
the interconnect level virtual grate defined to be perpendicular to
the linear gate electrode virtual grate. However, in other
embodiments, the interconnect level virtual grate can be defined to
be parallel to the linear gate electrode virtual grate.
[0039] In one embodiment, gate contacts, diffusion contacts, VIAs,
or a combination thereof can be defined in conjunction with one or
more linear interconnect levels. In this regard, a linear
interconnect level is defined to include linear-shaped interconnect
features that, regardless of function, extend in a common direction
across the linear interconnect level and do not directly connect to
each other by way of a conductive feature defined within the linear
interconnect level. FIG. 1 shows an exemplary embodiment in which
the interconnect features 102, 104, and 106 are defined as part of
a linear interconnect level. However, it should be understood that
gate contacts, diffusion contacts, VIAs, or a combination thereof
can be defined in accordance with the principles disclosed herein
and in conjunction with one or more linear interconnect levels
and/or with one or more non-linear interconnect levels. A
non-linear interconnect level in this regard includes a number of
non-linear interconnect features that extend in more than one
direction across the non-linear interconnect level.
[0040] Linear gate electrode features 114 and 118 electrically
interface with diffusion region 116 to form transistors 122 and
120, respectively. Transistors 122 and 120 share a drain connection
made through a diffusion contact 112, extending between the
diffusion region 116 and the interconnect level feature 106. Also,
transistor 122 has a source connection made through a diffusion
contact 110, extending between the diffusion region 116 and the
interconnect level feature 104. It should be understood that the
layout of FIG. 1 is provided for descriptive purposes and is not
intended to represent a particular electronic circuit or electrical
functionality.
[0041] Each of the diffusion contacts 112 and 110 is of rectangular
shape defined by a longer dimension D2 and a shorter dimension D1.
In one embodiment, the shorter dimension D1 of each diffusion
contact 112 and 110 is the same as a minimum diffusion contact size
allowed by conventional design rule. Setting the shorter dimension
D1 of the rectangular-shaped diffusion contacts 112 and 110 to the
minimum diffusion contact size allowed by conventional design rule
enables minimization of the gate electrode-to-gate electrode pitch
130, and thereby enables the layout to be defined over as small a
chip area as possible.
[0042] It should be understood that the dimension of each
rectangular diffusion contact that extends perpendicularly between
neighboring gate electrodes can be defined so as to avoid adversely
impacting diffusion contact-to-gate electrode spacing. For example,
if an originally defined square diffusion contact is "stretched"
into a rectangular-shaped diffusion contact, the dimension of the
diffusion contact that extends perpendicularly between neighboring
gate electrodes can remain unchanged so as to avoid changing the
original diffusion contact-to-gate electrode spacing. It should be
appreciated that an increase in size of a given diffusion contact
in the direction parallel to the gate electrodes, when going from a
square-shaped diffusion contact to a rectangular-shaped diffusion
contact, should improve diffusion contact yield without requiring
an increase in diffusion region area, i.e., without requiring
utilization of more chip area.
[0043] In one embodiment, a rectangular-shaped diffusion contact is
oriented to have its longer dimension extend perpendicularly to the
interconnect level feature to which it connects. Also, in one
embodiment, a rectangular-shaped diffusion contact is oriented to
have its longer dimension extend parallel to its neighboring gate
electrodes. Additionally, in one embodiment, a rectangular-shaped
diffusion contact is oriented to have its longer dimension extend
both parallel to its neighboring gate electrodes and perpendicular
to the interconnect level feature to which it connects. For
instance, in the exemplary embodiment of FIG. 1, each of the
diffusion contacts 110 and 112 is defined to have its longer
dimension D2 extend both parallel to its neighboring gate
electrodes 114 and 118, and perpendicular to the interconnect level
feature to which it connects, 104 and 106 respectively. In one
variation of this embodiment, the longer dimension of the
rectangular-shaped diffusion contact is defined to overlap at least
one side of the interconnect level feature to which it connects. In
another variation of this embodiment, the longer dimension of the
rectangular-shaped diffusion contact is defined to overlap both
sides of the interconnect level feature to which it connects. In
yet another variation of this embodiment, the longer dimension of
the rectangular-shaped diffusion contact is defined to be about two
times a minimum diffusion contact size allowed by conventional
design rule.
[0044] FIG. 1 also shows a gate contact 108 defined to connect with
both the gate electrode feature 114 and the interconnect level
feature 102. The gate contact 108 is rectangular shaped, i.e.,
oversized, so as to ensure connection with the gate electrode
feature 114. Also, the gate contact 108 is oriented such that its
longer dimension extends in a substantially perpendicular
orientation with respect to the centerline of the gate electrode
feature 114 to which it connects. In one embodiment, the gate
contact 108 is defined to overlap at least one side of the gate
electrode feature 114 to which it connects. In another embodiment,
the gate contact 108 is defined to overlap both sides of the gate
electrode feature 114 to which it connects.
[0045] In one embodiment, such as that shown in FIG. 1, the gate
contact 108 is oriented such that its longer dimension extends in a
substantially parallel orientation with respect to the centerline
of the interconnect level feature 102 to which it connects. In one
variant of this embodiment, the gate contact 108 can be placed in a
substantially centered manner with respect to the centerline of the
interconnect level feature 102 to which it connects. In another
variant of this embodiment, the gate contact 108 can be placed in a
non-centered manner with respect to the centerline of the
interconnect level feature 102 to which it connects, so long as
adequate electrical connection is made between the gate contact 108
and the interconnect level feature 102.
[0046] In one embodiment, each crossing point between virtual
grates associated with different chip levels represents a potential
contact or VIA location. Placement of contacts and/or VIAs
according to crossing points of two or more virtual grates is
defined as placement of contacts and/or VIAs "on-grid." For
example, with regard to FIG. 1, each crossing point between the
virtual lines 126 of the linear gate electrode level and the
virtual lines 124 of the interconnect level represents a potential
diffusion contact or gate contact location. In FIG. 1, each of
diffusion contacts 110 and 112 and gate contact 108 is considered
to be placed on-grid, wherein the grid is defined by the crossing
points of the virtual lines 126 and the virtual lines 124. More
specifically, in FIG. 1, the rectangular diffusion contacts 110 and
112 and gate contact 108 are centered on a virtual grid points
created by the intersection of the interconnect level virtual grate
(124) and the linear gate electrode level virtual grate (126),
where the linear gate level virtual grate (126) includes parallel
virtual lines 126 spaced on the half-pitch of the gate electrode
features 114 and 118. Therefore, in the example of FIG. 1,
placement of contacts 110, 112, and 108 is constrained in two
orthogonal directions by the virtual grates of the linear gate
electrode level and the linear interconnect level.
[0047] It should be understood, however, that some embodiments do
not require placement of contacts and/or VIAs to be constrained in
two orthogonal directions by virtual grates. For example, in one
embodiment, placement of contacts and/or VIAs can be constrained in
a first direction based on one or more virtual grates, and
unconstrained in a second direction orthogonal to the first
direction. For example, with regard to FIG. 1, the diffusion
contacts 110 and 112 and/or the gate contact 108 can be constrained
in the horizontal direction, i.e., x-direction, so as to be
centered on the virtual lines 126, which are spaced on the
half-pitch of the gate electrode features 114 and 118, and can be
unconstrained in the vertical direction, i.e., y-direction, so as
to enable adjustment for design rule compliance. Thus, in one
embodiment, placement of diffusion contacts and/or gate contacts
can be constrained only by the virtual grate of the linear gate
electrode level. In another embodiment, placement of the diffusion
contacts and/or gate contacts can be unconstrained with regard to
virtual grates of various chip levels, so long as the diffusion
contacts and/or gate contacts are placed to make required
connections and are defined within an achievable manufacturing
process window.
[0048] FIG. 2 is an illustration showing the rectangular contact
layout of FIG. 1 with the rectangular diffusion contacts 110 and
112 rotated so that their long dimension (D2) extends in the same
direction as the long dimension (D2) of the rectangular gate
contact 108, and hence extends in a direction substantially
perpendicular to the centerline of the gate electrode features 114
and 118, thereby forming rectangular diffusion contacts 110A and
112A, in accordance with one embodiment of the present invention.
It should be appreciated that for a given gate electrode pitch with
placement of diffusion contacts on the half-pitch of the gate
electrode features, orientation of rectangular diffusion contacts
to have their long dimension (D2) extend perpendicular to the
centerlines of the gate electrodes (such as with diffusion contact
112A of FIG. 2) results in a smaller diffusion contact-to-gate
electrode spacing, relative to the configuration in which the
rectangular diffusion contacts are oriented to have their long
dimension (D2) extend parallel to the gate electrode features (such
as with diffusion contact 112 of FIG. 1). In one embodiment, the
rectangular diffusion contacts 110A and 112A can be self-aligned to
the diffusion level so that a reduction in diffusion
contact-to-gate electrode spacing does not impact, i.e., increase,
the required gate electrode pitch and correspondingly increase an
amount of chip area required for the layout.
[0049] In one embodiment, all rectangular-shaped contacts (both
diffusion and gate contacts) in a layout region are oriented to
have their longer dimension extend in the same direction across the
level of the chip. This embodiment may enable a more efficient OPC
solution for the contacts in the layout region. However, in another
embodiment, each rectangular-shaped contact (diffusion/gate) in a
layout region can be independently oriented to have its longer
dimension extend in either of multiple directions across the level
of the chip without regard to an orientation of other contacts
within the layout region. In this embodiment, placement of contacts
according to a virtual grid within the layout region may enable a
more efficient OPC solution for the contacts in the layout
region.
[0050] FIG. 3 is an illustration showing the rectangular contact
and linear gate level layout of FIG. 1 defined in conjunction with
a non-linear interconnect level, in accordance with one embodiment
of the present invention. Although the interconnect level is shown
to have a corresponding virtual grate defined by virtual lines 124,
the interconnect level features 102A, 104A, and 106A are not
required to extend in a single common direction across the layout
and are not required to be placed according to the virtual grate of
the non-linear interconnect level. In other words, layout features
within the non-linear interconnect level may include bends, such as
those shown in interconnect level features 102A and 106A. Also, in
one embodiment, a portion of the interconnect level features may be
placed according to the virtual grate (124) of the non-linear
interconnect level. However, in another embodiment, the
interconnect level features of the non-linear interconnect level
may be placed without regard to a virtual grate.
[0051] As previously discussed, in one embodiment, placement of the
rectangular diffusion contacts 110 and 112 and gate contact 108 may
be constrained by the virtual grate (126) of the linear gate level.
However, depending on the embodiment, placement of the rectangular
diffusion contacts 110 and 112 and gate contact 108 may or may not
be constrained by the virtual grate (124) of the interconnect
level. Moreover, in the case of the non-linear interconnect level,
placement of the rectangular diffusion contacts 110 and 112 and
gate contact 108 may be constrained only in the x-direction by the
virtual grate (126) of the linear gate level, while unconstrained
in the y-direction so as to enable design rule compliance with
regard to placement of the diffusion contacts 110 and 112 and gate
contact 108 relative to the interconnect level features 102A, 104A,
106A to which they electrically connect.
[0052] FIG. 4 is an illustration showing placement of rectangular
VIAs to make connections between two interconnect levels, in
accordance with one embodiment of the present invention. A first of
the two interconnect levels is defined by interconnect level
features 402, 404, and 406. A second of the two interconnect levels
is defined by interconnect level features 416, 414, and 412. In the
example layout of FIG. 4, each of the two interconnect levels is
defined as a linear interconnect level. More specifically, each of
interconnect level features 402, 404, and 406 is linear-shaped and
is placed so as to be substantially centered upon a respective
virtual line 424 of the virtual grate associated with the
interconnect level. Similarly, each of interconnect level features
416, 414, and 412 is linear-shaped and is placed so as to be
substantially centered upon a respective virtual line 426 of the
virtual grate associated with the interconnect level. As previously
mentioned, a linear interconnect level is defined to include
linear-shaped interconnect features that, regardless of function,
extend in a common direction across the linear interconnect level
and do not directly connect to each other by way of a conductive
feature defined within the linear interconnect level.
[0053] In one embodiment, the interconnect features 402, 404 and
406 in FIG. 4 are defined on a lower interconnect level and the
interconnect features 412, 414 and 416 are defined on an upper
interconnect level. In another embodiment, the interconnect
features 402, 404 and 406 in FIG. 4 are defined on an upper
interconnect level and the interconnect features 412, 414 and 416
are defined on a lower interconnect level. In one embodiment,
virtual grates 424 and 426 are oriented perpendicular to each
other, thereby causing the interconnect features 402, 404, 406, to
extend perpendicular to the interconnect features 412, 414, 416.
Also, it should be understood that the lower and upper interconnect
level orientations can be rotated with respect to each other such
that the lower interconnect level features extend in the
y-direction and the upper interconnect level features extend in the
x-direction, vice-versa.
[0054] In the exemplary embodiment of FIG. 4, a rectangular-shaped
VIA 408 is defined to make an electrical connection between
interconnect features 412 and 402. Also, a rectangular-shaped VIA
410 is defined to make an electrical connection between
interconnect features 416 and 406. Also, in the exemplary
embodiment of FIG. 4, each of the rectangular VIAs 408 and 410 is
centered on a grid point defined by an intersection of a virtual
line of the lower interconnect level virtual grate (424) and a
virtual line of the upper interconnect level virtual grate (426).
Also, in the exemplary embodiment of FIG. 4, each of the
rectangular VIAs 408 and 410 is oriented to have its longer
dimension (D3) extend in the direction of the virtual lines of the
lower interconnect level virtual grate (424). However, it should be
understood that in another embodiment, each of the rectangular VIAs
408 and 410 is oriented to have its longer dimension (D3) extend in
the direction of the virtual lines of the upper interconnect level
virtual grate (426).
[0055] Orientation of the rectangular VIAs can be set to optimize
manufacturability and/or chip area utilization. In one embodiment,
all rectangular VIAs within a given chip level are oriented to have
their respective longer dimension (D3) extend in a common direction
to facilitate optimum OPC (Optical Proximity Correction) and/or
lithography light source optimization. However, in another
embodiment, each rectangular VIA can be independently oriented
within a given chip level, such that multiple VIA orientations are
utilized within the given chip level. In this embodiment, each VIA
orientation may be based on a more localized OPC and/or lithography
light source optimization.
[0056] More specifically, in one embodiment, each
rectangular-shaped VIA in a layout region is oriented to have its
longer dimension extend in the same direction across the level of
the chip. This embodiment may enable a more efficient OPC solution
for the VIAs in the layout region. However, in another embodiment,
each rectangular-shaped VIA in a layout region can be independently
oriented to have its longer dimension extend in either of multiple
directions across the level of the chip without regard to an
orientation of other VIAs within the layout region. In this
embodiment, placement of VIAs according to a virtual grid within
the layout region may enable a more efficient OPC solution for the
VIAs in the layout region. Additionally, in various embodiments,
rectangular-shaped VIAs within a given layout region may be
oriented to have their longer dimension extend perpendicularly with
respect to an interconnect feature in either a lower interconnect
level or a upper interconnect level.
[0057] In one embodiment, the longer dimension (D3) of a given VIA
is defined to be larger than a width of a perpendicularly oriented
interconnect feature to which the given VIA is electrically
connected, wherein the width of the perpendicularly oriented
interconnect feature is measured perpendicular to a centerline of
the perpendicularly oriented interconnect feature. In one
embodiment, the given VIA can be placed to overlap at least one
edge of the perpendicularly oriented interconnect feature to which
the given VIA is electrically connected. In another embodiment, the
given VIA can be placed to overlap both edges of the
perpendicularly oriented interconnect feature to which the given
VIA is electrically connected. In one embodiment, a shorter
dimension (D4) of a given VIA is defined to be set at a minimum VIA
size allowed by conventional design rule. Also, in one embodiment,
the longer dimension (D3) of a given VIA is defined to be about two
times a minimum VIA size allowed by conventional design rule.
[0058] Although the exemplary embodiment of FIG. 4 shows the
interconnect level features 402, 404, 406, 412, 414, 416 and VIAs
408, 410 placed on the virtual grid defined by virtual grates 424
and 426, it should be understood that placement of interconnect
level features and/or VIAs on-grid is not a requirement for all
embodiments. Also, in a given embodiment, a portion of interconnect
level features and/or a portion of VIAs may be placed according to
a virtual grid, with a remaining portion of interconnect level
features and/or VIAs placed without regard to a virtual grid.
Therefore, in one embodiment, rectangular VIA placement can be
constrained in two orthogonal directions (i.e., x- and
y-directions) by respective virtual grates. In another embodiment,
rectangular VIA placement can be constrained in one direction by a
virtual grate and unconstrained in a corresponding orthogonal
direction. In yet another embodiment, rectangular VIA placement can
be unconstrained in two orthogonal directions (i.e., x- and
y-directions).
[0059] FIG. 5A is an illustration showing a variation of the
exemplary layout of FIG. 4, in which one of the interconnect levels
is defined as a non-linear interconnect level, and another of the
interconnect levels is defined as a linear interconnect level, in
accordance with one embodiment of the present invention.
Specifically, a non-linear interconnect level is defined to include
interconnect features 502 and 504. The linear interconnect level is
defined by linear interconnect features 412, 414, and 416 placed
according to virtual grate 426. In one embodiment, the non-linear
interconnect level is defined as a lower level with respect to the
linear interconnect level. In another embodiment, the non-linear
interconnect level is defined as an upper level with respect to the
linear interconnect level.
[0060] In one embodiment, the non-linear interconnect level is
defined in a completely arbitrary manner without regard to any
virtual grate. For example, FIG. 5A shows the interconnect features
502 and 504 defined without regard to either of virtual grates 426
or 424. In one embodiment, placement of each VIA is constrained in
one direction by the virtual grate of the linear interconnect
level, and is unconstrained in a corresponding orthogonal
direction. For example, with regard to FIG. 5A, placement of VIAs
408 and 410 can be constrained in the x-direction by the virtual
grate 426 of the linear interconnect level, but may be
unconstrained in the y-direction.
[0061] In another embodiment, the non-linear interconnect level is
defined in a partially constrained manner according to a virtual
grate. FIG. 5B is an illustration showing a variation of the
exemplary layout of FIG. 5A, in which the non-linear interconnect
level is constrained in the y-direction by the virtual grate 424,
but is unconstrained in the x-direction, in accordance with one
embodiment of the present invention. For example, each of
non-linear interconnect features 506 and 508 includes segments
extending in the x-direction that are constrained in the
y-direction by the virtual grate 424, and also includes segments
extending in the y-direction that are unconstrained with regard to
a virtual grate. In this embodiment, placement of the VIAs 408 and
410 according to the virtual grates 424 and 426 should ensure
connection between the linear interconnect level and the non-linear
interconnect level, when the VIAs 408 and 410 connect with segments
of the non-linear interconnect features 506 and 508 that extend in
the x-direction.
[0062] FIG. 5C is an illustration showing a variation of the
exemplary layout of FIG. 5A, in which the non-linear interconnect
level is constrained in the x-direction by the virtual grate 426,
but is unconstrained in the y-direction, in accordance with one
embodiment of the present invention. For example, each of
non-linear interconnect features 510 and 512 includes segments
extending in the y-direction that are constrained in the
x-direction by the virtual grate 426, and also includes segments
extending in the x-direction that are unconstrained with regard to
a virtual grate. In this embodiment, placement of the VIAs 408 and
410 according to the virtual grates 424 and 426 should ensure
connection between the linear interconnect level and the non-linear
interconnect level, when the VIAs 408 and 410 connect with segments
of the non-linear interconnect features 510 and 512 that extend in
the y-direction.
[0063] In another embodiment, the non-linear interconnect level is
defined in a fully constrained manner according to a pair of
orthogonally related virtual grates. FIG. 5D is an illustration
showing a variation of the exemplary layout of FIG. 5A, in which
the non-linear interconnect level is constrained in both the x- and
y-directions by the virtual grates 426 and 424, respectively, in
accordance with one embodiment of the present invention. For
example, each of non-linear interconnect features 514 and 516
includes segments extending in the x-direction that are constrained
in the y-direction by the virtual grate 424, and also includes
segments extending in the y-direction that are constrained in the
x-direction by the virtual grate 426. In this embodiment, placement
of a given VIA according to the pair of orthogonally related
virtual grates should ensure connection between the linear
interconnect level and the non-linear interconnect level, so long
as a non-linear interconnect level feature is defined to extend
over the given VIA.
[0064] Although the foregoing exemplary embodiments have been
described as implementing rectangular-shaped diffusion contacts,
gate contacts, and VIAs, it should be understood that other
embodiments may utilize oversized square-shaped diffusion contacts,
gate contacts, VIAs, or a combination thereof. Placement of the
oversized square-shaped contacts and/or VIAs can be constrained by
one or more virtual grates, just as described for the
rectangular-shaped contacts and/or VIAs. Additionally, it should be
understood that the oversized square-shaped contacts and/or VIAs
can be oversized with regard to the size of corresponding contacts
and/or VIAs as allowed by conventional design rule.
[0065] As discussed with regard to FIGS. 1 through 5D, each of the
example contacts and vias represents a rectangular-shaped
interlevel connection layout structure defined to electrically
connect a first layout structure in a first chip level with a
second layout structure in a second chip level. The
rectangular-shaped interlevel connection layout structure is
defined by an as-drawn cross-section having at least one dimension
larger than a corresponding dimension of at least one of the first
layout structure and the second layout structure. For example, in
FIG. 1, the diffusion contact 110 has a dimension D2 larger than
the corresponding dimension of interconnect level feature 104. Also
in FIG. 1, the gate contact 108 has a dimension D2 larger than the
corresponding dimension of gate electrode feature 114.
Additionally, by way of example, FIG. 4 shows that the VIA 408 has
a dimension D3 larger than the corresponding dimension of
interconnect feature 412.
[0066] In one embodiment, a smallest dimension of the as-drawn
cross-section of the rectangular-shaped interlevel connection
layout structure is minimally sized within design rule requirements
pertaining to the semiconductor chip layout. Also, in one
embodiment, a smallest dimension of the as-drawn cross-section of
the rectangular-shaped interlevel connection layout structure is
sized substantially equal to a minimum transistor channel length
allowed by design rule requirements pertaining to the semiconductor
chip layout. Additionally, in one embodiment, a largest dimension
of the as-drawn cross-section of the rectangular-shaped interlevel
connection layout structure is sized to exceed a normal maximum
size allowed by design rule requirements pertaining to the
semiconductor chip layout. In one embodiment, the as-drawn
cross-section of the rectangular-shaped interlevel connection
layout structure is square-shaped such that each side of the
as-drawn cross-section is the same size and is larger than at least
one dimension of at least one of the first layout structure and the
second layout structure to which the rectangular-shaped interlevel
connection layout structure connects.
[0067] In one embodiment, the rectangular-shaped interlevel
connection layout structure, e.g., contact or via, is placed in a
substantially centered manner with respect to a gridpoint of a
virtual grid. The virtual grid is defined by a first set of virtual
lines extending in a first direction and by a second set of virtual
lines extending in a second direction perpendicular to the first
direction. The gridpoint of the virtual grid is defined by an
intersection between respective virtual lines of the first and
second sets of virtual lines. For example, FIG. 1 shows the virtual
grid defined by the first set of virtual line 126 and by the second
set of virtual lines 124. The gate contact 108 is placed in a
substantially centered manner with respect to a gridpoint defined
by an intersection between respective virtual lines of the first
and second sets of virtual lines 126 and 124, respectively.
[0068] In one embodiment, one or both of the first and second
layout structures to which the rectangular-shaped interlevel
connection layout structure is connected is defined to include one
or more linear segments respectively centered upon one or more of
virtual lines of the virtual grid. Also, one or both of the first
and second layout structures to which the rectangular-shaped
interlevel connection layout structure is connected can be defined
by multiple linear segments substantially centered upon multiple
virtual lines of the virtual grid, and by one or more orthogonal
segments extending perpendicularly between the multiple linear
segments. In one embodiment, each of the multiple linear segments
and one or more orthogonal segments of the first and/or second
layout structures has a substantially rectangular-shaped
cross-section when viewed in an as-drawn state. Additionally, in
one embodiment, the one or more orthogonal segments of the first
and/or second layout structures is substantially centered upon a
given virtual line of the virtual grid.
[0069] It should be understood that the oversized contacts and/or
vias as disclosed herein can be defined in a layout that is stored
in a tangible form, such as in a digital format on a computer
readable medium. For example, the layout including the oversized
contacts and/or vias as disclosed herein can be stored in a layout
data file of one or more cells, selectable from one or more
libraries of cells. The layout data file can be formatted as a GDS
II (Graphic Data System) database file, an OASIS (Open Artwork
System Interchange Standard) database file, or any other type of
data file format suitable for storing and communicating
semiconductor device layouts. Also, multi-level layouts utilizing
the oversized contacts and/or vias can be included within a
multi-level layout of a larger semiconductor device. The
multi-level layout of the larger semiconductor device can also be
stored in the form of a layout data file, such as those identified
above.
[0070] Also, the invention described herein can be embodied as
computer readable code on a computer readable medium. For example,
the computer readable code can include the layout data file within
which one or more layouts including the oversized contacts and/or
vias are stored. The computer readable code can also include
program instructions for selecting one or more layout libraries
and/or cells that include a layout having oversized contacts and/or
vias defined therein. The layout libraries and/or cells can also be
stored in a digital format on a computer readable medium.
[0071] The computer readable medium mentioned herein is any data
storage device that can store data which can thereafter be read by
a computer system. Examples of the computer readable medium include
hard drives, network attached storage (NAS), read-only memory,
random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and
other optical and non-optical data storage devices. The computer
readable medium can also be distributed over a network of coupled
computer systems so that the computer readable code is stored and
executed in a distributed fashion.
[0072] Any of the operations described herein that form part of the
invention are useful machine operations. The invention also relates
to a device or an apparatus for performing these operations. The
apparatus may be specially constructed for the required purpose,
such as a special purpose computer. When defined as a special
purpose computer, the computer can also perform other processing,
program execution or routines that are not part of the special
purpose, while still being capable of operating for the special
purpose. Alternatively, the operations may be processed by a
general purpose computer selectively activated or configured by one
or more computer programs stored in the computer memory, cache, or
obtained over a network. When data is obtained over a network the
data maybe processed by other computers on the network, e.g., a
cloud of computing resources.
[0073] The embodiments of the present invention can also be defined
as a machine that transforms data from one state to another state.
The data may represent an article, that can be represented as an
electronic signal and electronically manipulate data. The
transformed data can, in some cases, be visually depicted on a
display, representing the physical object that results from the
transformation of data. The transformed data can be saved to
storage generally, or in particular formats that enable the
construction or depiction of a physical and tangible object. In
some embodiments, the manipulation can be performed by a processor.
In such an example, the processor thus transforms the data from one
thing to another. Still further, the methods can be processed by
one or more machines or processors that can be connected over a
network. Each machine can transform data from one state or thing to
another, and can also process data, save data to storage, transmit
data over a network, display the result, or communicate the result
to another machine.
[0074] It should be further understood that the oversized contacts
and/or vias as disclosed herein can be manufactured as part of a
semiconductor device or chip. In the fabrication of semiconductor
devices such as integrated circuits, memory cells, and the like, a
series of manufacturing operations are performed to define features
on a semiconductor wafer. The wafer includes integrated circuit
devices in the form of multi-level structures defined on a silicon
substrate. At a substrate level, transistor devices with diffusion
regions are formed. In subsequent levels, interconnect
metallization lines are patterned and electrically connected to the
transistor devices to define a desired integrated circuit device.
Also, patterned conductive layers are insulated from other
conductive layers by dielectric materials.
[0075] While this invention has been described in terms of several
embodiments, it will be appreciated that those skilled in the art
upon reading the preceding specifications and studying the drawings
will realize various alterations, additions, permutations and
equivalents thereof. Therefore, it is intended that the present
invention includes all such alterations, additions, permutations,
and equivalents as fall within the true spirit and scope of the
invention.
* * * * *