U.S. patent application number 15/646825 was filed with the patent office on 2017-10-26 for methods for linewidth modification and apparatus implementing the same.
The applicant listed for this patent is Tela Innovations, Inc.. Invention is credited to Scott T. Becker, Michael C. Smayling.
Application Number | 20170309609 15/646825 |
Document ID | / |
Family ID | 46046862 |
Filed Date | 2017-10-26 |
United States Patent
Application |
20170309609 |
Kind Code |
A1 |
Smayling; Michael C. ; et
al. |
October 26, 2017 |
Methods for Linewidth Modification and Apparatus Implementing the
Same
Abstract
A linear-shaped core structure of a first material is formed on
an underlying material. A layer of a second material is conformally
deposited over the linear-shaped core structure and exposed
portions of the underlying material. The layer of the second
material is etched so as to leave a filament of the second material
on each sidewall of the linear-shaped core structure, and so as to
remove the second material from the underlying material. The
linear-shaped core structure of the first material is removed so as
to leave each filament of the second material on the underlying
material. Each filament of the second material provides a mask for
etching the underlying material. Each filament of the second
material can be selectively etched further to adjust its size, and
to correspondingly adjust a size of a feature to be formed in the
underlying material.
Inventors: |
Smayling; Michael C.;
(Fremont, CA) ; Becker; Scott T.; (Scotts Valley,
CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Tela Innovations, Inc. |
Los Gatos |
CA |
US |
|
|
Family ID: |
46046862 |
Appl. No.: |
15/646825 |
Filed: |
July 11, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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14875570 |
Oct 5, 2015 |
9704845 |
|
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15646825 |
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13373470 |
Nov 14, 2011 |
9159627 |
|
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14875570 |
|
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61413284 |
Nov 12, 2010 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 23/528 20130101;
H01L 21/0337 20130101; H01L 21/823456 20130101; H01L 2924/00
20130101; H01L 2924/0002 20130101; H01L 21/0338 20130101; H01L
29/42376 20130101; H01L 21/32139 20130101; H01L 2924/0002 20130101;
H01L 27/0207 20130101 |
International
Class: |
H01L 27/02 20060101
H01L027/02; H01L 29/423 20060101 H01L029/423; H01L 21/033 20060101
H01L021/033; H01L 21/033 20060101 H01L021/033; H01L 21/3213
20060101 H01L021/3213; H01L 21/8234 20060101 H01L021/8234; H01L
23/528 20060101 H01L023/528 |
Claims
1. An integrated circuit, comprising: a first linear-shaped
conductive structure formed to extend lengthwise in a first
direction, the first linear-shaped conductive structure having a
first width size as measured in a second direction perpendicular to
the first direction; a second linear-shaped conductive structure
formed to extend lengthwise in the first direction, the second
linear-shaped conductive structure having a second width size as
measured in the second direction perpendicular to the first
direction, the second width size less than the first width size,
the second linear-shaped conductive structure spaced apart from the
first linear-shaped conductive structure, wherein a length of the
second linear-shaped conductive structure as measured in the first
direction is less than a length of the first linear-shaped
conductive structure as measured in the first direction; and a
third linear-shaped conductive structure formed to extend
lengthwise in the first direction, the third linear-shaped
conductive structure having a third width size as measured in the
second direction perpendicular to the first direction, the third
width size less than the second width size, the third linear-shaped
conductive structure spaced apart from either the first
linear-shaped conductive structure, or the second linear-shaped
conductive structure, or both the first and second linear-shaped
conductive structures.
Description
CLAIM OF PRIORITY
[0001] This application is a continuation application under 35
U.S.C. 120 of prior U.S. application Ser. No. 14/875,570, filed
Oct. 5, 2015, issued as U.S. Pat. No. 9,704,845, on Jul. 11, 2017,
which is a continuation application under 35 U.S.C. 120 of prior
U.S. application Ser. No. 13/373,470, filed Nov. 14, 2011, issued
as U.S. Pat. No. 9,159,627, on Oct. 13, 2015, which claims priority
under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No.
61/413,284, filed Nov. 12, 2010. The disclosure of each
above-identified patent application is incorporated herein by
reference in its entirety.
BACKGROUND
[0002] A push for higher performance and smaller die size drives
the semiconductor industry to reduce circuit chip area by
approximately 50% every two years. The chip area reduction provides
an economic benefit for migrating to newer technologies. The 50%
chip area reduction is achieved by reducing the feature sizes
between 25% and 30%. The reduction in feature size is enabled by
improvements in manufacturing equipment and materials. For example,
improvement in the lithographic process has enabled smaller feature
sizes to be achieved, while improvement in chemical mechanical
polishing (CMP) has in-part enabled a higher number of interconnect
layers.
[0003] In the evolution of lithography, as the minimum feature size
approached the wavelength of the light source used to expose the
feature shapes, unintended interactions occurred between
neighboring features. Today minimum feature sizes are being reduced
below 45 nm (nanometers), while the wavelength of the light source
used in the photolithography process remains at 193 nm. The
difference between the minimum feature size and the wavelength of
light used in the photolithography process is defined as the
lithographic gap. As the lithographic gap grows, the resolution
capability of the lithographic process decreases.
[0004] An interference pattern occurs as each shape on the mask
interacts with the light. The interference patterns from
neighboring shapes can create constructive or destructive
interference. In the case of constructive interference, unwanted
shapes may be inadvertently created. In the case of destructive
interference, desired shapes may be inadvertently removed. In
either case, a particular shape is printed in a different manner
than intended, possibly causing a device failure. Correction
methodologies, such as optical proximity correction (OPC), attempt
to predict the impact from neighboring shapes and modify the mask
such that the printed shape is fabricated as desired. The quality
of the light interaction prediction is declining as process
geometries shrink and as the light interactions become more
complex.
[0005] In view of the foregoing, solutions are sought for
improvements in integrated circuit design, layout, and fabrication
that can improve management of lithographic gap issues as
technology continues to progress toward smaller semiconductor
device feature sizes.
SUMMARY
[0006] In one embodiment, a method is disclosed for fabricating a
mask for etching of linear-shaped structures for an integrated
circuit. The method includes forming a plurality of linear-shaped
core structures of a first material on an underlying material. The
method also includes conformally depositing a layer of a second
material over each of the linear-shaped core structures and exposed
portions of the underlying material. The method also includes
etching the layer of the second material so as to leave a filament
of the second material on each sidewall of each of the
linear-shaped core structures, and so as to remove the second
material from the underlying material. The method also includes
depositing a third material over each filament of the second
material. The method also includes removing a portion of the third
material to as to expose one or more of the filaments of the second
material. The method also includes etching the exposed filaments of
the second material so as to leave thinner filaments of the second
material. The method also includes removing the third material and
the plurality of linear-shaped core structures of the first
material so as to leave the filaments of the second material on the
underlying material, whereby the filaments of the second material
provides a mask for etching the underlying material.
[0007] In one embodiment, a method is disclosed for fabricating
linear-shaped conductive structures for an integrated circuit. The
method includes depositing a layer of a conductive material over a
substrate. The method also includes forming a plurality of
linear-shaped core structures of a first material on the conductive
material. The method also includes conformally depositing a layer
of a second material over each of the linear-shaped core structures
and exposed portions of the conductive material. The method also
includes etching the layer of the second material so as to leave a
filament of the second material on each sidewall of each of the
linear-shaped core structures and so as to remove the second
material from the conductive material. The method also includes
depositing a third material over each filament of the second
material. The method also includes removing a portion of the third
material to as to expose one or more of the filaments of the second
material. The method also includes etching the exposed filaments of
the second material so as to leave thinner filaments of the second
material. The method also includes removing the third material and
the plurality of linear-shaped core structures of the first
material so as to leave the filaments of the second material on the
conductive material, whereby the filaments of the second material
provide a mask for etching the conductive material. The method also
includes etching the conductive material so as to leave
linear-shaped portions of the conductive material beneath the
filaments of the second material. The method also includes removing
the filaments of the second material from the linear-shaped
portions of the conductive material.
[0008] Other aspects and advantages of the invention will become
more apparent from the following detailed description, taken in
conjunction with the accompanying drawings, illustrating by way of
example the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 shows a plan view of the gate electrode layer of an
example logic circuit with uniform conductive segment line-widths,
in accordance with an example embodiment.
[0010] FIG. 2 shows a plan view of the gate electrode layer of an
example logic circuit with two different conductive segment
line-widths, and with conductive segment line-widths grouped for
the same optical resolution as a core pattern, in accordance with
an example embodiment.
[0011] FIG. 3 shows a plan view of the gate electrode layer of an
example logic circuit with two different conductive segment
line-widths, and with line-widths patterned with a resolution
higher than used for the core pattern, in accordance with an
example embodiment.
[0012] FIG. 4 shows a plan view of the gate electrode layer of an
example logic circuit with three different conductive segment
line-widths, and with line-widths grouped for the same optical
resolution as a core pattern, in accordance with an example
embodiment.
[0013] FIG. 5A shows a plan view, i.e., top view, of a core pattern
for use in forming a gate electrode layer of an example logic
circuit, in accordance with an example embodiment.
[0014] FIG. 5B shows the plan view of the core pattern of FIG. 5A
following dielectric deposition and etching processes to form
sidewall filaments 531, 533, and 535, in accordance with an example
embodiment.
[0015] FIG. 5C shows the plan view of the sidewall filaments 531,
533, 535 of FIG. 5B after the core pattern, including core
structures 521, 523, and 525, has been removed, in accordance with
an example embodiment.
[0016] FIG. 5D shows a plan view of a cut pattern overlying the
sidewall filaments 531, 533, 535 of FIG. 5C, prior to etching the
sidewall filaments 531, 533, 535 in the cut pattern areas 541, 543,
545, and 547, in accordance with an example embodiment.
[0017] FIG. 5E shows the plan view of the sidewall filaments 531,
533, 535 of FIG. 5D after they have been etched within the cut
pattern areas 541, 543, 545, and 547 as shown in FIG. 5D, in
accordance with an example embodiment.
[0018] FIG. 6A shows a plan view, i.e., top view, of a core pattern
that includes core structures 621, 623, and 625, surrounded by
sidewall filaments 631, 633, and 635, respectively, in accordance
with an example embodiment.
[0019] FIG. 6B shows the plan view of FIG. 6A after the etching
process to reduce the width of the sidewall filament 633 that is
exposed through the mask opening 641, in accordance with an example
embodiment.
[0020] FIG. 6C shows the plan view of FIG. 6B after the first
etching process to reduce the width of the sidewall filament 633,
in accordance with an example embodiment.
[0021] FIG. 6D shows the plan view of FIG. 6C after the second
etching process to reduce the width of the sidewall filament 631,
in accordance with an example embodiment.
[0022] FIG. 7A shows vertical cross-section view of a core pattern
for use in forming a gate electrode layer of an example logic
circuit, in accordance with an example embodiment.
[0023] FIG. 7B shows the cross-section view of FIG. 7A, after
deposition of a material layer 721 which will later become sidewall
filaments, in accordance with an example embodiment.
[0024] FIG. 7C shows the cross-section view of FIG. 7B, after the
material layer 721 has been etched to transform it into sidewall
filaments 731, 732, 733, 734, 735, 736 formed along sides of the
core structures 711, 713, 715, in accordance with an example
embodiment.
[0025] FIG. 7D shows the cross-section view of FIG. 7C with a mask
material 706 deposited to cover the core structures 711, 715, and
their sidewall filaments 731, 732, 735, 736, and leave the core
structure 713 and its sidewall filaments 733, 734 exposed, in
accordance with an example embodiment.
[0026] FIG. 7E shows the cross-section view of FIG. 7C, after the
sidewall filaments 733 and 734 have been selectively etched to
reduce their width sizes, in accordance with an example
embodiment.
[0027] FIG. 7F shows the cross-section view of FIG. 7E with a mask
material 706 deposited to cover the core structures 713, 715, and
their sidewall filaments 733, 734, 735, 736, and leave the core
structure 711 and its sidewall filaments 731, 732 exposed, in
accordance with an example embodiment.
[0028] FIG. 7G shows the cross-section view of FIG. 7E, after the
sidewall filaments 731 and 732 have been selectively etched to
reduce their width sizes, in accordance with an example
embodiment.
[0029] FIG. 7H shows the cross-section view of FIG. 7G, after the
core structures 711, 713, 715 have been removed, in accordance with
an example embodiment.
[0030] FIG. 7I shows the cross-section view of FIG. 7H, after the
underlying gate conductor material layer 705 has been etched in
regions between the sidewall filaments 731, 732, 733, 734, 735,
736, in accordance with an example embodiment.
[0031] FIG. 7J shows the cross-section view of FIG. 7I, after the
sidewall filaments 731, 732, 733, 734, 735, 736 have been removed,
thereby leaving the etched gate conductor material layer 705, in
accordance with an example embodiment.
[0032] FIG. 8A shows a vertical cross-section view of a core
structure 803 formed on a conductive material layer 801 (e.g., gate
conductor material layer 801), in accordance with an example
embodiment.
[0033] FIG. 8B shows the cross-section view of FIG. 8A, after an
etching process which leaves a full-width sidewall filament 850, in
accordance with an example embodiment.
[0034] FIG. 8C shows the cross-section view of FIG. 8B, after the
core structure 803 has been removed, and the sidewall filaments 850
have been used as a mask for etching the underlying gate conductor
material layer 801, in accordance with an example embodiment.
[0035] FIG. 8D shows the cross-section of FIG. 8B following a
further etching process to obtain sidewall filaments 853 of reduced
width 873, relative to the sidewall filaments 850 of FIG. 8B, in
accordance with an example embodiment.
[0036] FIG. 8E shows the cross-section view of FIG. 8D, after the
core structure 803 and outside sidewall filament layer 815 have
been removed, and the sidewall filaments 853 have been used as a
mask for etching the underlying gate conductor material layer 801,
in accordance with an example embodiment.
[0037] FIG. 8F shows the cross-section of FIG. 8D following a
further etching process to reduce the sidewall filament 855 width
875 to essentially the thickness of the first deposited sidewall
filament material layer 811, in accordance with an example
embodiment.
[0038] FIG. 8G shows the cross-section view of FIG. 8F, after the
core structure 803 and sidewall filament layer 813 have been
removed, and the sidewall filaments 855 have been used as a mask
for etching the underlying gate conductor material layer 801, in
accordance with an example embodiment.
[0039] FIG. 9A shows a vertical cross-section view of a core
structure 903 formed on a conductive material layer 901 (e.g., gate
conductor material layer 901), in accordance with an example
embodiment.
[0040] FIG. 9B shows the cross-section view of FIG. 9A, after an
etching process which leaves sidewall filaments 911 and 912 of
width size 950, in accordance with an example embodiment.
[0041] FIG. 9C shows the cross-section view of FIG. 9B, after the
core structure 903 has been removed, and the sidewall filaments
911, 912 have been used as a mask for etching the underlying gate
conductor material layer 901, in accordance with an example
embodiment.
[0042] FIG. 9D shows the cross-section of FIG. 9B, after further
etching of the sidewall filaments 911 and 912 to obtain sidewall
filaments 921 and 922 of reduced width size 953, in accordance with
an example embodiment.
[0043] FIG. 9E shows the cross-section view of FIG. 9D, after the
core structure 903 has been removed, and the sidewall filaments
921, 922 have been used as a mask for etching the underlying gate
conductor material layer 901, in accordance with an example
embodiment.
[0044] FIG. 9F shows the cross-section of FIG. 9D, after further
etching of the sidewall filaments 921 and 922 to obtain sidewall
filaments 931 and 932 of even further reduced width size 955, in
accordance with an example embodiment.
[0045] FIG. 9G shows the cross-section view of FIG. 9F, after the
core structure 903 has been removed, and the sidewall filaments
931, 932 have been used as a mask for etching the underlying gate
conductor material layer 901, in accordance with an example
embodiment.
[0046] FIG. 10 shows a plan view of the gate electrode layer of a
portion of an example SRAM cell with gate electrode layer
conductive segments (1001, 1003, 1005, 1007, 1009, 1011, 1013,
1015) of uniform width size, as measured in the direction (x), in
accordance with an example embodiment.
[0047] FIG. 11 shows a plan view of the gate electrode layer of a
portion of an example SRAM cell with gate electrode layer
conductive segments (1101, 1103, 1105, 1107, 1109, 1111, 1113,
1115) of non-uniform width size, as measured in the direction (x),
in accordance with an example embodiment.
[0048] FIG. 12 shows a flowchart of a method for fabricating a mask
for etching of linear-shaped structures for an integrated circuit,
in accordance with one embodiment of the present invention.
[0049] FIG. 13 shows a flowchart of a method for fabricating a mask
for etching of linear-shaped structures for an integrated circuit,
in accordance with one embodiment of the present invention.
[0050] FIG. 14 shows a flowchart of a method for fabricating
linear-shaped conductive structures for an integrated circuit, in
accordance with one embodiment of the present invention.
DETAILED DESCRIPTION
[0051] In the following description, numerous specific details are
set forth in order to provide a thorough understanding of the
present invention. It will be apparent, however, to one skilled in
the art that the present invention may be practiced without some or
all of these specific details. In other instances, well known
process operations have not been described in detail in order not
to unnecessarily obscure the present invention.
[0052] Integrated circuit scaling has been enabled to a large
extent by improvements in photolithography equipment resolution and
overlay. The resolution capability was such that random logical
functions could be drawn with two-dimensional (2D) bent layout
shapes with few restrictions on layout shape dimensions or
relationships between layout shapes. Some parts of certain types of
integrated circuits (IC's), for example memory cells in a DRAM or
Flash memory, were drawn with more regular layout patterns to
permit reducing the feature sizes and hence the memory bit
size.
[0053] As optical lithography has reached a cost-driven limit of
the 193 nm ArF excimer laser light source and a lens numerical
aperture of 0.93 (or 1.35 for water immersion systems), other
approaches are being considered. One such approach is double
patterning, in which the layout pattern is split into two parts,
each of which can be separately processed with optical lithography
equipment.
[0054] One approach to double patterning for regular layout
patterns is SDP (spacer double patterning). This approach uses the
following sequence to reduce the layout pattern shape-to-shape
pitch by a factor of two: [0055] 1. standard optical lithography to
pattern a "core" [0056] 2. etch the core and remove the resist
[0057] 3. deposit a different material which can be etched
selectively relative to the core [0058] 4. etch the deposited film,
leaving sidewall material and the core [0059] 5. etch the core,
leaving only the sidewall material [0060] 6. cut the sidewall
material to create separate parts [0061] 7. etch the underlying
material using the sidewall material as the mask [0062] 8. remove
the sidewall material, leaving the underlying material with the
desired pattern.
[0063] One attribute of this approach is that all of the sidewall
filaments are uniform in line-width. This is desirable for the gate
electrode layer, since uniform MOS transistor lengths give uniform
circuit speed and leakage.
[0064] However, there are cases in which different gate electrode
line-widths are useful, such as in analog circuits, in SRAM bit
cells, in IO (input/output) cells, and for power optimization using
several gate electrode critical dimensions (CD's) or line-widths,
by way of example. Therefore, it can be necessary to design
circuits that have different gate line-widths and/or MOS transistor
structures with different line-widths. Accordingly, methods are
needed to design and manufacture these types of circuits.
Embodiments of such methods are disclosed herein.
[0065] Although the exemplary descriptions herein are provided
within the context of the gate electrode layer, the approaches and
principles illustrated herein can be applied to any masking
layer/device layer in which SDP is done. Also, in some cases,
multiple applications of SDP can be performed to obtain a pitch
division by 4 or more. The "core" as depicted in the figures herein
can either be a directly patterned core, or a line coming from a
first SDP sequence which is now used as the "core" for a second SDP
sequence. The linewidth modifications could be applied either after
the first sequence, the second sequence, or both.
[0066] Gate linewidth modification is an effective method to
control MOS transistor "off" or "leakage" current since. At
technology nodes roughly below 28 nm (nanometers), the gate
electrode is not patterned directly from a mask pattern. Instead,
because of photolithography limits on pitch and the need for
reduced LER (line-edge-roughness), the fabrication is done with the
SDP process sequence. A "mold" or "core" is patterned and etched,
then a filament is created around the edge. The width of the
filament is uniform, and becomes the linewidth of the gate
electrode. Hence, the gate linewidths are the same within the
tolerance of the filament process.
[0067] A chip design is proposed which uses multiple gate electrode
line-widths. The line-width is chosen based on requirements such
as: [0068] 1. Relative current at a given gate bias for analog
circuits [0069] 2. Ratio of current for select and pull-down
transistors in an SRAM bit cell [0070] 3. Field-dependent breakdown
voltage for IO transistors [0071] 4. Power optimized timing path,
in which some transistors have gate lengths adjusted to reduce
speed and leakage current or to increase speed and leakage
current
[0072] Structures on the chip are proposed with different gate
electrode line-widths. These structures can be applied to functions
such as: [0073] 1. Analog circuits [0074] 2. SRAM bit cells [0075]
3. IO cells [0076] 4. Logic cells selected for power/speed
optimization
[0077] Example methods to create the structures on the chip
include: [0078] 1. Individually patterned lines with different
widths [0079] 2. SDP pitch division flow to create lines, followed
by circuit customization with cuts [0080] a. SDP to create uniform
lines [0081] b. SDP with different sidewall filaments created with
optical resolution or sub-optical resolution (e.g., e-beam) [0082]
c. SDP with multiple film depositions and patterned etches to
achieve different line-widths (combinations of etch selectivity are
required, but the CD is well controlled by the film thicknesses)
[0083] d. SDP with patterned etches, each etch creating a different
line-width through etch time or etch rate or both
[0084] FIG. 1 shows a plan view of the gate electrode layer of an
example logic circuit with uniform conductive segment line-widths,
in accordance with an example embodiment. The conductive segments
of uniform line-width are represented by shapes 101, 103, 105, 107,
109, 111, 113, and 115.
[0085] FIG. 2 shows a plan view of the gate electrode layer of an
example logic circuit with two different conductive segment
line-widths, and with conductive segment line-widths grouped for
the same optical resolution as a core pattern, in accordance with
an example embodiment. The conductive segments of a first larger
line width are represented by shapes 201, 203, 209, 211, and 213.
The conductive segments of a second smaller line width are
represented by shapes 205, 207, and 215.
[0086] FIG. 3 shows a plan view of the gate electrode layer of an
example logic circuit with two different conductive segment
line-widths, and with line-widths patterned with a resolution
higher than used for the core pattern, in accordance with an
example embodiment. The conductive segments of a first larger line
width are represented by shapes 301, 303, and 311. The conductive
segments of a second smaller line width are represented by shapes
305, 307, 309, 313, and 315.
[0087] FIG. 4 shows a plan view of the gate electrode layer of an
example logic circuit with three different conductive segment
line-widths, and with line-widths grouped for the same optical
resolution as a core pattern, in accordance with an example
embodiment. The conductive segments of a first larger line width
are represented by shapes 409 and 411. The conductive segments of a
second smaller line width are represented by shapes 405, 407, and
415. The conductive segments of a third smallest line width are
represented by shapes 401, 403, and 413.
[0088] FIG. 5A shows a plan view, i.e., top view, of a core pattern
for use in forming a gate electrode layer of an example logic
circuit, in accordance with an example embodiment. The core pattern
includes core structures 521, 523, and 525. The core structures
521, 523, and 525 are temporary structures that are formed of a
material that can be subsequently removed. For example, the core
structures 521, 523, and 525 can be formed of photoresist material
or advanced patterning film (APF), among other types of materials.
The core pattern is formed above a conductive layer that is to be
formed into conductive segments to create the gate electrode
layer.
[0089] FIG. 5B shows the plan view of the core pattern of FIG. 5A
following dielectric deposition and etching processes to form
sidewall filaments 531, 533, and 535, in accordance with an example
embodiment. The sidewall filaments are formed of a material that is
suitable for use as a hard-mask material for subsequent etching of
the underlying conductive layer that is to be formed into
conductive segments to create the gate electrode layer.
[0090] FIG. 5C shows the plan view of the sidewall filaments 531,
533, 535 of FIG. 5B after the core pattern, including core
structures 521, 523, and 525, has been removed, in accordance with
an example embodiment.
[0091] FIG. 5D shows a plan view of a cut pattern overlying the
sidewall filaments 531, 533, 535 of FIG. 5C, prior to etching the
sidewall filaments 531, 533, 535 in the cut pattern areas 541, 543,
545, and 547, in accordance with an example embodiment.
[0092] FIG. 5E shows the plan view of the sidewall filaments 531,
533, 535 of FIG. 5D after they have been etched within the cut
pattern areas 541, 543, 545, and 547 as shown in FIG. 5D, in
accordance with an example embodiment. At this point, the sidewall
filaments 531, 533, 535 form a patterned hard mask that can be used
to etch the underlying conductive material layer to form conductive
structures within a gate electrode layer of the example logic
circuit.
[0093] FIG. 6A shows a plan view, i.e., top view, of a core pattern
that includes core structures 621, 623, and 625, surrounded by
sidewall filaments 631, 633, and 635, respectively, in accordance
with an example embodiment. In one embodiment, the core pattern and
surrounding sidewall filaments 631, 633, and 635 of FIG. 6A are
formed as part of a hard mask creation process, wherein the hard
mask is to be used for etching an underlying conductive layer of
material to form conductive structures within a gate electrode
layer of an integrated circuit device. As with the previous example
of FIGS. 5A-5E, the sidewall filaments 631, 633, and 635 can be
formed around the core structures 621, 623, and 625 by dielectric
deposition and etching processes, by way of example. FIG. 6A also
shows an opening 641 in a mask pattern that is deposited to overly
the core structures 621, 623, 625, and sidewall filaments 631, 633,
635. In this example, the mask pattern covers core structures 621,
625 and their surrounding sidewall filaments 631 and 635. The
opening 641 in the mask pattern exposes the sidewall filament 633
to an etching process. In this manner, the sidewall filament 633
can be etched to reduce its width, as measured outward from the
core structure 623, without affecting the sizes of sidewall
filaments 631 and 635. Therefore, sidewall filament 633 can be
selectively adjusted in size, i.e., width.
[0094] FIG. 6B shows the plan view of FIG. 6A after the etching
process to reduce the width of the sidewall filament 633 that is
exposed through the mask opening 641, in accordance with an example
embodiment.
[0095] FIG. 6C shows the plan view of FIG. 6B after the first
etching process to reduce the width of the sidewall filament 633,
in accordance with an example embodiment. FIG. 6C also shows the
overlying mask pattern (that is deposited to overly the core
structures 621, 623, 625, and sidewall filaments 631, 633, 635)
adjusted to have an opening 643 which exposes the sidewall filament
631 without exposing the other sidewall filaments 633 and 635. With
the sidewall filament 631 selectively exposed by way of the mask
opening 643, the sidewall filament 631 can be etched to
independently adjust its width size.
[0096] FIG. 6D shows the plan view of FIG. 6C after the second
etching process to reduce the width of the sidewall filament 631,
in accordance with an example embodiment. FIG. 6D also shows the
core structures 621, 623, 625 removed. The sidewall filaments 631,
633, and 635 now have differing widths, and can be cut as needed,
similar to the examples of FIGS. 5D-5E, to define a hard mask for
etching of an underlying conductive material layer.
[0097] FIG. 7A shows vertical cross-section view of a core pattern
for use in forming a gate electrode layer of an example logic
circuit, in accordance with an example embodiment. The
cross-section shows a substrate 701, a gate dielectric material
layer 703 deposited on the substrate 701, and a gate conductor
material layer 705 deposited on the gate dielectric material layer
703. The cross-section also shows core structures 711, 713, and 715
formed on the gate conductor material layer 705. It should be
understood that the core structures 711, 713, and 715 are formed
through a deposition, mask patterning, and etching process
conducted above the gate conductor material layer 705.
[0098] FIG. 7B shows the cross-section view of FIG. 7A, after
deposition of a material layer 721 which will later become sidewall
filaments, in accordance with an example embodiment.
[0099] FIG. 7C shows the cross-section view of FIG. 7B, after the
material layer 721 has been etched to transform it into sidewall
filaments 731, 732, 733, 734, 735, 736 formed along sides of the
core structures 711, 713, 715, in accordance with an example
embodiment.
[0100] FIG. 7D shows the cross-section view of FIG. 7C with a mask
material 706 deposited to cover the core structures 711, 715, and
their sidewall filaments 731, 732, 735, 736, and leave the core
structure 713 and its sidewall filaments 733, 734 exposed, in
accordance with an example embodiment. The mask material 706
protects the core structures 711, 715, and their sidewall filaments
731, 732, 735, 736 from a subsequent etching process, and thereby
enables further selective etching of the sidewall filaments 733,
734.
[0101] FIG. 7E shows the cross-section view of FIG. 7C, after the
sidewall filaments 733 and 734 have been selectively etched to
reduce their width sizes, in accordance with an example embodiment.
As illustrated by the example in FIGS. 6A-6B, a mask layer can be
formed with an opening defined to expose the core structure 713 and
its surrounding sidewall filaments 733 and 734 to enable the
selective etching, i.e., selective width size adjustment, of the
sidewall filaments 733 and 734, relative to the other sidewall
filaments 731, 732, 735, and 736.
[0102] FIG. 7F shows the cross-section view of FIG. 7E with a mask
material 706 deposited to cover the core structures 713, 715, and
their sidewall filaments 733, 734, 735, 736, and leave the core
structure 711 and its sidewall filaments 731, 732 exposed, in
accordance with an example embodiment. The mask material 706
protects the core structures 713, 715, and their sidewall filaments
733, 734, 735, 736 from a subsequent etching process, and thereby
enables further selective etching of the sidewall filaments 731,
732.
[0103] FIG. 7G shows the cross-section view of FIG. 7E, after the
surrounding sidewall filaments 731 and 732 have been selectively
etched to reduce their width sizes, in accordance with an example
embodiment. As illustrated by the example in FIGS. 6C-6D, a mask
layer can be formed with an opening defined to expose the core
structure 711 and its surrounding sidewall filaments 731 and 732 to
enable the selective etching, i.e., selective width size
adjustment, of the sidewall filaments 731 and 732, relative to the
other sidewall filaments 733, 734, 735, and 736.
[0104] FIG. 7H shows the cross-section view of FIG. 7G, after the
core structures 711, 713, 715 have been removed, in accordance with
an example embodiment. The sidewall filaments 731, 732, 733, 734,
735, 736 provide a mask for etching the underlying gate conductor
material layer 705. FIG. 7I shows the cross-section view of FIG.
7H, after the underlying gate conductor material layer 705 has been
etched in regions between the sidewall filaments 731, 732, 733,
734, 735, 736, in accordance with an example embodiment. FIG. 7J
shows the cross-section view of FIG. 7I, after the sidewall
filaments 731, 732, 733, 734, 735, 736 have been removed, thereby
leaving the etched gate conductor material layer 705, in accordance
with an example embodiment.
[0105] FIG. 8A shows a vertical cross-section view of a core
structure 803 formed on a conductive material layer 801 (e.g., gate
conductor material layer 801), in accordance with an example
embodiment. FIG. 8A also shows three different sidewall filament
material layers 811, 813, and 815 sequentially and conformally
deposited over the core structure 803 and surrounding/adjacent
conductive material layer 801.
[0106] FIG. 8B shows the cross-section view of FIG. 8A, after an
etching process which leaves a full-width sidewall filament 850, in
accordance with an example embodiment. Considering that the
sidewall filament 850 will serve as a hard mask to protect the
underlying gate conductor material layer 801 during a subsequent
etching process to form conductive segments within the gate
electrode layer, and further considering that the core structure
803 will be removed prior to the subsequent etching process on the
gate conductor material layer 801, the width size 870 of the
sidewall filament 850 effectively defines the width size of the
conductive segment to be formed within the gate conductor material
layer 801. FIG. 8C shows the cross-section view of FIG. 8B, after
the core structure 803 has been removed, and the sidewall filaments
850 have been used as a mask for etching the underlying gate
conductor material layer 801, in accordance with an example
embodiment.
[0107] Considering that the conductive segment formed within the
gate conductor material layer 801 below the sidewall filament 850
is a gate electrode of a transistor, the width size 870 of the gate
electrode of the transistor (which may also be referred to as the
transistor's channel length) can be adjusted by adjusting the width
size 870 of the sidewall filament. FIG. 8D shows the cross-section
of FIG. 8B following a further etching process to obtain sidewall
filaments 853 of reduced width 873, relative to the sidewall
filaments 850 of FIG. 8B, in accordance with an example embodiment.
It should be understood that the etching of the sidewall filaments
can be controlled, by way of a mask pattern, such that either one
or both of the sidewall filaments adjacent to the core structure
803 is etched, i.e., thinned. Also, it should be understood that
the layered deposition of the sidewall filament material in the
layers 811, 813, and 815 can provide control of sidewall filament
etching, such that the etching will stop at the boundaries between
the successively removed sidewall filament material layers.
[0108] FIG. 8E shows the cross-section view of FIG. 8D, after the
core structure 803 and outside sidewall filament layer 815 have
been removed, and the sidewall filaments 853 have been used as a
mask for etching the underlying gate conductor material layer 801,
in accordance with an example embodiment. FIG. 8F shows the
cross-section of FIG. 8D following a further etching process to
reduce the sidewall filament 855 width 875 to essentially the
thickness of the first deposited sidewall filament material layer
811, in accordance with an example embodiment. FIG. 8G shows the
cross-section view of FIG. 8F, after the core structure 803 and
sidewall filament layer 813 have been removed, and the sidewall
filaments 855 have been used as a mask for etching the underlying
gate conductor material layer 801, in accordance with an example
embodiment.
[0109] The examples of FIGS. 8A-8G utilized successively deposited
sidewall filament material layers to provide a measure of etching
control for the sidewall filaments, such that boundaries between
the successively deposited sidewall filament material layers
provided etching stops to facilitate sizing of the sidewall
filaments, and correspondingly formed underlying gate electrode
layer conductive structures. However, some etching processes may
enable sidewall filament thickness control without requiring
sidewall material layer boundaries.
[0110] For example, FIG. 9A shows a vertical cross-section view of
a core structure 903 formed on a conductive material layer 901
(e.g., gate conductor material layer 901), in accordance with an
example embodiment. FIG. 9A also shows a single sidewall filament
material layer 911 conformally deposited over the core structure
903 and surrounding/adjacent conductive material layer 901.
[0111] FIG. 9B shows the cross-section view of FIG. 9A, after an
etching process which leaves sidewall filaments 911 and 912 of
width size 950, in accordance with an example embodiment. The width
size 950 may represent a largest gate electrode layer conductive
segment width size. In this case, the sidewall filaments 911 and
912 are ready to use as the hard mask for etching of the underlying
gate conductor material layer 901. FIG. 9C shows the cross-section
view of FIG. 9B, after the core structure 903 has been removed, and
the sidewall filaments 911, 912 have been used as a mask for
etching the underlying gate conductor material layer 901, in
accordance with an example embodiment.
[0112] It may be necessary to form gate electrode layer conductive
segments of reduced size. In this case, the etching of the sidewall
filaments can continue until the desired width size is obtained.
Again, it should be understood that appropriately formed mask
patterns can expose any one or more sidewall filaments for etching
and size adjustment. For example, FIG. 9D shows the cross-section
of FIG. 9B, after further etching of the sidewall filaments 911 and
912 to obtain sidewall filaments 921 and 922 of reduced width size
953, in accordance with an example embodiment. FIG. 9E shows the
cross-section view of FIG. 9D, after the core structure 903 has
been removed, and the sidewall filaments 921, 922 have been used as
a mask for etching the underlying gate conductor material layer
901, in accordance with an example embodiment.
[0113] Additionally, FIG. 9F shows the cross-section of FIG. 9D,
after further etching of the sidewall filaments 921 and 922 to
obtain sidewall filaments 931 and 932 of even further reduced width
size 955, in accordance with an example embodiment. FIG. 9G shows
the cross-section view of FIG. 9F, after the core structure 903 has
been removed, and the sidewall filaments 931, 932 have been used as
a mask for etching the underlying gate conductor material layer
901, in accordance with an example embodiment.
[0114] FIG. 10 shows a plan view of the gate electrode layer of a
portion of an example SRAM cell with gate electrode layer
conductive segments (1001, 1003, 1005, 1007, 1009, 1011, 1013,
1015) of uniform width size, as measured in the direction (x), in
accordance with an example embodiment. Also, the example of FIG. 10
shows diffusion regions 1021 and 1023 of non-uniform size, i.e., of
non-uniform active line-widths, to improve static noise margin. The
principles disclosed herein with regard to FIGS. 1-9G can be used
to form the gate electrode layer conductive segments (1001, 1003,
1005, 1007, 1009, 1011, 1013, 1015).
[0115] FIG. 11 shows a plan view of the gate electrode layer of a
portion of an example SRAM cell with gate electrode layer
conductive segments (1101, 1103, 1105, 1107, 1109, 1111, 1113,
1115) of non-uniform width size, as measured in the direction (x),
in accordance with an example embodiment. Also, the example of FIG.
11 shows diffusion regions 1121 and 1123 of uniform size, i.e., of
uniform active line-widths, to improve static noise margin. The
principles disclosed herein with regard to FIGS. 1-9G can be used
to form the gate electrode layer conductive segments (1101, 1103,
1105, 1107, 1109, 1111, 1113, 1115). This approach is suitable for
FinFETs, in which the active regions, i.e., diffusion regions, are
fins of uniform width.
[0116] The embodiments illustrated herein provide for patterning of
the gate electrode layer, or for any layer that uses patterning
that cannot be achieved by litho in a single step. Examples of
other layers that may benefit from the embodiments shown herein can
include metallization layers requiring multiple widths for power
bussing etc. The patterning can be SDP patterning or litho-based
double patterning. In one embodiment, the gate electrode layer (or
other layer) line widths are selectively decreased by using a
patterned trim step. In one embodiment, the gate electrode layer
(or other layer) line widths are selectively increased by using a
patterned resist reflow step. In one embodiment, the gate electrode
layer (or other layer) patterning is completed by cutting the
filaments based on a pattern set by the circuit layout.
[0117] FIG. 12 shows a flowchart of a method for fabricating a mask
for etching of linear-shaped structures for an integrated circuit,
in accordance with one embodiment of the present invention. The
method includes an operation 1201 in which a linear-shaped core
structure of a first material is formed on an underlying material.
The method also includes an operation 1203 for conformally
depositing a layer of a second material over the linear-shaped core
structure and exposed portions of the underlying material. The
method also includes an operation 1205 for etching the layer of the
second material so as to leave a filament of the second material on
each sidewall of the linear-shaped core structure, and so as to
remove the second material from the underlying material. The method
further includes an operation 1207 for removing the linear-shaped
core structure of the first material so as to leave each filament
of the second material on the underlying material, whereby each
filament of the second material provides a mask for etching the
underlying material.
[0118] In one embodiment, the linear-shaped core structure of the
first material is formed on the underlying material in operation
1201 using a mask material patterned by an optical lithography
process. Also, in this embodiment, the filaments of the second
material on the underlying material collectively have dimensions
and spacings too small to be directly formed by the optical
lithography process. In another embodiment, the linear-shaped core
structure of the first material is formed on the underlying
material in operation 1201 using a multiple mask patterning
process, wherein each mask of the multiple mask patterning process
is formed by an optical lithography process. Also, in this
embodiment, the filaments of the second material on the underlying
material collectively have dimensions and spacings too small to be
directly formed by the optical lithography process.
[0119] In one embodiment, operation 1205 for etching the layer of
the second material includes removing the second material from a
top surface of the linear-shaped core structure of the first
material so as to expose the top surface of the linear-shaped core
structure of the first material. Also, in one embodiment, etching
the layer of the second material in operation 1205 includes biasing
an etching front in a direction toward the underlying material. It
should be appreciated that the first material and the second
material have different etching selectivities to enable removal of
the first material without substantial removal of the second
material during a given etching process.
[0120] In one embodiment, the method further includes an operation
in which a cut mask is formed over the filaments of the second
material so as to expose portions of the filaments of the second
material for removal, so as to form ends of linear segments of the
filaments of the second material. In this embodiment, the method
correspondingly includes an operation for removing exposed portions
of the filaments of the second material, whereby the linear
segments of the filaments of the second material provide the mask
for etching the underlying material.
[0121] FIG. 13 shows a flowchart of a method for fabricating a mask
for etching of linear-shaped structures for an integrated circuit,
in accordance with one embodiment of the present invention. The
method includes an operation 1301 in which a plurality of
linear-shaped core structures of a first material are formed on an
underlying material. The method also includes an operation 1303 for
conformally depositing a layer of a second material over each of
the linear-shaped core structures and exposed portions of the
underlying material. An operation 1305 is then performed to etch
the layer of the second material so as to leave a filament of the
second material on each sidewall of each of the linear-shaped core
structures and so as to remove the second material from the
underlying material.
[0122] The method further includes an operation 1307 for depositing
a third material over each filament of the second material. Then,
in an operation 1309, a portion of the third material is removed so
as to expose one or more filaments of the second material. The
method continues with an operation 1311 for etching the exposed
filaments of the second material so as to leave thinner filaments
of the second material. The method also includes an operation 1313
for removing the third material and the plurality of linear-shaped
core structures of the first material so as to leave the filaments
of the second material on the underlying material, whereby the
filaments of the second material provides a mask for etching the
underlying material.
[0123] In one embodiment, each of the plurality of linear-shaped
core structures of the first material is formed on the underlying
material in operation 1301 using a mask material patterned by an
optical lithography process. In this embodiment, the filaments of
the second material on the underlying material collectively have
dimensions and spacings too small to be directly formed by the
optical lithography process. In another embodiment, each of the
plurality of linear-shaped core structures of the first material is
formed on the underlying material in operation 1301 using a
multiple mask patterning process. In this embodiment, each mask of
the multiple mask patterning process is formed by an optical
lithography process. Also, in this embodiment, the filaments of the
second material on the underlying material collectively have
dimensions and spacings too small to be directly formed by the
optical lithography process.
[0124] It should be appreciated that the first material and the
second material have different etching selectivities to enable
removal of the first material without substantial removal of the
second material during a given etching process. In one embodiment,
etching the layer of the second material in operation 1305 includes
removing the second material from a top surface of each of the
plurality of linear-shaped core structures of the first material so
as to expose the top surface of each of the plurality of
linear-shaped core structures of the first material. In one
embodiment, etching the layer of the second material in one or both
of operations 1305 and 1311 can include biasing an etching front in
a direction toward the underlying material.
[0125] In one embodiment, the method further includes an operation
in which a cut mask is formed over the filaments of the second
material so as to expose portions of the filaments of the second
material for removal, so as to form ends of linear segments of the
filaments of the second material. This embodiment also includes an
operation for removing exposed portions of the filaments of the
second material, whereby the linear segments of the filaments of
the second material provide the mask for etching the underlying
material.
[0126] In one embodiment, conformally depositing the layer of the
second material over each of the linear-shaped core structures and
exposed portions of the underlying material in operation 1303
includes conformally depositing multiple sub-layers of the second
material. In this embodiment, each boundary between the multiple
sub-layers of the second material provides an etch stop for a
subsequent etching of the second material.
[0127] FIG. 14 shows a flowchart of a method for fabricating
linear-shaped conductive structures for an integrated circuit, in
accordance with one embodiment of the present invention. The method
includes an operation 1401 for depositing a layer of a conductive
material over a substrate. The method also includes an operation
1403 in which a plurality of linear-shaped core structures of a
first material are formed on the conductive material. The method
also includes an operation 1405 for conformally depositing a layer
of a second material over each of the linear-shaped core structures
and exposed portions of the conductive material. The method also
includes an operation 1407 for etching the layer of the second
material so as to leave a filament of the second material on each
sidewall of each of the linear-shaped core structures and so as to
remove the second material from the conductive material. The method
also includes an operation 1409 for depositing a third material
over each filament of the second material. The method also includes
an operation 1411 for removing a portion of the third material to
as to expose one or more of the filaments of the second material.
The method also includes an operation 1413 for etching the exposed
filaments of the second material so as to leave thinner filaments
of the second material. The method also includes an operation 1415
for removing the third material and the plurality of linear-shaped
core structures of the first material so as to leave the filaments
of the second material on the conductive material, whereby the
filaments of the second material provide a mask for etching the
conductive material. The method also includes an operation 1417 for
etching the conductive material so as to leave linear-shaped
portions of the conductive material beneath the filaments of the
second material. The method also includes an operation 1419 for
removing the filaments of the second material from the
linear-shaped portions of the conductive material.
[0128] In one embodiment, the linear-shaped core structure of the
first material is formed on the conductive material in operation
1403 using an optical lithography process. In this embodiment, the
filaments of the second material on the conductive material
collectively have dimensions and spacings too small to be directly
formed by the optical lithography process.
[0129] It should be appreciated that the first material and the
second material have different etching selectivities to enable
removal of the first material without substantial removal of the
second material during a given etching process. Also, in one
embodiment, etching the layer of the second material in operation
1407 includes biasing an etching front in a direction toward the
conductive material.
[0130] In one embodiment, the method also includes an operation in
which a cut mask is formed over the filaments of the second
material so as to expose portions of the filaments of the second
material for removal, so as to form ends of linear segments of the
filaments of the second material. Also, in this embodiment, an
operation is performed to remove exposed portions of the filaments
of the second material, whereby the linear segments of the
filaments of the second material provide the mask for etching the
conductive material.
[0131] It should be understood that the methods disclosed herein
can be used to create sidewall filaments having a thickness of less
than or equal to 30 nanometers (nm), in various embodiments.
Because the sidewall filaments provide a mask for fabricating
underlying structures, it should be understood that the thickness
of the sidewall filaments as measured horizontal to the substrate
determines the size, e.g., critical dimension, of the underlying
structures. For a 32 nm process node, the minimum as-drawn
structure size is about 30 nm, which can be incremented by about
10% to obtain structure sizes of about 34 nm, 38 nm, etc. Also,
with a 90% scaling process, the 30 nm minimum as-drawn structure
size can be decreased to obtain about a 28 nm structure size.
Therefore, at the 32 nm process node with the 90% scaling process
applied, sidewall filaments can be formed to fabricate structure
sizes of 28 nm, 32 nm, 36 nm, etc. For a 22 nm process node, the
minimum as-drawn structure size is about 20 nm, which can be
incremented by about 10% to obtain structure sizes of about 22 nm,
24 nm, etc. Also, with a 90% scaling process, the 20 nm minimum
as-drawn structure size can be decreased to obtain about a 18 nm
structure size. Therefore, at the 22 nm process node with the 90%
scaling process applied, sidewall filaments can be formed to
fabricate structure sizes of 18 nm, 20 nm, 22 nm, etc. For a 16 nm
process node, the minimum as-drawn structure size is about 14 nm,
which can be incremented by about 10% to obtain structure sizes of
about 16 nm, 18 nm, etc. Also, with a 90% scaling process, the 14
nm minimum as-drawn structure size can be decreased to obtain about
a 12 nm structure size. Therefore, at the 16 nm process node with
the 90% scaling process applied, sidewall filaments can be formed
to fabricate structure sizes of 12 nm, 14 nm, 16 nm, etc. It should
be appreciated that structure size fabrication capabilities of
future process nodes can be scaled by a factor of about 0.7 to
about 0.8.
[0132] It should be understood that layout features associated with
the methods disclosed herein can be implemented in a layout that is
stored in a tangible form, such as in a digital format on a
computer readable medium. For example, the layouts incorporating
the layout features associated with the methods disclosed herein
can be stored in a layout data file of one or more cells,
selectable from one or more libraries of cells. The layout data
file can be formatted as a GDS II (Graphic Data System) database
file, an OASIS (Open Artwork System Interchange Standard) database
file, or any other type of data file format suitable for storing
and communicating semiconductor device layouts. Also, multi-level
layouts including the layout features associated with the methods
disclosed herein can be included within a multi-level layout of a
larger semiconductor device. The multi-level layout of the larger
semiconductor device can also be stored in the form of a layout
data file, such as those identified above.
[0133] Also, the invention described herein can be embodied as
computer readable code on a computer readable medium. For example,
the computer readable code can include the layout data file within
which one or more layouts including layout features associated with
the methods disclosed herein are stored. The computer readable code
can also include program instructions for selecting one or more
layout libraries and/or cells that include a layout including
layout features associated with the methods disclosed herein. The
layout libraries and/or cells can also be stored in a digital
format on a computer readable medium.
[0134] The computer readable medium mentioned herein is any data
storage device that can store data which can thereafter be read by
a computer system. Examples of the computer readable medium include
hard drives, network attached storage (NAS), read-only memory,
random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and
other optical and non-optical data storage devices. The computer
readable medium can also be distributed over a network of coupled
computer systems so that the computer readable code is stored and
executed in a distributed fashion.
[0135] Any of the operations described herein that form part of the
invention are useful machine operations. The invention also relates
to a device or an apparatus for performing these operations. The
apparatus may be specially constructed for the required purpose,
such as a special purpose computer. When defined as a special
purpose computer, the computer can also perform other processing,
program execution or routines that are not part of the special
purpose, while still being capable of operating for the special
purpose. Alternatively, the operations may be processed by a
general purpose computer selectively activated or configured by one
or more computer programs stored in the computer memory, cache, or
obtained over a network. When data is obtained over a network the
data maybe processed by other computers on the network, e.g., a
cloud of computing resources.
[0136] The embodiments of the present invention can also be defined
as a machine that transforms data from one state to another state.
The data may represent an article, that can be represented as an
electronic signal and electronically manipulate data. The
transformed data can, in some cases, be visually depicted on a
display, representing the physical object that results from the
transformation of data. The transformed data can be saved to
storage generally, or in particular formats that enable the
construction or depiction of a physical and tangible object. In
some embodiments, the manipulation can be performed by a processor.
In such an example, the processor thus transforms the data from one
thing to another. Still further, the methods can be processed by
one or more machines or processors that can be connected over a
network. Each machine can transform data from one state or thing to
another, and can also process data, save data to storage, transmit
data over a network, display the result, or communicate the result
to another machine.
[0137] It should be further understood that the layout features
associated with the methods disclosed herein can be manufactured as
part of a semiconductor device or chip. In the fabrication of
semiconductor devices such as integrated circuits, memory cells,
and the like, a series of manufacturing operations are performed to
define features on a semiconductor wafer. The wafer includes
integrated circuit devices in the form of multi-level structures
defined on a silicon substrate. At a substrate level, transistor
devices with diffusion regions are formed. In subsequent levels,
interconnect metallization lines are patterned and electrically
connected to the transistor devices to define a desired integrated
circuit device. Also, patterned conductive layers are insulated
from other conductive layers by dielectric materials.
[0138] While this invention has been described in terms of several
embodiments, it will be appreciated that those skilled in the art
upon reading the preceding specifications and studying the drawings
will realize various alterations, additions, permutations and
equivalents thereof. Therefore, it is intended that the present
invention includes all such alterations, additions, permutations,
and equivalents as fall within the true spirit and scope of the
invention.
* * * * *