Smayling; Michael C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Smayling; Michael C..The latest application filed is for "methods, structures, and designs for self-aligning local interconnects used in integrated circuits".

Company Profile

12.200.156

Smayling; Michael C. - Fremont CA
Smayling; Michael C. - San Jose CA US
Smayling; Michael C. - Fremond CA
Smayling; Michael C. - Campbell CA
Smayling; Michael C. - Milpitas CA
Smayling; Michael C. - Sunnyvale CA
Smayling; Michael C. - Fermont CA
Smayling; Michael C. - Missouri City TX
Smayling; Michael C. - Fort Bend TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Precision substrate material multi-processing using miniature-column charged particle beam arrays Grant 11,037,756 - Lam , et al. June 15, 2	2021-06-15
Secure permanent integrated circuit personalization Grant 10,978,303 - Smayling , et al. April 13, 2	2021-04-13
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits App 20200381429 - Smayling; Michael C. ; et al.	2020-12-03
Methods, structures, and designs for self-aligning local interconnects used in integrated circuits Grant 10,734,383 - Smayling , et al.	2020-08-04
Precision substrate material multi-processing using miniature-column charged particle beam arrays Grant 10,734,192 - Lam , et al.	2020-08-04
Secure permanent integrated circuit personalization Grant 10,659,229 - Smayling , et al.	2020-05-19
Precision substrate material multi-processing using miniature-column charged particle beam arrays Grant 10,658,153 - Lam , et al.	2020-05-19
Patterned atomic layer etching and deposition using miniature-column charged particle beam arrays Grant 10,607,845 - Monahan , et al.	2020-03-31
Super-Self-Aligned Contacts and Method for Making the Same App 20200066722 - Smayling; Michael C.	2020-02-27
Super-self-aligned contacts and method for making the same Grant 10,461,081 - Smayling Oc	2019-10-29
Secure permanent integrated circuit personalization Grant 10,341,108 - Smayling , et al.	2019-07-02
Secure permanent integrated circuit personalization Grant 10,312,091 - Smayling , et al.	2019-06-04
Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid Grant 10,217,763 - Becker , et al. Feb	2019-02-26
Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid Grant 10,186,523 - Becker , et al. Ja	2019-01-22
Semiconductor Chip Having Region Including Gate Electrode Features Formed In Part from Rectangular Layout Shapes on Gate Horizontal Grid and First-Metal Structures Formed In Part from Rectangular Layout Shapes on First-Metal Vertical Grid App 20190019810 - Becker; Scott T. ; et al.	2019-01-17
Semiconductor Chip Having Region Including Gate Electrode Features of Rectangular Shape on Gate Horizontal Grid and First-Metal Structures of Rectangular Shape on First-Metal Vertical Grid App 20180374871 - Becker; Scott T. ; et al.	2018-12-27
Semiconductor Chip Having Region Including Gate Electrode Features Formed In Part from Rectangular Layout Shapes on Gate Horizontal Grid and First-Metal Structures Formed In Part from Rectangular Layout Shapes on At Least Eight First-Metal Gridlines of First-Metal Vertical Grid App 20180374873 - Becker; Scott T. ; et al.	2018-12-27
Semiconductor Chip Having Region Including Gate Electrode Features of Rectangular Shape on Gate Horizontal Grid and First-Metal Structures of Rectangular Shape on At Least Eight First-Metal Gridlines of First-Metal Vertical Grid App 20180374872 - Becker; Scott T. ; et al.	2018-12-27
Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures Grant 10,141,335 - Becker , et al. Nov	2018-11-27
Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures Grant 10,141,334 - Becker , et al. Nov	2018-11-27
Integrated circuit cell library for multiple patterning Grant 10,074,640 - Smayling , et al. September 11, 2	2018-09-11
Coarse Grid Design Methods and Structures App 20180204795 - Smayling; Michael C. ; et al.	2018-07-19
Alignment and registration targets for charged particle beam substrate patterning and inspection Grant 10,026,589 - Monahan , et al. July 17, 2	2018-07-17
Patterned atomic layer etching and deposition using miniature-column charged particle beam arrays Grant 10,020,200 - Monahan , et al. July 10, 2	2018-07-10
Alignment and registration targets for charged particle beam substrate patterning and inspection Grant 10,020,166 - Monahan , et al. July 10, 2	2018-07-10
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits App 20180145075 - Smayling; Michael C. ; et al.	2018-05-24
Super-Self-Aligned Contacts and Method for Making the Same App 20180083003 - Smayling; Michael C.	2018-03-22
Coarse grid design methods and structures Grant 9,917,056 - Smayling , et al. March 13, 2	2018-03-13
Semiconductor chip including region having rectangular-shaped gate structures and first metal structures Grant 9,905,576 - Becker , et al. February 27, 2	2018-02-27
Precision substrate material multi-processing using miniature-column charged particle beam arrays Grant 9,881,817 - Lam , et al. January 30, 2	2018-01-30
Methods, structures, and designs for self-aligning local interconnects used in integrated circuits Grant 9,859,277 - Smayling , et al. January 2, 2	2018-01-02
Semiconductor Chip and Method for Manufacturing the Same App 20170365620 - Becker; Scott T. ; et al.	2017-12-21
Semiconductor Chip and Method for Manufacturing the Same App 20170365621 - Becker; Scott T. ; et al.	2017-12-21
Semiconductor Chip and Method for Manufacturing the Same App 20170358600 - Becker; Scott T. ; et al.	2017-12-14
Precision material modification using miniature-column charged particle beam arrays Grant 9,824,859 - Smayling , et al. November 21, 2	2017-11-21
Precision material modification using miniature-column charged particle beam arrays Grant 9,822,443 - Smayling , et al. November 21, 2	2017-11-21
Super-self-aligned contacts and method for making the same Grant 9,818,747 - Smayling November 14, 2	2017-11-14
Methods for Linewidth Modification and Apparatus Implementing the Same App 20170309609 - Smayling; Michael C. ; et al.	2017-10-26
Methods, structures, and designs for self-aligning local interconnects used in integrated circuits Grant 9,741,719 - Smayling , et al. August 22, 2	2017-08-22
Integrated Circuit Cell Library for Multiple Patterning App 20170229441 - Smayling; Michael C. ; et al.	2017-08-10
Methods for linewidth modification and apparatus implementing the same Grant 9,704,845 - Smayling , et al. July 11, 2	2017-07-11
Semiconductor Chip and Method for Manufacturing the Same App 20170186771 - Becker; Scott T. ; et al.	2017-06-29
Semiconductor Chip Including Integrated Circuit Defined Within Dynamic Array Section App 20170186772 - Becker; Scott T. ; et al.	2017-06-29
Integrated Circuit Implementing Scalable Meta-Data Objects App 20170177779 - Smayling; Michael C. ; et al.	2017-06-22
Precision substrate material removal using miniature-column charged particle beam arrays Grant 9,673,114 - Lam , et al. June 6, 2	2017-06-06
Integrated circuit cell library for multiple patterning Grant 9,633,987 - Smayling , et al. April 25, 2	2017-04-25
Alignment and registration targets for multiple-column charged particle beam lithography and inspection Grant 9,595,419 - Monahan , et al. March 14, 2	2017-03-14
Semiconductor chip including integrated circuit defined within dynamic array section Grant 9,595,515 - Becker , et al. March 14, 2	2017-03-14
Scalable meta-data objects Grant 9,589,091 - Smayling , et al. March 7, 2	2017-03-07
Semiconductor Chip and Method for Manufacturing the Same App 20170053937 - Becker; Scott T. ; et al.	2017-02-23
Precision deposition using miniature-column charged particle beam arrays Grant 9,556,521 - Prescop , et al. January 31, 2	2017-01-31
Semiconductor Chip and Method for Manufacturing the Same App 20160379991 - Becker; Scott T. ; et al.	2016-12-29
Alignment and registration targets for multiple-column charged particle beam lithography and inspection Grant 9,478,395 - Monahan , et al. October 25, 2	2016-10-25
Precision substrate material removal using miniature-column charged particle beam arrays Grant 9,466,464 - Lam , et al. October 11, 2	2016-10-11
Precision deposition using miniature-column charged particle beam arrays Grant 9,453,281 - Prescop , et al. September 27, 2	2016-09-27
Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same Grant 9,443,947 - Becker , et al. September 13, 2	2016-09-13
Coarse Grid Design Methods and Structures App 20160254223 - Smayling; Michael C. ; et al.	2016-09-01
Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same Grant 9,425,273 - Becker , et al. August 23, 2	2016-08-23
Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same Grant 9,425,272 - Becker , et al. August 23, 2	2016-08-23
Super-Self-Aligned Contacts and Method for Making the Same App 20160190132 - Smayling; Michael C.	2016-06-30
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits App 20160133625 - Smayling; Michael C. ; et al.	2016-05-12
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits App 20160133626 - Smayling; Michael C. ; et al.	2016-05-12
Coarse grid design methods and structures Grant 9,336,344 - Smayling , et al. May 10, 2	2016-05-10
Semiconductor Chip Including Integrated Circuit Including At Least Five Gate Level Conductive Structures Having Particular Spatial and Electrical Relationship and Method for Manufacturing the Same App 20160079381 - Becker; Scott T. ; et al.	2016-03-17
Super-self-aligned contacts and method for making the same Grant 9,281,371 - Smayling March 8, 2	2016-03-08
Methods for Linewidth Modification and Apparatus Implementing the Same App 20160027770 - Smayling; Michael C. ; et al.	2016-01-28
Methods, structures, and designs for self-aligning local interconnects used in integrated circuits Grant 9,240,413 - Smayling , et al. January 19, 2	2016-01-19
Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication App 20150363542 - Reed; Brian ; et al.	2015-12-17
Methods for linewidth modification and apparatus implementing the same Grant 9,159,627 - Smayling , et al. October 13, 2	2015-10-13
Semiconductor Chip Including Integrated Circuit Including Four Transistors of First Transistor Type and Four Transistors of Second Transistor Type with Electrical Connections Between Various Transistors and Methods for Manufacturing the Same App 20150270218 - Becker; Scott T. ; et al.	2015-09-24
Semiconductor Chip Including Region Having Integrated Circuit Transistor Gate Electrodes Formed by Various Conductive Structures of Specified Shape and Position and Method for Manufacturing the Same App 20150249041 - Becker; Scott T. ; et al.	2015-09-03
Methods for controlling microloading variation in semiconductor wafer layout and fabrication Grant 9,122,832 - Reed , et al. September 1, 2	2015-09-01
Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods Grant 9,035,359 - Becker , et al. May 19, 2	2015-05-19
Circuits with linear finfet structures Grant 9,009,641 - Becker , et al. April 14, 2	2015-04-14
Super-Self-Aligned Contacts and Method for Making the Same App 20150091190 - Smayling; Michael C.	2015-04-02
Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length Grant 8,952,425 - Becker , et al. February 10, 2	2015-02-10
Super-self-aligned contacts and method for making the same Grant 8,951,916 - Smayling February 10, 2	2015-02-10
Integrated circuit including gate electrode conductive structures with different extension distances beyond contact Grant 8,946,781 - Becker , et al. February 3, 2	2015-02-03
Integrated circuit with gate electrode conductive structures having offset ends Grant 8,921,897 - Becker , et al. December 30, 2	2014-12-30
Integrated circuit including linear gate electrode structures having different extension distances beyond contact Grant 8,921,896 - Becker , et al. December 30, 2	2014-12-30
Scalable Meta-Data Objects App 20140380260 - Smayling; Michael C. ; et al.	2014-12-25
Finfet transistor circuit Grant 8,863,063 - Becker , et al. October 14, 2	2014-10-14
Semiconductor Chip Including Region Including Linear-Shaped Conductive Structures Forming Gate Electrodes and Having Electrical Connection Areas Arranged Relative to Inner Region Between Transistors of Different Types and Associated Methods App 20140291731 - Becker; Scott T. ; et al.	2014-10-02
Scalable meta-data objects Grant 8,839,175 - Smayling , et al. September 16, 2	2014-09-16
Semiconductor Chip Including Integrated Circuit Defined Within Dynamic Array Section App 20140246733 - Becker; Scott T. ; et al.	2014-09-04
Integrated circuit with offset line end spacings in linear gate electrode level Grant 8,823,062 - Becker , et al. September 2, 2	2014-09-02
Integrated Circuit Cell Library for Multiple Patterning App 20140175565 - Smayling; Michael C. ; et al.	2014-06-26
Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos Grant 8,759,882 - Becker , et al. June 24, 2	2014-06-24
Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits App 20140167185 - Smayling; Michael C. ; et al.	2014-06-19
Coarse Grid Design Methods and Structures App 20140167183 - Smayling; Michael C. ; et al.	2014-06-19
Methods for designing semiconductor device with dynamic array section Grant 8,756,551 - Becker , et al. June 17, 2	2014-06-17
Methods, structures, and designs for self-aligning local interconnects used in integrated circuits Grant 8,680,626 - Smayling , et al. March 25, 2	2014-03-25
Integrated circuit cell library for multiple patterning Grant 8,667,443 - Smayling , et al. March 4, 2	2014-03-04
Coarse grid design methods and structures Grant 8,658,542 - Smayling , et al. February 25, 2	2014-02-25
Super-Self-Aligned Contacts and Method for Making the Same App 20140030890 - Smayling; Michael C.	2014-01-30
Integrated Circuit Including Linear Gate Electrode Structures Having Different Extension Distances Beyond Contact App 20130249013 - Becker; Scott T. ; et al.	2013-09-26
Super-self-aligned contacts and method for making the same Grant 8,541,879 - Smayling September 24, 2	2013-09-24
Finfet Transistor Circuit App 20130207199 - Becker; Scott T. ; et al.	2013-08-15
Integrated Circuit Including Gate Electrode Conductive Structures With Different Extension Distances Beyond Contact App 20130207165 - Becker; Scott T. ; et al.	2013-08-15
Integrated Circuit with Offset Line End Spacings in Linear Gate Electrode Level App 20130200462 - Becker; Scott T. ; et al.	2013-08-08
Integrated Circuit with Gate Electrode Conductive Structures Having Offset Ends App 20130200436 - Becker; Scott T. ; et al.	2013-08-08
Integrated Circuit Including At Least Four Linear-Shaped Conductive Structures Having Extending Portions of Different Length App 20130175639 - Becker; Scott T. ; et al.	2013-07-11
Integrated Circuit Including Gate Electrode Tracks That Each Form Gate Electrodes of Different Transistor Types With Intervening Non-Gate-Forming Gate Electrode Track App 20130168778 - Becker; Scott T. ; et al.	2013-07-04
Integrated Circuit Including Gate Electrode Tracks Forming Gate Electrodes of Different Transistor Types and Linear Shaped Conductor Electrically Connecting Gate Electrodes App 20130168777 - Becker; Scott T. ; et al.	2013-07-04
Integrated Circuit Including Gate Electrode Tracks Including Offset End-to-End Spacings App 20130161760 - Becker; Scott T. ; et al.	2013-06-27
Coarse Grid Design Methods and Structures App 20130130511 - Smayling; Michael C. ; et al.	2013-05-23
Circuits With Linear Finfet Structures App 20130126978 - Becker; Scott T. ; et al.	2013-05-23
Semiconductor device with gate level including gate electrode conductors for transistors of first type and transistors of second type with some gate electrode conductors of different length Grant 8,436,400 - Becker , et al. May 7, 2	2013-05-07
Integrated circuit device including dynamic array section with gate level having linear conductive features on at least three side-by-side lines and uniform line end spacings Grant 8,356,268 - Becker , et al. January 15, 2	2013-01-15
Methods and systems for process compensation technique acceleration Grant 8,286,107 - Smayling , et al. October 9, 2	2012-10-09
Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos Grant 8,283,701 - Becker , et al. October 9, 2	2012-10-09
Semiconductor device including transistor forming linear shapes including gate portions and extending portions of different size Grant 8,264,008 - Becker , et al. September 11, 2	2012-09-11
Semiconductor device including at least six transistor forming linear shapes including at least two different gate contact connection distances Grant 8,264,007 - Becker , et al. September 11, 2	2012-09-11
Semiconductor device with linearly restricted gate level region including four transistors of first type and four transistors of second type with gate defining shapes of different length Grant 8,264,009 - Becker , et al. September 11, 2	2012-09-11
Semiconductor device with gate level including transistors of first type and transistors of second type with corresponding gate contact placement restriction Grant 8,258,551 - Becker , et al. September 4, 2	2012-09-04
Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region with restricted gate contact placement over separating non-diffusion region Grant 8,258,548 - Becker , et al. September 4, 2	2012-09-04
Semiconductor device including two transistors of first type having gates formed by conductors of different length respectively aligned with two transistors of second type having gates formed by conductors of different length Grant 8,258,549 - Becker , et al. September 4, 2	2012-09-04
Semiconductor device including at least six transistor forming linear shapes with at least two transistor forming linear shapes having offset ends Grant 8,258,552 - Becker , et al. September 4, 2	2012-09-04
Semiconductor device including at least six transistor forming linear shapes including at least two transistor forming linear shapes having different extension distances beyond gate contact Grant 8,258,550 - Becker , et al. September 4, 2	2012-09-04
Semiconductor device with linearly restricted gate level region including two transistors of first type and two transistors of second type with offset gate contacts Grant 8,258,547 - Becker , et al. September 4, 2	2012-09-04
Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region and having at least two gate contacts positioned outside separating non-diffusion region Grant 8,253,173 - Becker , et al. August 28, 2	2012-08-28
Semiconductor device with linearly restricted gate level region including four serially connected transistors of first type and four serially connected transistors of second type separated by non-diffusion region Grant 8,253,172 - Becker , et al. August 28, 2	2012-08-28
Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same Grant 8,245,180 - Smayling , et al. August 14, 2	2012-08-14
Methods for defining and utilizing sub-resolution features in linear topology Grant 8,225,239 - Reed , et al. July 17, 2	2012-07-17
Integrated circuit including gate electrode level region including at least three linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type Grant 8,217,428 - Becker , et al. July 10, 2	2012-07-10
Electrodes of transistors with at least two linear-shaped conductive structures of different length Grant 8,207,053 - Becker , et al. June 26, 2	2012-06-26
Integrated circuit including gate electrode level region including at least four linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different type Grant 8,198,656 - Becker , et al. June 12, 2	2012-06-12
Scalable Meta-Data Objects App 20120144360 - Smayling; Michael C. ; et al.	2012-06-07
Methods for linewidth modification and apparatus implementing the same App 20120118854 - Smayling; Michael C. ; et al.	2012-05-17
Integrated circuit including at least three linear-shaped conductive structures of different length each forming gate of different transistor Grant 8,138,525 - Becker , et al. March 20, 2	2012-03-20
Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned ends Grant 8,134,185 - Becker , et al. March 13, 2	2012-03-13
Integrated circuit including linear-shaped conductive structures that have gate portions and extending portions of different size Grant 8,134,183 - Becker , et al. March 13, 2	2012-03-13
Integrated circuit including at least three linear-shaped conductive structures at equal pitch including linear-shaped conductive structure having non-gate portion length greater than gate portion length Grant 8,134,186 - Becker , et al. March 13, 2	2012-03-13
Integrated circuit having gate electrode level region including at least four linear-shaped conductive structures with some outer-contacted linear-shaped conductive structures having larger outer extending portion than inner extending portion Grant 8,134,184 - Becker , et al. March 13, 2	2012-03-13
Integrated circuit with gate electrode level including at least four linear-shaped conductive structures of equal length and equal pitch with linear-shaped conductive structure forming one transistor Grant 8,129,755 - Becker , et al. March 6, 2	2012-03-06
Integrated circuit including a linear-shaped conductive structure forming one gate electrode and having length greater than or equal to one-half the length of linear-shaped conductive structure forming two gate electrodes Grant 8,129,752 - Becker , et al. March 6, 2	2012-03-06
Integrated circuit with gate electrode level including at least six linear-shaped conductive structures forming gate electrodes of transisters with at least one pair of linear-shaped conductive structures having offset ends Grant 8,129,754 - Becker , et al. March 6, 2	2012-03-06
Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes and including four conductive contacting structures having at least two different connection distances Grant 8,129,751 - Becker , et al. March 6, 2	2012-03-06
Method of fabricating integrated circuit including at least six linear-shaped conductive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length Grant 8,129,819 - Becker , et al. March 6, 2	2012-03-06
Integrated circuit including at least six linear-shaped conductive structive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different length Grant 8,129,757 - Becker , et al. March 6, 2	2012-03-06
Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two different extension distances beyond conductive contacting structures Grant 8,129,756 - Becker , et al. March 6, 2	2012-03-06
Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two linear-shaped conductive structures of different length Grant 8,129,750 - Becker , et al. March 6, 2	2012-03-06
Integrated circuit including gate electrode level region including at least seven linear-shaped conductive structures of equal length positioned at equal pitch with at least two linear-shaped conductive structures each forming one transistor and having extending portion sized greater than gate porti Grant 8,129,753 - Becker , et al. March 6, 2	2012-03-06
Integrated circuit device with linearly defined gate electrode level region and shared diffusion region of first type connected to shared diffusion region of second type through at least two interconnect levels Grant 8,110,854 - Becker , et al. February 7, 2	2012-02-07
Integrated circuit device with gate level region including non-gate linear conductive segment positioned within 965 nanometers of four transistors of first type and four transistors of second type Grant 8,101,975 - Becker , et al. January 24, 2	2012-01-24
Method for fabricating integrated circuit with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level Grant 8,088,682 - Becker , et al. January 3, 2	2012-01-03
Integrated circuit with gate electrode level region including at least four linear-shaped conductive structures forming gate electrodes of transistors and including extending portions of at least two different sizes Grant 8,089,100 - Becker , et al. January 3, 2	2012-01-03
Method for fabricating integrated circuit with gate electrode level portion including at least two complementary transistor forming linear conductive segments and at least one non-gate linear conductive segment Grant 8,088,679 - Becker , et al. January 3, 2	2012-01-03
Integrated circuit device and associated layout including gate electrode level region of 965 NM radius with linear-shaped conductive segments on fixed pitch Grant 8,089,099 - Becker , et al. January 3, 2	2012-01-03
Integrated circuit device with gate level region including at least three linear-shaped conductive segments having offset line ends and forming three transistors of first type and one transistor of second type Grant 8,089,103 - Becker , et al. January 3, 2	2012-01-03
Method for fabricating integrated circuit having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitch Grant 8,089,102 - Becker , et al. January 3, 2	2012-01-03
Integrated circuit with gate electrode level region including multiple linear-shaped conductive structures forming gate electrodes of transistors and including uniformity extending portions of different size Grant 8,089,104 - Becker , et al. January 3, 2	2012-01-03
Method for fabricating integrated circuit having at least three linear-shaped gate electrode level conductive features of equal length positioned side-by-side at equal pitch Grant 8,088,680 - Becker , et al. January 3, 2	2012-01-03
Integrated circuit device with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate level Grant 8,089,101 - Becker , et al. January 3, 2	2012-01-03
Method for fabricating integrated circuit including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear condcutive segment Grant 8,088,681 - Becker , et al. January 3, 2	2012-01-03
Integrated circuit device and associated layout including linear gate electrodes of different transistor types next to linear-shaped non-gate conductive segment Grant 8,089,098 - Becker , et al. January 3, 2	2012-01-03
Integrated circuit device and associated layout including two pairs of co-aligned complementary gate electrodes with offset gate contact structures Grant 8,072,003 - Becker , et al. December 6, 2	2011-12-06
Methods, Structures, and Designs for Self-Aligning Local Interconnects used in Integrated Circuits App 20110278681 - Smayling; Michael C. ; et al.	2011-11-17
Semiconductor device having at least three linear-shaped electrode level conductive features of equal length positioned side-by-side at equal pitch Grant 8,058,671 - Becker , et al. November 15, 2	2011-11-15
Semiconductor device having two pairs of transistors of different types formed from shared linear-shaped conductive features with intervening transistors of common type on equal pitch Grant 8,035,133 - Becker , et al. October 11, 2	2011-10-11
Integrated circuit device and associated layout including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear conductive segment Grant 8,030,689 - Becker , et al. October 4, 2	2011-10-04
Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode-to-gate electrode connection through single interconnect level and common node connection through different interconnect level Grant 8,022,441 - Becker , et al. September 20, 2	2011-09-20
Methods, structures, and designs for self-aligning local interconnects used in integrated circuits Grant 7,994,545 - Smayling , et al. August 9, 2	2011-08-09
Semiconductor device having linear-shaped gate electrodes of different transistor types with uniformity extending portions of different lengths Grant 7,989,847 - Becker , et al. August 2, 2	2011-08-02
Semiconductor device having at least four side-by-side electrodes of equal length and equal pitch with at least two transistor connections to power or ground Grant 7,989,848 - Becker , et al. August 2, 2	2011-08-02
Integrated Circuit Device Including Dynamic Array Section with Gate Level Having Linear Conductive Features on at Least Three Side-by-Side Lines and Uniform Line End Spacings App 20110175144 - BECKER; SCOTT T. ; et al.	2011-07-21
Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods Grant 7,979,829 - Smayling July 12, 2	2011-07-12
Methods for Designing Semiconductor Device with Dynamic Array Section App 20110161909 - Becker; Scott T. ; et al.	2011-06-30
Methods and apparatus for multi-exposure patterning Grant 7,965,382 - Smayling June 21, 2	2011-06-21
Semiconductor device and associated layout having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitch Grant 7,952,119 - Becker , et al. May 31, 2	2011-05-31
Semiconductor device having 1965 nm gate electrode level region including at least four active linear conductive segments and at least one non-gate linear conductive segment Grant 7,948,012 - Becker , et al. May 24, 2	2011-05-24
Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch Grant 7,948,013 - Becker , et al. May 24, 2	2011-05-24
Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments Grant 7,943,967 - Becker , et al. May 17, 2	2011-05-17
Integrated circuit and associated layout with gate electrode level portion including at least two complimentary transistor forming linear conductive segments and at least one non-gate linear conductive segment Grant 7,943,966 - Becker , et al. May 17, 2	2011-05-17
Semiconductor Device with Dynamic Array Sections Defined and Placed According to Manufacturing Assurance Halos App 20110108891 - Becker; Scott T. ; et al.	2011-05-12
Semiconductor Device with Dynamic Array Sections Defined and Placed According to Manufacturing Assurance Halos App 20110108890 - Becker; Scott T. ; et al.	2011-05-12
Diffusion variability control and transistor device sizing using threshold voltage implant Grant 7,939,898 - Smayling , et al. May 10, 2	2011-05-10
Semiconductor device and associated layouts including linear conductive segments having non-gate extension portions Grant 7,932,544 - Becker , et al. April 26, 2	2011-04-26
Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers Grant 7,932,545 - Becker , et al. April 26, 2	2011-04-26
Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level Grant 7,923,757 - Becker , et al. April 12, 2	2011-04-12
Semiconductor device with dynamic array section Grant 7,917,879 - Becker , et al. March 29, 2	2011-03-29
Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode connection through single interconnect level Grant 7,910,959 - Becker , et al. March 22, 2	2011-03-22
Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segment Grant 7,910,958 - Becker , et al. March 22, 2	2011-03-22
Semiconductor device and associated layouts having transistors formed from six linear conductive segments with intervening diffusion contact restrictions Grant 7,906,801 - Becker , et al. March 15, 2	2011-03-15
Methods for designing semiconductor device with dynamic array section Grant 7,908,578 - Becker , et al. March 15, 2	2011-03-15
Methods and apparatus for detecting defects in interconnect structures Grant 7,901,953 - Smayling , et al. March 8, 2	2011-03-08
Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same Grant 7,888,705 - Becker , et al. February 15, 2	2011-02-15
Integrated Circuit Cell Library with Cell-Level Process Compensation Technique (PCT) Application and Associated Methods App 20100306719 - Smayling; Michael C.	2010-12-02
Dynamic array architecture Grant 7,842,975 - Becker , et al. November 30, 2	2010-11-30
Methods, Structures, and Designs for Self-Aligning Local Interconnects used in Integrated Circuits App 20100252896 - Smayling; Michael C. ; et al.	2010-10-07
Methods, structures and designs for self-aligning local interconnects used in integrated circuits Grant 7,763,534 - Smayling , et al. July 27, 2	2010-07-27
Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors App 20100096671 - Becker; Scott T. ; et al.	2010-04-22
Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors App 20100037194 - Becker; Scott T. ; et al.	2010-02-11
Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions App 20100032726 - Becker; Scott T. ; et al.	2010-02-11
Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors App 20100032724 - Becker; Scott T. ; et al.	2010-02-11
Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors App 20100032722 - Becker; Scott T. ; et al.	2010-02-11
Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors App 20100032723 - Becker; Scott T. ; et al.	2010-02-11
Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors App 20100032721 - Becker; Scott T. ; et al.	2010-02-11
Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors and Having Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region App 20100037195 - Becker; Scott T. ; et al.	2010-02-11
Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors App 20100025733 - Becker; Scott T. ; et al.	2010-02-04
Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors App 20100025731 - Becker; Scott T. ; et al.	2010-02-04
Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors App 20100025735 - Becker; Scott T. ; et al.	2010-02-04
Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors App 20100025732 - Becker; Scott T. ; et al.	2010-02-04
Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors App 20100025734 - Becker; Scott T. ; et al.	2010-02-04
Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors App 20100025736 - Becker; Scott T. ; et al.	2010-02-04
Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication App 20100031211 - Reed; Brian ; et al.	2010-02-04
Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region App 20100023907 - Becker; Scott T. ; et al.	2010-01-28
Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors App 20100023911 - Becker; Scott T. ; et al.	2010-01-28
Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing App 20100023906 - Becker; Scott T. ; et al.	2010-01-28
Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing App 20100019286 - Becker; Scott T. ; et al.	2010-01-28
Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks App 20100019281 - Becker; Scott T. ; et al.	2010-01-28
Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing App 20100019288 - Becker; Scott T. ; et al.	2010-01-28
Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors App 20100019283 - Becker; Scott T. ; et al.	2010-01-28
Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors and Having Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region App 20100023908 - Becker; Scott T. ; et al.	2010-01-28
Cell of Semiconductor Device Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors App 20100019284 - Becker; Scott T. ; et al.	2010-01-28
Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors App 20100019285 - Becker; Scott T. ; et al.	2010-01-28
Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks App 20100019282 - Becker; Scott T. ; et al.	2010-01-28
Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks App 20100019280 - Becker; Scott T. ; et al.	2010-01-28
Cell of Semiconductor Device Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing App 20100019287 - Becker; Scott T. ; et al.	2010-01-28
Layout of Cell of Semiconductor Device Having Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors App 20100017769 - Becker; Scott T. ; et al.	2010-01-21
Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors App 20100012985 - Becker; Scott T. ; et al.	2010-01-21
Layout of Cell of Semiconductor Device Having Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region App 20100017768 - Becker; Scott T. ; et al.	2010-01-21
Layout of Cell of Semiconductor Device Having Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors App 20100017771 - Becker; Scott T. ; et al.	2010-01-21
Layout of Cell of Semiconductor Device Having Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors with Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region App 20100017770 - Becker; Scott T. ; et al.	2010-01-21
Layout of Cell of Semiconductor Device Having Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors with Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region App 20100017772 - Becker; Scott T. ; et al.	2010-01-21
Layout of Cell of Semiconductor Device Having Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks App 20100017767 - Becker; Scott T. ; et al.	2010-01-21
Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions App 20100012982 - Becker; Scott T. ; et al.	2010-01-21
Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors App 20100017766 - Becker; Scott T. ; et al.	2010-01-21
Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors App 20100012983 - Becker; Scott T. ; et al.	2010-01-21
Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors App 20100012984 - Becker; Scott T. ; et al.	2010-01-21
Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions App 20100012981 - Becker; Scott T. ; et al.	2010-01-21
Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors App 20100012986 - Becker; Scott T. ; et al.	2010-01-21
Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors App 20100011329 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors App 20100011327 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions App 20100006902 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Layout Having Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors App 20100011332 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Portion Having Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions App 20100006903 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors App 20100006898 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors App 20100006948 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions App 20100006901 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors App 20100006950 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Layout Having Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing with Corresponding Non-Symmetric Diffusion Regions App 20100011330 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors App 20100006947 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Portion Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors App 20100006899 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Portion Having Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors App 20100006900 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions App 20100006986 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing with Corresponding Non-Symmetric Diffusion Regions App 20100011331 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors App 20100006897 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors App 20100011328 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors App 20100006951 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Layout Having Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors App 20100011333 - Becker; Scott T. ; et al.	2010-01-14
Semiconductor Device Layout Having Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions App 20100001321 - Becker; Scott T. ; et al.	2010-01-07
Methods for Defining and Using Co-Optimized Nanopatterns for Integrated Circuit Design and Apparatus Implementing Same App 20090294981 - Smayling; Michael C. ; et al.	2009-12-03
Methods for Defining and Utilizing Sub-Resolution Features in Linear Topology App 20090300574 - Reed; Brian ; et al.	2009-12-03
Methods for risk-informed chip layout generation Grant 7,590,968 - Becker , et al. September 15, 2	2009-09-15
Super-Self-Aligned Contacts and Method for Making the Same App 20090152734 - Smayling; Michael C.	2009-06-18
Diffusion Variability Control and Transistor Device Sizing Using Threshold Voltage Implant App 20090127636 - Smayling; Michael C. ; et al.	2009-05-21
Methods, Structures And Designs For Self-aligning Local Interconnects Used In Integrated Circuits App 20090108360 - Smayling; Michael C. ; et al.	2009-04-30
Methods and Systems for Process Compensation Technique Acceleration App 20090100396 - Smayling; Michael C. ; et al.	2009-04-16
Methods And Apparatus For Detecting Defects In Interconnect Structures App 20090066358 - Smayling; Michael C. ; et al.	2009-03-12
Semiconductor Device with Dynamic Array Section App 20090032967 - Becker; Scott T. ; et al.	2009-02-05
Methods for Defining Dynamic Array Section with Manufacturing Assurance Halo and Apparatus Implementing the Same App 20090032898 - Becker; Scott T. ; et al.	2009-02-05
Methods for Designing Semiconductor Device with Dynamic Array Section App 20090037864 - Becker; Scott T. ; et al.	2009-02-05
Lithography Track Systems And Methods For Electronic Device Manufacturing App 20090023101 - Smayling; Michael C.	2009-01-22
Methods And Apparatus For Depositing An Anti-reflection Coating App 20090023230 - Smayling; Michael C.	2009-01-22
Dynamic Array Architecture App 20090014811 - Becker; Scott T. ; et al.	2009-01-15
Method and apparatus for characterizing features formed on a substrate Grant 7,459,319 - Smayling , et al. December 2, 2	2008-12-02
Dynamic array architecture Grant 7,446,352 - Becker , et al. November 4, 2	2008-11-04
Integrated Circuit Cell Library for Multiple Patterning App 20080222587 - Smayling; Michael C. ; et al.	2008-09-11
Package For Housing A Semiconductor Chip And Method For Operating A Semiconductor Chip At Less-than-ambient Temperatures App 20080190119 - SMAYLING; MICHAEL C.	2008-08-14
Method And Test-structure For Determining An Offset Between Lithographic Masks App 20080192253 - Yang; Susie Xiuru ; et al.	2008-08-14
Methods And Apparatus For Multi-exposure Patterning App 20080143983 - Smayling; Michael C.	2008-06-19
Early detection of metal wiring reliability using a noise spectrum Grant 7,332,360 - Smayling , et al. February 19, 2	2008-02-19
Dynamic Array Architecture App 20070210391 - Becker; Scott T. ; et al.	2007-09-13
Method And Apparatus For Characterizing Features Formed On A Substrate App 20070145998 - Smayling; Michael C. ; et al.	2007-06-28
Method of making floating-gate memory-cell array with digital logic transistors Grant RE39,697 - Marotta , et al. June 19, 2	2007-06-19
Integrated circuit layout methods App 20070074142 - Smayling; Michael C. ; et al.	2007-03-29
Method and apparatus for characterizing features formed on a substrate Grant 7,196,350 - Smayling , et al. March 27, 2	2007-03-27
Method and apparatus for characterizing features formed on a substrate App 20060255825 - Smayling; Michael C. ; et al.	2006-11-16
Flash Gate Stack Notch To Improve Coupling Ratio App 20060234449 - Smayling; Michael C.	2006-10-19
Line edge roughness reduction compatible with trimming App 20060205223 - Smayling; Michael C.	2006-09-14
Early detection of metal wiring reliability using a noise spectrum App 20060088949 - Smayling; Michael C. ; et al.	2006-04-27
Flash gate stack notch to improve coupling ratio App 20060081908 - Smayling; Michael C.	2006-04-20
Detection and feed forward of exposed area to improve plasma etching App 20060065626 - Smayling; Michael C.	2006-03-30
Multiple image photolithography system and method Grant 6,741,333 - Smayling , et al. May 25, 2	2004-05-25
Integrated equipment set for forming shallow trench isolation regions App 20030220708 - Sahin, Turgut ; et al.	2003-11-27
Multiple image photolithography system and method App 20030210384 - Smayling, Michael C. ; et al.	2003-11-13
Flash memory segmentation Grant 6,262,914 - Smayling , et al. July 17, 2	2001-07-17
Integrated circuits, transistors, data processing systems, printed wiring boards, digital computers, smart power devices, and processes of manufacture Grant 6,246,102 - Sauerbrey , et al. June 12, 2	2001-06-12
Flash memory margin mode enhancements Grant 6,191,976 - Smayling , et al. February 20, 2	2001-02-20
Flash memory block or sector clear operation Grant 6,118,706 - Smayling , et al. September 12, 2	2000-09-12
Intergrated circuit combining high frequency bipolar and high power CMOS transistors Grant 5,917,222 - Smayling , et al. June 29, 1	1999-06-29
Method of making floating-gate memory-cell array with digital logic transistors Grant 5,907,171 - Santin , et al. May 25, 1	1999-05-25
Low voltage, high current pump for flash memory Grant 5,874,849 - Marotta , et al. February 23, 1	1999-02-23
Programmable and convertible non-volatile memory array Grant 5,844,839 - Smayling , et al. December 1, 1	1998-12-01
High efficiency, high voltage, low current charge pump Grant 5,815,026 - Santin , et al. September 29, 1	1998-09-29
LDMOS transistors, systems and methods Grant 5,811,850 - Smayling , et al. September 22, 1	1998-09-22
Method for current ballasting and busing over active device area using a multi-level conductor process Grant 5,801,091 - Efland , et al. September 1, 1	1998-09-01
Method for detecting defects in semiconductor insulators Grant 5,798,649 - Smayling , et al. August 25, 1	1998-08-25
Intergrated circuit combining high frequency bipolar and high power CMOS transistors Grant 5,767,551 - Smayling , et al. June 16, 1	1998-06-16
Programmable and convertible non-volatile memory array Grant 5,732,021 - Smayling , et al. March 24, 1	1998-03-24
Programmable memory verify "0" and verify "1" circuit and method Grant 5,715,195 - Smayling , et al. February 3, 1	1998-02-03
EEPROM with enhanced reliability by selectable V.sub.PP for write and erase Grant 5,703,807 - Smayling , et al. December 30, 1	1997-12-30
Integrated circuits formed in radiation sensitive material and method of forming same Grant 5,691,089 - Smayling November 25, 1	1997-11-25
Integrated circuits, transistors, data processing systems, printed wiring boards, digital computers, smart power devices, and processes of manufacture Grant 5,689,428 - Sauerbrey , et al. November 18, 1	1997-11-18
Transistor having reduced hot carrier implantation Grant 5,681,768 - Smayling , et al. October 28, 1	1997-10-28
Transistor having reduced hot carrier implantation Grant 5,679,968 - Smayling , et al. October 21, 1	1997-10-21
Integrated circuits formed in radiation sensitive material and method of forming same Grant 5,677,041 - Smayling October 14, 1	1997-10-14
Device having current ballasting and busing over active area using a multi-level conductor process Grant 5,665,991 - Efland , et al. September 9, 1	1997-09-09
Systems utilizing a single chip microcontroller having non-volatile memory devices and power devices Grant 5,642,295 - Smayling June 24, 1	1997-06-24
Windowed and segmented linear geometry source cell for power DMOS processes Grant 5,585,657 - Efland , et al. December 17, 1	1996-12-17
Method of fabricating lateral double diffused MOS (LDMOS) transistors Grant 5,585,294 - Smayling , et al. December 17, 1	1996-12-17
Low voltage flash EEPROM C-cell using fowler-nordheim tunneling Grant 5,557,569 - Smayling , et al. September 17, 1	1996-09-17
Non-volatile memory cell and level shifter Grant 5,515,319 - Smayling , et al. May 7, 1	1996-05-07
Gated thyristor and process for its simultaneous fabrication with high- and low-voltage semiconductor devices, integrated circuit containing the same, systems and methods. Grant 5,504,451 - Smayling , et al. April 2, 1	1996-04-02
Low voltage Fowler-Nordheim flash EEPROM memory array utilizing single level poly cells Grant 5,504,706 - D'Arrigo , et al. April 2, 1	1996-04-02
Flash EEPROM array with P-tank insulated from substrate by deep N-tank Grant 5,504,708 - Santin , et al. April 2, 1	1996-04-02
Planar process using common alignment marks for well implants Grant 5,500,392 - Reynolds , et al. March 19, 1	1996-03-19
Memory array utilizing low voltage Fowler-Nordheim Flash EEPROM cell Grant 5,467,307 - D'Arrigo , et al. November 14, 1	1995-11-14
Low voltage flash EEPROM memory cell with merge select transistor and non-stacked gate structure Grant 5,432,740 - D'Arrigo , et al. July 11, 1	1995-07-11
Process for simultaneously fabricating a bipolar transistor and a field-effect transistor Grant 5,429,959 - Smayling July 4, 1	1995-07-04
Process for simultaneously fabricating an insulated gate field-effect transistor and a bipolar transistor Grant 5,407,844 - Smayling , et al. April 18, 1	1995-04-18
Method of forming a charge pump circuit Grant 5,364,801 - Smayling , et al. November 15, 1	1994-11-15
Devices for non-volatile memory, systems and methods Grant 5,355,007 - Smayling October 11, 1	1994-10-11
LDMOS transistor with self-aligned source/backgate and photo-aligned gate Grant 5,348,895 - Smayling , et al. September 20, 1	1994-09-20
Method and apparatus for integrated circuit design Grant 5,319,564 - Smayling , et al. * June 7, 1	1994-06-07
Method of forming insulated gate field-effect transistors Grant 5,275,961 - Smayling , et al. January 4, 1	1994-01-04
Vertical and lateral insulated-gate, field-effect transistors, systems and methods Grant 5,272,098 - Smayling , et al. December 21, 1	1993-12-21
Method and apparatus for integrated circuit design Grant 5,245,543 - Smayling , et al. September 14, 1	1993-09-14
Method of making LDMOS transistor with self-aligned source/backgate and photo-aligned gate Grant 5,242,841 - Smayling , et al. September 7, 1	1993-09-07
Circuit and method for forming a non-volatile memory cell Grant 5,225,700 - Smayling July 6, 1	1993-07-06
Gated thyristor and process for its simultaneous fabrication with high- and low-voltage semiconductor devices Grant 5,204,541 - Smayling , et al. April 20, 1	1993-04-20