U.S. patent application number 15/457997 was filed with the patent office on 2017-06-29 for semiconductor chip including integrated circuit defined within dynamic array section.
The applicant listed for this patent is Tela Innovations, Inc.. Invention is credited to Scott T. Becker, Michael C. Smayling.
Application Number | 20170186772 15/457997 |
Document ID | / |
Family ID | 40337325 |
Filed Date | 2017-06-29 |
United States Patent
Application |
20170186772 |
Kind Code |
A1 |
Becker; Scott T. ; et
al. |
June 29, 2017 |
Semiconductor Chip Including Integrated Circuit Defined Within
Dynamic Array Section
Abstract
A semiconductor chip includes four linear-shaped conductive
structures that each form a gate electrode of corresponding
transistor of a first transistor type and a gate electrode of a
corresponding transistor of a second transistor type. First and
second ones of the four linear-shaped conductive structures are
positioned to have their lengthwise-oriented centerlines separated
by a gate electrode pitch. Third and fourth ones of the four
linear-shaped conductive structures are also positioned to have
their lengthwise-oriented centerlines separated by the gate
electrode pitch. The first and third ones of the four linear-shaped
conductive structures are positioned to have their
lengthwise-oriented centerlines co-aligned and are separated by a
first end-to-end spacing. The second and fourth ones of the four
linear-shaped conductive structures are positioned to have their
lengthwise-oriented centerlines co-aligned and are separated by a
second end-to-end spacing substantially equal in size to the first
end-to-end spacing.
Inventors: |
Becker; Scott T.; (Scotts
Valley, CA) ; Smayling; Michael C.; (Fremont,
CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Tela Innovations, Inc. |
Los Gatos |
CA |
US |
|
|
Family ID: |
40337325 |
Appl. No.: |
15/457997 |
Filed: |
March 13, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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14276528 |
May 13, 2014 |
9595515 |
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15457997 |
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13047474 |
Mar 14, 2011 |
8756551 |
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14276528 |
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|
12013356 |
Jan 11, 2008 |
7908578 |
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13047474 |
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60963364 |
Aug 2, 2007 |
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60972394 |
Sep 14, 2007 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
Y02P 90/02 20151101;
H01L 2027/11874 20130101; Y02P 90/265 20151101; H01L 23/5226
20130101; H01L 2027/11866 20130101; H01L 27/11807 20130101; H01L
27/11803 20130101; H01L 27/0207 20130101; G06F 2119/18 20200101;
H01L 23/528 20130101; H01L 2027/11888 20130101; G06F 30/39
20200101; H01L 2027/1182 20130101 |
International
Class: |
H01L 27/118 20060101
H01L027/118; G06F 17/50 20060101 G06F017/50; H01L 23/522 20060101
H01L023/522; H01L 27/02 20060101 H01L027/02; H01L 23/528 20060101
H01L023/528 |
Claims
1. A semiconductor chip, comprising: a region including at least
nine gate electrode tracks, the at least nine gate electrode tracks
positioned such that a distance as measured perpendicular to the at
least nine gate electrode tracks and between any two of the at
least nine gate electrode tracks is substantially equal to an
integer multiple of a gate electrode pitch, each of the at least
nine gate electrode tracks including one or more conductive
segments, the conductive segments of the at least nine gate
electrode tracks including a first conductive segment that forms a
gate electrode of a first transistor of a first transistor type,
the conductive segments of the at least nine gate electrode tracks
including a second conductive segment that forms a gate electrode
of a first transistor of a second transistor type, the conductive
segments of the at least nine gate electrode tracks including a
third conductive segment that forms a gate electrode of a second
transistor of the first transistor type, the conductive segments of
the at least nine gate electrode tracks including a fourth
conductive segment that forms a gate electrode of a second
transistor of the second transistor type, the conductive segments
of the at least nine gate electrode tracks including a fifth
conductive segment that forms a gate electrode of a third
transistor of the first transistor type, the conductive segments of
the at least nine gate electrode tracks including a sixth
conductive segment that forms a gate electrode of a third
transistor of the second transistor type, the conductive segments
of the at least nine gate electrode tracks including a seventh
conductive segment that forms a gate electrode of a fourth
transistor of the first transistor type, the conductive segments of
the at least nine gate electrode tracks including an eighth
conductive segment that forms a gate electrode of a fourth
transistor of the second transistor type, the first and third
conductive segments separated by a center-to-center distance as
measured perpendicular to the at least nine gate electrode tracks
substantially equal to the gate electrode pitch, the fourth and
sixth conductive segments separated by a center-to-center distance
as measured perpendicular to the at least nine gate electrode
tracks substantially equal to the gate electrode pitch.
Description
CLAIM OF PRIORITY
[0001] This application is a continuation application under 35
U.S.C. 120 of prior U.S. application Ser. No. 14/276,528, filed May
13, 2014, which is a continuation application under 35 U.S.C. 120
of prior U.S. application Ser. No. 13/047,474, filed Mar. 14, 2011,
issued as U.S. Pat. No. 8,756,551, on Jun. 17, 2014, which is a
continuation application under 35 U.S.C. 120 of prior U.S.
application Ser. No. 12/013,356, filed Jan. 11, 2008, issued as
U.S. Pat. No. 7,908,578, on Mar. 15, 2011, which 1) claims priority
under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No.
60/963,364, filed Aug. 2, 2007, and 2) claims priority under 35
U.S.C. 119(e) to U.S. Provisional Patent Application No.
60/972,394, filed Sep. 14, 2007. The disclosure of each
above-identified patent application is incorporated herein by
reference in its entirety for all purposes.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0002] This application is also related to U.S. patent application
Ser. No. 11/683,402, filed on Mar. 7, 2007, and entitled "Dynamic
Array Architecture." This application is also related to U.S.
patent application Ser. No. 12/013,342, filed on Jan. 11, 2008, and
entitled "Semiconductor Device with Dynamic Array Section." This
application is also related to U.S. patent application Ser. No.
12/013,366, filed on Jan. 11, 2008, and entitled "Methods for
Defining Dynamic Array Section with Manufacturing Assurance Halo
and Apparatus Implementing the Same."
BACKGROUND
[0003] A push for higher performance and smaller die size drives
the semiconductor industry to reduce circuit chip area by
approximately 50% every two years. The chip area reduction provides
an economic benefit for migrating to newer technologies. The 50%
chip area reduction is achieved by reducing the feature sizes
between 25% and 30%. The reduction in feature size is enabled by
improvements in manufacturing equipment and materials. For example,
improvement in the lithographic process has enabled smaller feature
sizes to be achieved, while improvement in chemical mechanical
polishing (CMP) has in-part enabled a higher number of interconnect
layers.
[0004] In the evolution of lithography, as the minimum feature size
approached the wavelength of the light source used to expose the
feature shapes, unintended interactions occurred between
neighboring features. Today minimum feature sizes are approaching
45 nm (nanometers), while the wavelength of the light source used
in the photolithography process remains at 193 nm. The difference
between the minimum feature size and the wavelength of light used
in the photolithography process is defined as the lithographic gap.
As the lithographic gap grows, the resolution capability of the
lithographic process decreases.
[0005] An interference pattern occurs as each shape on the mask
interacts with the light. The interference patterns from
neighboring shapes can create constructive or destructive
interference. In the case of constructive interference, unwanted
shapes may be inadvertently created. In the case of destructive
interference, desired shapes may be inadvertently removed. In
either case, a particular shape is printed in a different manner
than intended, possibly causing a device failure. Correction
methodologies, such as optical proximity correction (OPC), attempt
to predict the impact from neighboring shapes and modify the mask
such that the printed shape is fabricated as desired. The quality
of the light interaction prediction is declining as process
geometries shrink and as the light interactions become more
complex.
[0006] In view of the foregoing, a solution is needed for managing
lithographic gap issues as technology continues to progress toward
smaller semiconductor device features sizes.
SUMMARY
[0007] In one embodiment, a method is disclosed for designing a
semiconductor chip having one or more functionally interfaced
dynamic array sections. The method includes laying out a virtual
grate for conductive features used to define a gate electrode level
of a dynamic array section. The virtual grate is defined by a
framework of parallel lines defined at a substantially constant
pitch. The method also includes arranging one or more conductive
features along a number of lines of the virtual grate. For each
line of the virtual grate that has multiple conductive features
arranged thereon, an operation is performed to define a gap between
proximate ends of each pair of adjacent conductive features. Each
gap is defined to maintain a substantially consistent separation
between proximate ends of conductive features. Some of the
conductive features are designed to define gate electrodes of
transistor devices of the dynamic array section. The method further
includes defining each conductive feature to be devoid of a
substantial change in direction, such that the conductive features
remain substantially aligned to the framework of parallel lines of
the virtual grate.
[0008] In another embodiment, a method is disclosed for designing a
semiconductor chip having one or more functionally interfaced
dynamic array sections. The method includes defining a dynamic
array section grid on a portion of the chip. The dynamic array
section grid is defined by a virtual network of perpendicular
gridlines projected upon the portion of the chip. The method also
includes defining boundaries of a dynamic array section, such that
each boundary of the dynamic array section aligns with a gridline
of the dynamic array section grid. The dynamic array section
represents a portion of the chip defined according to a dynamic
array architecture. The method further includes defining one or
more diffusion regions to be formed within a substrate portion of
the dynamic array section. The method also includes defining a
plurality of levels of the chip above the substrate portion within
the dynamic array section. More specifically, a virtual grate is
defined for each of the plurality of levels. The virtual grate is
defined by a framework of parallel lines spaced at a substantially
constant pitch. The framework of parallel lines that define the
virtual grate for a particular level is oriented to be
substantially perpendicular to the framework of parallel lines that
define the virtual grate for either a level above or a level below
the particular level. Defining the plurality of levels also
includes defining a number of linear conductive features along the
framework of lines that define the virtual grate in each of the
plurality of levels. Some of the lines that define the virtual
grates in the plurality of levels have defined thereon multiple
linear conductive features having proximate ends separated by a
gap. Each gap is defined to maintain a substantially uniform
distance between proximate ends of linear conductive features
within a portion of a given level of the chip within the dynamic
array section. Each of the number of linear conductive features is
defined to be devoid of a substantial change in direction relative
to the line of the virtual grate along which the linear conductive
feature is defined.
[0009] In another embodiment, a method is disclosed for designing a
dynamic array section of a semiconductor chip. The method includes
defining one or more diffusion regions to be formed within a
substrate portion of the chip. The method also includes defining a
plurality of levels of the dynamic array section above the
substrate portion. Each level is defined to include linear
conductive features arranged along a virtual grate associated with
the level. The virtual grate of each level is defined by a
framework of parallel lines spaced at a substantially constant
pitch. The virtual grates in adjacent levels are oriented to be
perpendicular to each other. The method further includes laying out
a full-length linear conductive feature along a full length of a
number of lines of each virtual grate of each level. The method
also includes segmenting some of the full-length linear conductive
features into a number of linear conductive segments. The
segmenting of a given full-length linear conductive feature is
performed by placing one or more gaps along the given full-length
linear conductive feature, such that the gaps placed within a
region of a given level are uniformly defined. A first portion of
the linear conductive segments are defined to form conductive
elements of an electronic circuit. A remaining portion of the
linear conductive segments are defined to support manufacturing of
the first portion and do not form conductive elements of the
electronic circuit.
[0010] In another embodiment, a method is disclosed for designing
an integrated circuit device. The method includes placing a first
transistor of a first transistor type within a gate electrode
level. The method also includes placing a second transistor of the
first transistor type within the gate electrode level. The method
also includes placing a third transistor of the first transistor
type within the gate electrode level. The method also includes
placing a fourth transistor of the first transistor type within the
gate electrode level. Each of the first, second, third, and fourth
transistors of the first transistor type includes a respective
linear-shaped gate electrode segment positioned to extend
lengthwise in a first direction. Also, the first, second, third,
and fourth transistors of the first transistor type are placed
according to a substantially equal centerline-to-centerline spacing
as measured perpendicular to the first direction between
centerlines of adjacently placed linear-shaped gate electrode
segments. The method also includes placing a first transistor of a
second transistor type within a gate electrode level. The method
also includes placing a second transistor of the second transistor
type within the gate electrode level. The method also includes
placing a third transistor of the second transistor type within the
gate electrode level. The method also includes placing a fourth
transistor of the second transistor type within the gate electrode
level. Each of the first, second, third, and fourth transistors of
the second transistor type includes a respective linear-shaped gate
electrode segment positioned to extend lengthwise in the first
direction. Also, the first, second, third, and fourth transistors
of the second transistor type are placed according to the
substantially equal centerline-to-centerline spacing as measured
perpendicular to the first direction. The method further includes
placing a first linear conductive segment within the gate electrode
level to electrically connect the gate electrode of the first
transistor of the first transistor type to the gate electrode of
the first transistor of the second transistor type. The method also
includes placing a second linear conductive segment within the gate
electrode level to electrically connect the gate electrode of the
fourth transistor of the first transistor type to the gate
electrode of the fourth transistor of the second transistor type.
The method also includes placing a third linear conductive segment
beside either the first linear conductive segment or the second
linear conductive segment according to the substantially equal
centerline-to-centerline spacing as measured perpendicular to the
first direction. The first, second, and third linear conductive
segments extend in the first direction parallel to each other.
[0011] In another embodiment, a method is disclosed for designing
an integrated circuit device. The method includes placing a first
transistor of a first transistor type within a gate electrode
level. The first transistor of the first transistor type includes a
linear-shaped gate electrode segment positioned to extend
lengthwise in a first direction. The method also includes placing a
first transistor of a second transistor type within a gate
electrode level. The first transistor of the second transistor type
includes a linear-shaped gate electrode segment positioned to
extend lengthwise in the first direction. The linear-shaped gate
electrodes of the first transistor of the first transistor type and
the first transistor of the second transistor type are
substantially co-aligned in the first direction. The method also
includes placing a first linear conductive segment within the gate
electrode level to electrically connect the linear-shaped gate
electrode of the first transistor of the first transistor type to
the linear-shaped gate electrode of the first transistor of the
second transistor type. The method further includes placing a
second linear conductive segment next to, spaced apart from, and
parallel to the first linear conductive segment. The second linear
conductive segment does not form a gate electrode of a transistor
device.
[0012] In another embodiment, a method is disclosed for designing
an integrated circuit device. The method includes placing a first
transistor of a first transistor type within a gate electrode
level. The first transistor of the first transistor type includes a
first linear-shaped gate electrode defined to extend lengthwise in
a first direction. The method also includes placing a second
transistor of the first transistor type within the gate electrode
level next to and spaced apart from the first transistor of the
first transistor type. The second transistor of the first
transistor type includes a second linear-shaped gate electrode
defined to extend lengthwise in the first direction. The method
also includes placing a third transistor of the first transistor
type within the gate electrode level next to and spaced apart from
the second transistor of the first transistor type. The third
transistor of the first transistor type includes a third
linear-shaped gate electrode defined to extend lengthwise in the
first direction. Each of the first, second, and third transistors
of the first transistor type are placed according to a
substantially equal centerline-to-centerline spacing as measured
perpendicular to the first direction between centerlines of
adjacently placed linear-shaped gate electrodes. The method also
includes placing a first linear conductive segment to extend
lengthwise in the first direction from the first linear-shaped gate
electrode to an end location as delineated in the first direction.
The method also includes placing a second linear conductive segment
to extend lengthwise in the first direction from the second
linear-shaped gate electrode to the end location as delineated in
the first direction. The method further includes placing a third
linear conductive segment to extend lengthwise in the first
direction from the third linear-shaped gate electrode to the end
location as delineated in the first direction.
[0013] Other aspects and advantages of the invention will become
more apparent from the following detailed description, taken in
conjunction with the accompanying drawings, illustrating by way of
example the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1 is an illustration showing a number of neighboring
layout features and a representation of light intensity used to
render each of the layout features, in accordance with one
embodiment of the present invention;
[0015] FIG. 2 is an illustration showing a generalized stack of
layers used to define a dynamic array architecture, in accordance
with one embodiment of the present invention;
[0016] FIG. 3A is an illustration showing an exemplary base grid to
be projected onto the dynamic array to facilitate definition of the
restricted topology, in accordance with one embodiment of the
present invention;
[0017] FIG. 3B is an illustration showing separate base grids
projected across separate regions of the die, in accordance with an
exemplary embodiment of the present invention;
[0018] FIG. 3C is an illustration showing an exemplary
linear-shaped feature defined to be compatible with the dynamic
array, in accordance with one embodiment of the present
invention;
[0019] FIG. 3D is an illustration showing another exemplary
linear-shaped feature defined to be compatible with the dynamic
array, in accordance with one embodiment of the present
invention;
[0020] FIG. 4 is an illustration showing a diffusion layer layout
of an exemplary dynamic array, in accordance with one embodiment of
the present invention;
[0021] FIG. 5 is an illustration showing a gate electrode layer and
a diffusion contact layer above and adjacent to the diffusion layer
of FIG. 4, in accordance with one embodiment of the present
invention;
[0022] FIG. 6 is an illustration showing a gate electrode contact
layer defined above and adjacent to the gate electrode layer of
FIG. 5, in accordance with one embodiment of the present
invention;
[0023] FIG. 7A is an illustration showing a traditional approach
for making contact to the gate electrode;
[0024] FIG. 7B is an illustration showing a gate electrode contact
defined in accordance with one embodiment of the present
invention;
[0025] FIG. 8A is an illustration showing a metal 1 layer defined
above and adjacent to the gate electrode contact layer of FIG. 6,
in accordance with one embodiment of the present invention;
[0026] FIG. 8B is an illustration showing the metal 1 layer of FIG.
8A with larger track widths for the metal 1 ground and power
tracks, relative to the other metal 1 tracks;
[0027] FIG. 9 is an illustration showing a via 1 layer defined
above and adjacent to the metal 1 layer of FIG. 8A, in accordance
with one embodiment of the present invention;
[0028] FIG. 10 is an illustration showing a metal 2 layer defined
above and adjacent to the via 1 layer of FIG. 9, in accordance with
one embodiment of the present invention;
[0029] FIG. 11 is an illustration showing conductor tracks
traversing the dynamic array in a first diagonal direction relative
to the first and second reference directions (x) and (y), in
accordance with one embodiment of the present invention;
[0030] FIG. 12 is an illustration showing conductor tracks
traversing the dynamic array in a second diagonal direction
relative to the first and second reference directions (x) and (y),
in accordance with one embodiment of the present invention;
[0031] FIG. 13A is an illustration showing an example of a
sub-resolution contact layout used to lithographically reinforce
diffusion contacts and gate electrode contacts, in accordance with
one embodiment of the present invention;
[0032] FIG. 13B is an illustration showing the sub-resolution
contact layout of FIG. 13A with sub-resolution contacts defined to
fill the grid to the extent possible, in accordance with one
embodiment of the present invention;
[0033] FIG. 13C is an illustration showing an example of a
sub-resolution contact layout utilizing various shaped
sub-resolution contacts, in accordance with one embodiment of the
present invention;
[0034] FIG. 13D is an illustration showing an exemplary
implementation of alternate phase shift masking (APSM) with
sub-resolution contacts, in accordance with one embodiment of the
present invention;
[0035] FIG. 14 is an illustration showing a semiconductor chip
structure, in accordance with one embodiment of the present
invention;
[0036] FIG. 15 is an illustration showing an exemplary chip
implementing the dynamic array architecture, in accordance with one
embodiment of the present invention;
[0037] FIG. 16 is an illustration showing a blank canvas of the
dynamic array architecture region, in accordance with one
embodiment of the present invention;
[0038] FIG. 17A is an illustration showing a number of exemplary
dynamic array sections defined within the dynamic array
architecture region, in accordance with one embodiment of the
present invention;
[0039] FIG. 17B is an illustration showing a number of dynamic
array sections defined at a higher vertical position within the
dynamic array architecture region, in accordance with one
embodiment of the present invention;
[0040] FIG. 17C is an illustration showing a side view of the DAS
stack of FIG. 17B, in accordance with one embodiment of the present
invention;
[0041] FIG. 18 is an illustration showing a substrate level of
DAS10, in accordance with one embodiment of the present
invention;
[0042] FIG. 19A is an illustration showing a gate electrode level
virtual grate for the DAS10 example, in accordance with one
embodiment of the present invention;
[0043] FIG. 19A1 is an illustration showing a virtual grate of the
gate electrode level set at a pitch equal to one-half of the
minimum center-to-center spacing between adjacent contacted gate
electrode features, in accordance with one embodiment of the
present invention;
[0044] FIG. 19B is an illustration showing full-length linear
conductive features defined along each line of the gate electrode
level virtual grate of FIG. 19A, in accordance with one embodiment
of the present invention;
[0045] FIG. 19B1 is an illustration showing linear conductive
features defined along various lines of the gate electrode level
virtual grate of FIG. 19A1, in accordance with one embodiment of
the present invention;
[0046] FIG. 19C is an illustration showing a segmentation of the
linear conductive features of FIG. 19B, in accordance with one
embodiment of the present invention;
[0047] FIG. 19D is an illustration showing the gate electrode level
segmented features of FIG. 19C with a region within which a
non-functional linear conductive feature has been eliminated;
[0048] FIG. 20A is an illustration showing a first interconnect
level virtual grate for the DAS10 example, in accordance with one
embodiment of the present invention;
[0049] FIG. 20A1 is an illustration showing a virtual grate of the
first interconnect level set at a pitch equal to one-half of the
minimum center-to-center spacing between adjacent contacted linear
conductive features of the first interconnect level, in accordance
with one embodiment of the present invention;
[0050] FIG. 20B is an illustration showing full-length linear
conductive features defined along each line of the first
interconnect level virtual grate of FIG. 20A, in accordance with
one embodiment of the present invention;
[0051] FIG. 20B1 is an illustration showing linear conductive
features defined along various lines of the first interconnect
level virtual grate of FIG. 20A1, in accordance with one embodiment
of the present invention;
[0052] FIG. 20C is an illustration showing a segmentation of the
linear conductive features of FIG. 20B, in accordance with one
embodiment of the present invention;
[0053] FIG. 21A is an illustration showing a second interconnect
level virtual grate for the DAS10 example, in accordance with one
embodiment of the present invention;
[0054] FIG. 21B is an illustration showing the spatial relationship
between the second interconnect level and gate electrode level
virtual grates for the DAS10 example, as defined based on a 3-to-2
pitch relationship between second interconnect level and gate
electrode level conductive features, in accordance with one
embodiment of the present invention;
[0055] FIG. 21C is an illustration showing full-length linear
conductive features defined along each line of the second
interconnect level virtual grate, in accordance with one embodiment
of the present invention;
[0056] FIG. 21D is an illustration showing a segmentation of the
linear conductive features within the second interconnect level, in
accordance with one embodiment of the present invention;
[0057] FIG. 22A is an illustration showing a second interconnect
level virtual grate for the DAS10 example, as defined based on a
4-to-3 pitch relationship between second interconnect level and
gate electrode level conductive features, in accordance with one
embodiment of the present invention;
[0058] FIG. 22B is an illustration showing the spatial relationship
between the second interconnect level and gate electrode level
virtual grates for the dynamic array section, as defined based on a
4-to-3 pitch relationship between second interconnect level and
gate electrode level conductive features, in accordance with one
embodiment of the present invention;
[0059] FIG. 22C is an illustration showing full-length linear
conductive features defined along each line of the second
interconnect level virtual grate, in accordance with one embodiment
of the present invention;
[0060] FIG. 22D is an illustration showing a segmentation of the
linear conductive features of FIG. 22C within the second
interconnect level, in accordance with one embodiment of the
present invention;
[0061] FIG. 23 is an illustration showing the second interconnect
level of FIG. 22D with a number of exemplary via locations
identified thereon, in accordance with one embodiment of the
present invention;
[0062] FIG. 24A is an illustration showing a third interconnect
level virtual grate for the DAS10 example, in accordance with one
embodiment of the present invention;
[0063] FIG. 24B is an illustration showing a spatial relationship
between the third interconnect level and first interconnect level
virtual grates for the DAS10 example, in accordance with one
embodiment of the present invention;
[0064] FIG. 24C is an illustration showing full-length linear
conductive features defined along each line of the third
interconnect level virtual grate, in accordance with one embodiment
of the present invention;
[0065] FIG. 24D is an illustration showing a segmentation of the
linear conductive features within the third interconnect level, in
accordance with one embodiment of the present invention;
[0066] FIG. 25A is an illustration showing a number of exemplary
DASs with their respective manufacturing assurance boundary
compatibility designations, in accordance with one embodiment of
the present invention;
[0067] FIG. 25B is an illustration showing an exemplary assembly of
the DASs of FIG. 25A on a DAS grid according to their respective
manufacturing assurance boundary compatibility designations, in
accordance with one embodiment of the present invention;
[0068] FIG. 25C is an illustration showing an exemplary assembly of
the DASs of FIG. 25A on a DAS grid according to their respective
manufacturing assurance boundary compatibility designations with
intentionally defined empty areas, in accordance with one
embodiment of the present invention;
[0069] FIG. 26A-1 is an illustration showing a level of an
exemplary DAS, in accordance with one embodiment of the present
invention;
[0070] FIG. 26A-2 is an illustration showing the exemplary DAS of
FIG. 26A-1 with its DAS halo region pre-defined to include a number
of reinforcement features, in accordance with one embodiment of the
present invention;
[0071] FIG. 26B-1 is an illustration showing a level of another
exemplary DAS, in accordance with one embodiment of the present
invention;
[0072] FIG. 26B-2 is an illustration showing the exemplary DAS of
FIG. 26B-1 with its DAS halo region pre-defined to include a number
of reinforcement features, in accordance with one embodiment of the
present invention;
[0073] FIG. 26C-1 is an illustration showing an exemplary placement
of the DAS of FIG. 26A-2 and the DAS of FIG. 26B-2 on a DAS grid,
in accordance with one embodiment of the present invention;
[0074] FIG. 26C-2 is an illustration showing an exemplary placement
of the DAS of FIG. 26A-2 and the DAS of FIG. 26B-2 on a DAS grid
without regard to their respective DAS halos, in accordance with
one embodiment of the present invention;
[0075] FIG. 26C-3 is an illustration showing the DAS cluster of
FIG. 26C-2 having a DAS halo boundary defined around the periphery
of the DAS cluster to form a DAS halo region, in accordance with
one embodiment of the present invention;
[0076] FIG. 26C-4 is an illustration showing the defined content of
the DAS halo region of FIG. 26C-3, in accordance with one
embodiment of the present invention;
[0077] FIG. 26C-5 is an illustration showing the particular level
of the DAS cluster of FIG. 26C-4 having a number of DAS
interconnection segments defined therein, in accordance with one
embodiment of the present invention;
[0078] FIG. 26D-1 is an illustration showing a flowchart of a
method for defining a dynamic array architecture region of a
semiconductor chip, in accordance with one embodiment of the
present invention, in accordance with one embodiment of the present
invention;
[0079] FIG. 26D-2 is an illustration showing a flowchart of a
method for defining a dynamic array architecture region of a
semiconductor chip, in accordance with one embodiment of the
present invention;
[0080] FIG. 27A is an illustration showing an exemplary DAS that
defines a logic cell, in accordance with one embodiment of the
present invention;
[0081] FIG. 27B shows a number of instances of the example DAS of
FIG. 27A placed adjacent to each other so as to share DAS
components that extend beyond the DAS boundary, in accordance with
one embodiment of the present invention;
[0082] FIG. 28A is an illustration showing a flowchart of a method
for designing a semiconductor chip having one or more functionally
interfaced dynamic array sections, in accordance with one
embodiment of the present invention;
[0083] FIG. 28B is an illustration showing a continuation of the
flowchart of the method of FIG. 28A, in accordance with one
embodiment of the present invention;
[0084] FIG. 28C is an illustration showing an expansion of the
operation 2809 of FIG. 28B, in accordance with one embodiment of
the present invention;
[0085] FIG. 29A is an illustration showing a flowchart of a method
for designing a semiconductor chip having one or more functionally
interfaced dynamic array sections, in accordance with one
embodiment of the present invention;
[0086] FIG. 29B is an illustration showing an expansion of the
operation 2907 of FIG. 29A, in accordance with one embodiment of
the present invention;
[0087] FIG. 30 is an illustration showing a flowchart of a method
for designing a DAS of a semiconductor chip, in accordance with one
embodiment of the present invention;
[0088] FIG. 31 is an illustration showing a flowchart of a method
for defining a dynamic array section to be manufactured on a
semiconductor chip, in accordance with one embodiment of the
present invention;
[0089] FIG. 32 is an illustration showing a flowchart of a method
for designing a semiconductor chip having one or more functionally
interfaced dynamic array sections, in accordance with one
embodiment of the present invention; and
[0090] FIG. 33 is an illustration showing an example of different
phasings in a second interconnect level of adjacently disposed
logic cells defined within a DAS, in accordance with one embodiment
of the present invention.
DETAILED DESCRIPTION
[0091] In the following description, numerous specific details are
set forth in order to provide a thorough understanding of the
present invention. It will be apparent, however, to one skilled in
the art that the present invention may be practiced without some or
all of these specific details. In other instances, well known
process operations have not been described in detail in order not
to unnecessarily obscure the present invention.
[0092] Generally speaking, a dynamic array architecture is provided
to address semiconductor manufacturing process variability
associated with a continually increasing lithographic gap. In the
area of semiconductor manufacturing, lithographic gap is defined as
the difference between the minimum size of a feature to be defined
and the wavelength of light used to render the feature in the
lithographic process, wherein the feature size is less than the
wavelength of the light. Current lithographic processes utilize a
light wavelength of 193 nm. However, current feature sizes are as
small as 65 nm and are expected to soon approach sizes as small as
45 nm. With a size of 65 nm, the shapes are three times smaller
than the wavelength of the light used to define the shapes. Also,
considering that the interaction radius of light is about five
light wavelengths, it should be appreciated that shapes exposed
with a 193 nm light source will influence the exposure of shapes
approximately 5*193 nm (965 nm) away. When considering the 65 nm
sized features with respect to 90 nm sized features, it should be
appreciated that approximately two times as many 65 nm sizes
features may be within the 965 nm interaction radius of the 193 nm
light source as compared to the 90 nm sized features.
[0093] Due to the increased number of features within the
interaction radius of the light source, the extent and complexity
of light interference contributing to exposure of a given feature
is significant. Additionally, the particular shapes associated with
the features within the interaction radius of the light source
weighs heavily on the type of light interactions that occur.
Traditionally, designers were allowed to define essentially any
two-dimensional topology of feature shapes so long as a set of
design rules were satisfied. For example, in a given layer of the
chip, i.e., in a given mask, the designer may have defined
two-dimensionally varying features having bends that wrap around
each other. When such two-dimensionally varying features are
located in neighboring proximity to each other, the light used to
expose the features will interact in a complex and generally
unpredictable manner. The light interaction becomes increasingly
more complex and unpredictable as the feature sizes and relative
spacing become smaller.
[0094] Traditionally, if a designer follows the established set of
design rules, the resulting product will be manufacturable with a
specified probability associated with the set of design rules.
Otherwise, for a design that violates the set of design rules, the
probability of successful manufacture of the resulting product is
unknown. To address the complex light interaction between
neighboring two-dimensionally varying features, in the interest of
successful product manufacturing, the set of design rules is
expanded significantly to adequately address the possible
combinations of two-dimensionally varying features. This expanded
set of design rules quickly becomes so complicated and unwieldy
that application of the expanded set of design rules becomes
prohibitively time consuming, expensive, and prone to error. For
example, the expanded set of design rules requires complex
verification. Also, the expanded set of design rules may not be
universally applied. Furthermore, manufacturing yield is not
guaranteed even if all design rules are satisfied.
[0095] It should be appreciated that accurate prediction of all
possible light interactions when rendering arbitrarily-shaped
two-dimensional features is generally not feasible. Moreover, as an
alternative to or in combination with expansion of the set of
design rules, the set of design rules may also be modified to
include increased margin to account for unpredictable light
interaction between the neighboring two-dimensionally varying
features. Because the design rules are established in an attempt to
cover the random two-dimensional feature topology, the design rules
may incorporate a significant amount of margin. While addition of
margin in the set of design rules assists with the layout portions
that include the neighboring two-dimensionally varying features,
such global addition of margin causes other portions of the layout
that do not include the neighboring two-dimensionally varying
features to be overdesigned, thus leading to decreased optimization
of chip area utilization and electrical performance.
[0096] In view of the foregoing, it should be appreciated that
semiconductor product yield is reduced as a result of parametric
failures that stem from variability introduced by design-dependent
unconstrained feature topologies, i.e., arbitrary two-dimensionally
varying features disposed in proximity to each other. By way of
example, these parametric failures may result from failure to
accurately print contacts and vias and from variability in
fabrication processes. The variability in fabrication processes may
include CMP dishing, layout feature shape distortion due to
photolithography, gate distortion, oxide thickness variability,
implant variability, and other fabrication related phenomena. The
dynamic array architecture of the present invention is defined to
address the above-mentioned semiconductor manufacturing process
variability.
[0097] FIG. 1 is an illustration showing a number of neighboring
layout features and a representation of light intensity used to
render each of the layout features, in accordance with one
embodiment of the present invention. Specifically, three
neighboring linear-shaped layout features (101A-101C) are depicted
as being disposed in a substantially parallel relationship within a
given mask layer. The distribution of light intensity from a layout
feature shape is represented by a sin c function. The sin c
functions (103A-103C) represent the distribution of light intensity
from each of the layout features (101A-101C, respectively). The
neighboring linear-shaped layout features (101A-101C) are spaced
apart at locations corresponding to peaks of the sin c functions
(103A-103C). Thus, constructive interference between the light
energy associated with the neighboring layout features (101A-101C),
i.e., at the peaks of the sin c functions (103A-103C), serves to
reinforce the exposure of the neighboring shapes (101A-101C) for
the layout feature spacing illustrated. In accordance with the
foregoing, the light interaction represented in FIG. 1 represents a
synchronous case.
[0098] As illustrated in FIG. 1, when linear-shaped layout features
are defined in a regular repeating pattern at an appropriate
spacing, constructive interference of the light energy associated
with the various layout features serves to enhance the exposure of
each layout feature. The enhanced exposure of the layout features
provided by the constructive light interference can dramatically
reduce or even eliminate a need to utilize optical proximity
correction (OPC) and/or reticle enhancement technology (RET) to
obtain sufficient rendering of the layout features.
[0099] A forbidden pitch, i.e., forbidden layout feature spacing,
occurs when the neighboring layout features (101A-101C) are spaced
such that peaks of the sin c function associated with one layout
feature align with valleys of the sin c function associated with
another layout feature, thus causing destructive interference of
the light energy. The destructive interference of the light energy
causes the light energy focused at a given location to be reduced.
Therefore, to realize the beneficial constructive light
interference associated with neighboring layout features, it is
necessary to predict the layout feature spacing at which the
constructive overlap of the sin c function peaks will occur.
Predictable constructive overlap of the sin c function peaks and
corresponding layout feature shape enhancement can be realized if
the layout feature shapes are rectangular, near the same size, and
are oriented in the same direction, as illustrated by the layout
features (101A-101C) in FIG. 1. In this manner, resonant light
energy from neighboring layout feature shapes is used to enhance
the exposure of a particular layout feature shape.
[0100] FIG. 2 is an illustration showing a generalized stack of
layers used to define a dynamic array architecture, in accordance
with one embodiment of the present invention. It should be
appreciated that the generalized stack of layers used to define the
dynamic array architecture, as described with respect to FIG. 2, is
not intended to represent an exhaustive description of the CMOS
manufacturing process. However, the dynamic array is to be built in
accordance with standard CMOS manufacturing processes. Generally
speaking, the dynamic array architecture includes both the
definition of the underlying structure of the dynamic array and the
techniques for assembling the dynamic array for optimization of
area utilization and manufacturability. Thus, the dynamic array is
designed to optimize semiconductor manufacturing capabilities.
[0101] With regard to the definition of the underlying structure of
the dynamic array, the dynamic array is built-up in a layered
manner upon a base substrate 201, e.g., upon a silicon substrate,
or silicon-on-insulator (SOI) substrate. Diffusion regions 203 are
defined in the base substrate 201. The diffusion regions 203
represent selected regions of the base substrate 201 within which
impurities are introduced for the purpose of modifying the
electrical properties of the base substrate 201. Above the
diffusion regions 203, diffusion contacts 205 are defined to enable
connection between the diffusion regions 203 and conductor lines.
For example, the diffusion contacts 205 are defined to enable
connection between source and drain diffusion regions 203 and their
respective conductor nets. Also, gate electrode features 207 are
defined above the diffusion regions 203 to form transistor gates.
Gate electrode contacts 209 are defined to enable connection
between the gate electrode features 207 and conductor lines. For
example, the gate electrode contacts 209 are defined to enable
connection between transistor gates and their respective conductor
nets.
[0102] Interconnect layers are defined above the diffusion contact
205 layer and the gate electrode contact layer 209. The
interconnect layers include a first metal (metal 1) layer 211, a
first via (via 1) layer 213, a second metal (metal 2) layer 215, a
second via (via 2) layer 217, a third metal (metal 3) layer 219, a
third via (via 3) layer 221, and a fourth metal (metal 4) layer
223. The metal and via layers enable definition of the desired
circuit connectivity. For example, the metal and via layers enable
electrical connection of the various diffusion contacts 205 and
gate electrode contacts 209 such that the logic function of the
circuitry is realized. It should be appreciated that the dynamic
array architecture is not limited to a specific number of
interconnect layers, i.e., metal and via layers. In one embodiment,
the dynamic array may include additional interconnect layers 225,
beyond the fourth metal (metal 4) layer 223. Alternatively, in
another embodiment, the dynamic array may include less than four
metal layers.
[0103] The dynamic array is defined such that layers (other than
the diffusion region layer 203) are restricted with regard to
layout feature shapes that can be defined therein. Specifically, in
each layer other than the diffusion region layer 203, only
linear-shaped layout features are allowed. A linear-shaped layout
feature in a given layer is characterized as having a consistent
vertical cross-section shape and extending in a single direction
over the substrate. Thus, the linear-shaped layout features define
structures that are one-dimensionally varying. The diffusion
regions 203 are not required to be one-dimensionally varying,
although they are allowed to be if necessary. Specifically, the
diffusion regions 203 within the substrate can be defined to have
any two-dimensionally varying shape with respect to a plane
coincident with a top surface of the substrate. In one embodiment,
the number of diffusion bend topologies is limited such that the
interaction between the bend in diffusion and the conductive
material, e.g., polysilicon, that forms the gate electrode of the
transistor is predictable and can be accurately modeled. The
linear-shaped layout features in a given layer are positioned to be
parallel with respect to each other. Thus, the linear-shaped layout
features in a given layer extend in a common direction over the
substrate and parallel with the substrate. The specific
configurations and associated requirements of the linear-shaped
features in the various layers 207-223 are discussed further with
regard to FIGS. 3-15C.
[0104] The underlying layout methodology of the dynamic array uses
constructive light interference of light waves in the lithographic
process to reinforce exposure of neighboring shapes in a given
layer. Therefore, the spacing of the parallel, linear-shaped layout
features in a given layer is designed around the constructive light
interference of the standing light waves such that lithographic
correction (e.g., OPC/RET) is minimized or eliminated. Thus, in
contrast to conventional OPC/RET-based lithographic processes, the
dynamic array defined herein exploits the light interaction between
neighboring features, rather than attempting to compensate for the
light interaction between neighboring features.
[0105] Because the standing light wave for a given linear-shaped
layout feature can be accurately modeled, it is possible to predict
how the standing light waves associated with the neighboring
linear-shaped layout features disposed in parallel in a given layer
will interact. Therefore, it is possible to predict how the
standing light wave used to expose one linear-shaped feature will
contribute to the exposure of its neighboring linear-shaped
features. Prediction of the light interaction between neighboring
linear-shaped features enables the identification of an optimum
feature-to-feature spacing such that light used to render a given
shape will reinforce its neighboring shapes. The feature-to-feature
spacing in a given layer is defined as the feature pitch, wherein
the pitch is the center-to-center separation distance between
adjacent linear-shaped features in a given layer.
[0106] To provide the desired exposure reinforcement between
neighboring features, the linear-shaped layout features in a given
layer are spaced such that constructive and destructive
interference of the light from neighboring features will be
optimized to produce the best rendering of all features in the
neighborhood. The feature-to-feature spacing in a given layer is
proportional to the wavelength of the light used to expose the
features. The light used to expose each feature within about a five
light wavelength distance from a given feature will serve to
enhance the exposure of the given feature to some extent. The
exploitation of constructive interference of the standing light
waves used to expose neighboring features enables the manufacturing
equipment capability to be maximized and not be limited by concerns
regarding light interactions during the lithography process.
[0107] As discussed above, the dynamic array incorporates a
restricted topology in which the features within each layer (other
than diffusion) are required to be linear-shaped features that are
oriented in a parallel manner to traverse over the substrate in a
common direction. With the restricted topology of the dynamic
array, the light interaction in the photolithography process can be
optimized such that the printed image on the mask is essentially
identical to the drawn shape in the layout, i.e., essentially a
100% accurate transfer of the layout onto the resist is
achieved.
[0108] FIG. 3A is an illustration showing an exemplary base grid to
be projected onto the dynamic array to facilitate definition of the
restricted topology, in accordance with one embodiment of the
present invention. The base grid can be used to facilitate parallel
placement of the linear-shaped features in each layer of the
dynamic array at the appropriate optimized pitch. Although not
physically defined as part of the dynamic array, the base grid can
be considered as a projection on each layer of the dynamic array.
Also, it should be understood that the base grid is projected in a
substantially consistent manner with respect to position on each
layer of the dynamic array, thus facilitating accurate feature
stacking and alignment.
[0109] In the exemplary embodiment of FIG. 3A, the base grid is
defined as a rectangular grid, i.e., Cartesian grid, in accordance
with a first reference direction (x) and a second reference
direction (y). The gridpoint-to-gridpoint spacing in the first and
second reference directions can be defined as necessary to enable
definition of the linear-shaped features at the optimized
feature-to-feature spacing. Also, the gridpoint spacing in the
first reference direction (x) can be different than the gridpoint
spacing in the second reference direction (y). In one embodiment, a
single base grid is projected across the entire die to enable
location of the various linear-shaped features in each layer across
the entire die. However, in other embodiments, separate base grids
can be projected across separate regions of the die to support
different feature-to-feature spacing requirements within the
separate regions of the die. FIG. 3B is an illustration showing
separate base grids projected across separate regions of the die,
in accordance with an exemplary embodiment of the present
invention.
[0110] The base grid is defined with consideration for the light
interaction function, i.e., the sinc function, and the
manufacturing capability, wherein the manufacturing capability is
defined by the manufacturing equipment and processes to be utilized
in fabricating the dynamic array. With regard to the light
interaction function, the base grid is defined such that the
spacing between gridpoints enables alignment of peaks in the sin c
functions describing the light energy projected upon neighboring
gridpoints. Therefore, linear-shaped features optimized for
lithographic reinforcement can be specified by drawing a line from
a first gridpoint to a second gridpoint, wherein the line
represents a rectangular structure of a given width. It should be
appreciated that the various linear-shaped features in each layer
can be specified according to their endpoint locations on the base
grid and their width.
[0111] FIG. 3C is an illustration showing an exemplary
linear-shaped feature 301 defined to be compatible with the dynamic
array, in accordance with one embodiment of the present invention.
The linear-shaped feature 301 has a substantially rectangular
cross-section defined by a width 303 and a height 307. The
linear-shaped feature 301 extends in a linear direction to a length
305. In one embodiment, a cross-section of the linear-shaped
feature, as defined by its width 303 and height 307, is
substantially uniform along its length 305. It should be
understood, however, that lithographic effects may cause a rounding
of the ends of the linear-shaped feature 301. The first and second
reference directions (x) and (y), respectively, of FIG. 3A are
shown to illustrate an exemplary orientation of the linear-shaped
feature on the dynamic array. It should be appreciated that the
linear-shaped feature may be oriented to have its length 305 extend
in either the first reference direction (x), the second reference
direction (y), or in diagonal direction defined relative to the
first and second reference directions (x) and (y). Regardless of
the linear-shaped features' particular orientation with respect to
the first and second reference directions (x) and (y), it should be
understood that the linear-shaped feature is defined in a plane
that is substantially parallel to a top surface of the substrate
upon which the dynamic array is built. Also, it should be
understood that the linear-shaped feature is free of bends, i.e.,
change in direction, in the plane defined by the first and second
reference directions.
[0112] FIG. 3D is an illustration showing another exemplary
linear-shaped feature 317 defined to be compatible with the dynamic
array, in accordance with one embodiment of the present invention.
The linear-shaped feature 317 has a trapezoidal cross-section
defined by a lower width 313, an upper width 315, and a height 309.
The linear-shaped feature 317 extends in a linear direction to a
length 311. In one embodiment, the cross-section of the
linear-shaped feature 317 is substantially uniform along its length
311. It should be understood, however, that lithographic effects
may cause a rounding of the ends of the linear-shaped feature 317.
The first and second reference directions (x) and (y),
respectively, of FIG. 3A are shown to illustrate an exemplary
orientation of the linear-shaped feature on the dynamic array. It
should be appreciated that the linear-shaped feature 317 may be
oriented to have its length 311 extend in either the first
reference direction (x), the second reference direction (y), or in
diagonal direction defined relative to the first and second
reference directions (x) and (y). Regardless of the particular
orientation of the linear-shaped feature 317 with regard to the
first and second reference directions (x) and (y), it should be
understood that the linear-shaped feature 317 is defined in a plane
that is substantially parallel to a top surface of the substrate
upon which the dynamic array is built. Also, it should be
understood that the linear-shaped feature 317 is free of bends,
i.e., change in direction, in the plane defined by the first and
second reference directions.
[0113] Although FIGS. 3C and 3D explicitly discuss linear shaped
features having rectangular and trapezoidal cross-sections,
respectively, it should be understood that the linear shaped
features having other types of cross-sections can be defined within
the dynamic array. Therefore, essentially any suitable
cross-sectional shape of the linear-shaped feature can be utilized
so long as the linear-shaped feature is defined to have a length
that extends in one direction, and is oriented to have its length
extend in either the first reference direction (x), the second
reference direction (y), or in diagonal direction defined relative
to the first and second reference directions (x) and (y).
[0114] The layout architecture of the dynamic array follows the
base grid pattern. Thus, it is possible to use grid points to
represent where changes in direction occur in diffusion, wherein
gate electrode and metal linear-shaped features are placed, where
contacts are placed, where opens are in the linear-shaped gate
electrode and metal features, etc. The pitch of the gridpoints,
i.e., the gridpoint-to-gridpoint spacing, should be set for a given
feature line width, e.g., width 303 in FIG. 3C, such that exposure
of neighboring linear-shaped features of the given feature line
width will reinforce each other, wherein the linear-shaped features
are centered on gridpoints. With reference to the dynamic array
stack of FIG. 2 and the exemplary base grid of FIG. 3A, in one
embodiment, the gridpoint spacing in the first reference direction
(x) is set by the required gate electrode gate pitch. In this same
embodiment, the gridpoint pitch in the second reference direction
(y) is set by the metal 1 and metal 3 pitch. For example, in a 90
nm process technology, i.e., minimum feature size equal to 90 nm,
the gridpoint pitch in the second reference direction (y) is about
0.24 micron. In one embodiment, metal 1 and metal 2 layers will
have a common spacing and pitch. A different spacing and pitch may
be used above the metal 2 layer.
[0115] The various layers of the dynamic array are defined such
that the linear-shaped features in adjacent layers extend in a
crosswise manner with respect to each other. For example, the
linear-shaped features of adjacent layers may extend orthogonally,
i.e., perpendicularly with respect to each other. Also, the
linear-shaped features of one layer may extend across the
linear-shaped features of an adjacent layer at an angle, e.g., at
about 45 degrees. For example, in one embodiment the linear-shaped
feature of one layer extend in the first reference direction (x)
and the linear-shaped features of the adjacent layer extend
diagonally with respect to the first (x) and second (y) reference
directions. It should be appreciated that to route a design in the
dynamic array having the linear-shaped features positioned in the
crosswise manner in adjacent layers, opens can be defined in the
linear-shaped features, and contacts and vias can be defined as
necessary.
[0116] The dynamic array minimizes the use of bends in layout
shapes to eliminate unpredictable lithographic interactions.
Specifically, prior to OPC or other RET processing, the dynamic
array allows bends in the diffusion layer to enable control of
device sizes, but does not allow bends in layers above the
diffusion layer. The layout features in each layer above the
diffusion layer are linear in shape, e.g., FIG. 3C, and disposed in
a parallel relationship with respect to each other. The linear
shapes and parallel positioning of layout features are implemented
in each stack layer of the dynamic array where predictability of
constructive light interference is necessary to ensure
manufacturability. In one embodiment, the linear shapes and
parallel positioning of layout features are implemented in the
dynamic array in each layer above diffusion through metal 2. Above
metal 2, the layout features may be of sufficient size and shape
that constructive light interference is not required to ensure
manufacturability. However, the presence of constructive light
interference in patterning layout features above metal 2 may be
beneficial.
[0117] An exemplary buildup of dynamic array layers from diffusion
through metal 2 are described with respect to FIGS. 4 through 14.
It should be appreciated that the dynamic array described with
respect to FIGS. 4 through 14 is provided by way of example only,
and is not intended to convey limitations of the dynamic array
architecture. The dynamic array can be used in accordance with the
principles presented herein to define essentially any integrated
circuit design.
[0118] FIG. 4 is an illustration showing a diffusion layer layout
of an exemplary dynamic array, in accordance with one embodiment of
the present invention. The diffusion layer of FIG. 4 shows a
p-diffusion region 401 and an n-diffusion region 403. While the
diffusion regions are defined according to the underlying base
grid, the diffusion regions are not subject to the linear-shaped
feature restrictions associated with the layers above the diffusion
layer. The diffusion regions 401 and 403 include diffusion squares
405 defined where diffusion contacts will be located. The diffusion
regions 401 and 403 do not include extraneous jogs or corners, thus
improving the use of lithographic resolution and enabling more
accurate device extraction. Additionally, n+ mask regions (412 and
416) and p+ mask regions (410 and 414) are defined as rectangles on
the (x), (y) grid with no extraneous jogs or notches. This style
permits use of larger diffusion regions, eliminates need for
OPC/RET, and enables use of lower resolution and lower cost
lithographic systems, e.g., i-line illumination at 365 nm. It
should be appreciated that the n+ mask region 416 and the p+ mask
region 410, as depicted in FIG. 4, are for an embodiment that does
not employ well-biasing. In an alternative embodiment where
well-biasing is to be used, the n+ mask region 416 shown in FIG. 4
will actually be defined as a p+ mask region. Also, in this
alternative embodiment, the p+ mask region 410 shown in FIG. 4 will
actually be defined as a n+ mask region.
[0119] FIG. 5 is an illustration showing a gate electrode layer and
a diffusion contact layer above and adjacent to the diffusion layer
of FIG. 4, in accordance with one embodiment of the present
invention. As those skilled in the CMOS arts will appreciate, the
gate electrode features 501 define the transistor gates. The gate
electrode features 501 are defined as linear shaped features
extending in a parallel relationship across the dynamic array in
the second reference direction (y). In one embodiment, the gate
electrode features 501 are defined to have a common width. However,
in another embodiment, one or more of the gate electrode features
can be defined to have a different width. For example, FIG. 5 shows
a gate electrode features 501A that has a larger width relative to
the other gate electrode features 501. The pitch (center-to-center
spacing) of the gate electrode features 501 is minimized while
ensuring optimization of lithographic reinforcement, i.e., resonant
imaging, provided by neighboring gate electrode features 501. For
discussion purposes, gate electrode features 501 extending across
the dynamic array in a given line are referred to as a gate
electrode track.
[0120] The gate electrode features 501 form n-channel and p-channel
transistors as they cross the diffusion regions 403 and 401,
respectively. Optimal gate electrode feature 501 printing is
achieved by drawing gate electrode features 501 at every grid
location, even though no diffusion region may be present at some
grid locations. Also, long continuous gate electrode features 501
tend to improve line end shortening effects at the ends of gate
electrode features within the interior of the dynamic array.
Additionally, gate electrode printing is significantly improved
when all bends are removed from the gate electrode features
501.
[0121] Each of the gate electrode tracks may be interrupted, i.e.,
broken, any number of times in linearly traversing across the
dynamic array in order to provide required electrical connectivity
for a particular logic function to be implemented. When a given
gate electrode track is required to be interrupted, the separation
between ends of the gate electrode track segments at the point of
interruption is minimized to the extent possible taking into
consideration the manufacturing capability and electrical effects.
In one embodiment, optimal manufacturability is achieved when a
common end-to-end spacing is used between features within a
particular layer.
[0122] Minimizing the separation between ends of the gate electrode
track segments at the points of interruption serves to maximize the
lithographic reinforcement, and uniformity thereof, provided from
neighboring gate electrode tracks. Also, in one embodiment, if
adjacent gate electrode tracks need to be interrupted, the
interruptions of the adjacent gate electrode tracks are made such
that the respective points of interruption are offset from each
other so as to avoid, to the extent possible, an occurrence of
neighboring points of interruption. More specifically, points of
interruption within adjacent gate electrode tracks are respectively
positioned such that a line of sight does not exist through the
points of interruption, wherein the line of sight is considered to
extend perpendicularly to the direction in which the gate electrode
tracks extend over the substrate. Additionally, in one embodiment,
the gate electrodes may extend through the boundaries at the top
and bottom of the cells, i.e., the PMOS or NMOS cells. This
embodiment would enable bridging of neighboring cells.
[0123] With further regard to FIG. 5, diffusion contacts 503 are
defined at each diffusion square 405 to enhance the printing of
diffusion contacts via resonant imaging. The diffusion squares 405
are present around every diffusion contact 503 to enhance the
printing of the power and ground connection polygons at the
diffusion contacts 503.
[0124] The gate electrode features 501 and diffusion contacts 503
share a common grid spacing. More specifically, the gate electrode
feature 501 placement is offset by one-half the grid spacing
relative to the diffusion contacts 503. For example, if the gate
electrode features 501 and diffusion contact 503 grid spacing is
0.36 .mu.m, then the diffusion contacts are placed such that the
x-coordinate of their center falls on an integer multiple of 0.36
.mu.m, while the x-coordinate of the center of each gate electrode
feature 501 minus 0.18 .mu.m should be an integer multiple of 0.36
.mu.m. In the present example, the x-coordinates are represented by
the following: [0125] Diffusion contact center x-coordinate=I*0.36
.mu.m, where I is the grid number; [0126] Gate electrode feature
center x-coordinate=0.18 .mu.m+I*0.36 .mu.m, where I is the grid
number.
[0127] The grid based system of the dynamic array ensures that all
contacts (diffusion and gate electrode) will land on a horizontal
grid that is equal to a multiple of one-half of the diffusion
contact grid and a vertical grid that is set by the metal 1 pitch.
In the example above, the gate electrode feature and diffusion
contact grid is 0.36 .mu.m. The diffusion contacts and gate
electrode contacts will land on a horizontal grid that is a
multiple of 0.18 .mu.m. Also, the vertical grid for 90 nm process
technologies is about 0.24 .mu.m.
[0128] FIG. 6 is an illustration showing a gate electrode contact
layer defined above and adjacent to the gate electrode layer of
FIG. 5, in accordance with one embodiment of the present invention.
In the gate electrode contact layer, gate electrode contacts 601
are drawn to enable connection of the gate electrode features 501
to the overlying metal conduction lines. In general, design rules
will dictate the optimum placement of the gate electrode contacts
601. In one embodiment, the gate electrode contacts are drawn on
top of the transistor endcap regions. This embodiment minimizes
white space in the dynamic array when design rules specify long
transistor endcaps. In some process technologies white space may be
minimized by placing a number of gate electrode contacts for a cell
in the center of the cell. Also, it should be appreciated that in
the present invention, the gate electrode contact 601 is oversized
in the direction perpendicular to the gate electrode feature 501 to
ensure overlap between the gate electrode contact 601 and the gate
electrode feature 501.
[0129] FIG. 7A is an illustration showing a traditional approach
for making contact to a gate electrode, e.g., polysilicon feature.
In the traditional configuration of FIG. 7A, an enlarged
rectangular gate electrode region 707 is defined where a gate
electrode contact 709 is to be located. The enlarged rectangular
gate electrode region 707 introduces a bend of distance 705 in the
gate electrode. The bend associated with the enlarged rectangular
gate electrode region 707 sets up undesirable light interactions
and distorts the gate electrode line 711. Distortion of the gate
electrode line 711 is especially problematic when the gate
electrode width is about the same as a transistor length.
[0130] FIG. 7B is an illustration showing a gate electrode contact
601, e.g., polysilicon contact, defined in accordance with one
embodiment of the present invention. The gate electrode contact 601
is drawn to overlap the edges of the gate electrode feature 501,
and extend in a direction substantially perpendicular to the gate
electrode feature 501. In one embodiment, the gate electrode
contact 601 is drawn such that the vertical dimension 703 is same
as the vertical dimension used for the diffusion contacts 503. For
example, if the diffusion contact 503 opening is specified to be
0.12 .mu.m square then the vertical dimension of the gate electrode
contact 601 is drawn at 0.12 .mu.m. However, in other embodiments,
the gate electrode contact 601 can be drawn such that the vertical
dimension 703 is different from the vertical dimension used for the
diffusion contacts 503.
[0131] In one embodiment, the gate electrode contact 601 extension
701 beyond the gate electrode feature 501 is set such that maximum
overlap is achieved between the gate electrode contact 601 and the
gate electrode feature 501. The extension 701 is defined to
accommodate line end shortening of the gate electrode contact 601,
and misalignment between the gate electrode contact layer and gate
electrode feature layer. The length of the gate electrode contact
601 is defined to ensure maximum surface area contact between the
gate electrode contact 601 and the gate electrode feature 501,
wherein the maximum surface area contact is defined by the width of
the gate electrode feature 501.
[0132] FIG. 8A is an illustration showing a metal 1 layer defined
above the gate electrode contact layer of FIG. 6, in accordance
with one embodiment of the present invention. The metal 1 layer
includes a number of metal 1 tracks 801-821 defined to include
linear shaped features extending in a parallel relationship across
the dynamic array. The metal 1 tracks 801-821 extend in a direction
substantially perpendicular to the gate electrode features 501 in
the underlying gate electrode layer of FIG. 5. Thus, in the present
example, the metal 1 tracks 801-821 extend linearly across the
dynamic array in the first reference direction (x). The pitch
(center-to-center spacing) of the metal 1 tracks 801-821 is
minimized while ensuring optimization of lithographic
reinforcement, i.e., resonant imaging, provided by neighboring
metal 1 tracks 801-821. For example, in one embodiment, the metal 1
tracks 801-821 are centered on a vertical grid of about 0.24 .mu.m
for a 90 nm process technology.
[0133] Each of the metal 1 tracks 801-821 may be interrupted, i.e.,
broken, any number of times in linearly traversing across the
dynamic array in order to provide required electrical connectivity
for a particular logic function to be implemented. When a given
metal 1 track 801-821 is required to be interrupted, the separation
between ends of the metal 1 track segments at the point of
interruption is minimized to the extent possible taking into
consideration manufacturing capability and electrical effects.
Minimizing the separation between ends of the metal 1 track
segments at the points of interruption serves to maximize the
lithographic reinforcement, and uniformity thereof, provided from
neighboring metal 1 tracks. Also, in one embodiment, if adjacent
metal 1 tracks need to be interrupted, the interruptions of the
adjacent metal 1 tracks are made such that the respective points of
interruption are offset from each other so as to avoid, to the
extent possible, an occurrence of neighboring points of
interruption. More specifically, points of interruption within
adjacent metal 1 tracks are respectively positioned such that a
line of sight does not exist through the points of interruption,
wherein the line of sight is considered to extend perpendicularly
to the direction in which the metal 1 tracks extend over the
substrate.
[0134] In the example of FIG. 8A, the metal 1 track 801 is
connected to the ground supply, and the metal 1 track 821 is
connected to the power supply voltage. In the embodiment of FIG.
8A, the widths of the metal 1 tracks 801 and 821 are the same as
the other metal 1 tracks 803-819. However, in another embodiment,
the widths of metal 1 tracks 801 and 821 are larger than the widths
of the other metal 1 tracks 803-819. FIG. 8B is an illustration
showing the metal 1 layer of FIG. 8A with larger track widths for
the metal 1 ground and power tracks (801A and 821A), relative to
the other metal 1 tracks 803-819.
[0135] The metal 1 track pattern is optimally configured to
optimize the use of "white space" (space not occupied by
transistors). The example of FIG. 8A includes the two shared metal
1 power tracks 801 and 821, and nine metal 1 signal tracks 803-819.
Metal 1 tracks 803, 809, 811, and 819 are defined as gate electrode
contact tracks in order to minimize white space. Metal 1 tracks 805
and 807 are defined to connect to n-channel transistor source and
drains. Metal 1 tracks 813, 815, and 817 are defined to connect to
p-channel source and drains. Also, any of the nine metal 1 signal
tracks 803-819 can be used as a feed through if no connection is
required. For example, metal 1 tracks 813 and 815 are configured as
feed through connections.
[0136] FIG. 9 is an illustration showing a via 1 layer defined
above and adjacent to the metal 1 layer of FIG. 8A, in accordance
with one embodiment of the present invention. Vias 901 are defined
in the via 1 layer to enable connection of the metal 1 tracks
801-821 to higher level conduction lines.
[0137] FIG. 10 is an illustration showing a metal 2 layer defined
above and adjacent to the via 1 layer of FIG. 9, in accordance with
one embodiment of the present invention. The metal 2 layer includes
a number of metal 2 tracks 1001 defined as linear shaped features
extending in a parallel relationship across the dynamic array. The
metal 2 tracks 1001 extend in a direction substantially
perpendicular to the metal 1 tracks 801-821 in the underlying metal
1 layer of FIG. 8A, and in a direction substantially parallel to
the gate electrode tracks 501 in the underlying gate electrode
layer of FIG. 5. Thus, in the present example, the metal 2 tracks
1001 extend linearly across the dynamic array in the second
reference direction (y).
[0138] The pitch (center-to-center spacing) of the metal 2 tracks
1001 is minimized while ensuring optimization of lithographic
reinforcement, i.e., resonant imaging, provided by neighboring
metal 2 tracks. It should be appreciated that regularity can be
maintained on higher level interconnect layers in the same manner
as implemented in the gate electrode and metal 1 layers. In one
embodiment, the gate electrode feature 501 pitch and the metal 2
track pitch is the same. In another embodiment, the contacted gate
electrode pitch (e.g., polysilicon-to-polysilicon space with a
diffusion contact in between) is greater than the metal 2 track
pitch. In this embodiment, the metal 2 track pitch is optimally set
to be 2/3 or 3/4 of the contacted gate electrode pitch. Thus, in
this embodiment, the gate electrode track and metal 2 track align
at every two gate electrode track pitches and every three metal 2
track pitches. For example, in a 90 nm process technology, the
optimum contacted gate electrode track pitch is 0.36 .mu.m, and the
optimum metal 2 track pitch is 0.24 .mu.m. In another embodiment,
the gate electrode track and the metal 2 track align at every three
gate electrode pitches and every four metal 2 pitches. For example,
in a 90 nm process technology, the optimum contacted gate electrode
track pitch is 0.36 .mu.m, and the optimum metal 2 track pitch is
0.27 .mu.m.
[0139] Each of the metal 2 tracks 1001 may be interrupted, i.e.,
broken, any number of times in linearly traversing across the
dynamic array in order to provide required electrical connectivity
for a particular logic function to be implemented. When a given
metal 2 track 1001 is required to be interrupted, the separation
between ends of the metal 2 track segments at the point of
interruption is minimized to the extent possible taking into
consideration manufacturing and electrical effects. Minimizing the
separation between ends of the metal 2 track segments at the points
of interruption serves to maximize the lithographic reinforcement,
and uniformity thereof, provided from neighboring metal 2 tracks.
Also, in one embodiment, if adjacent metal 2 tracks need to be
interrupted, the interruptions of the adjacent metal 2 tracks are
made such that the respective points of interruption are offset
from each other so as to avoid, to the extent possible, an
occurrence of neighboring points of interruption. More
specifically, points of interruption within adjacent metal 2 tracks
are respectively positioned such that a line of sight does not
exist through the points of interruption, wherein the line of sight
is considered to extend perpendicularly to the direction in which
the metal 2 tracks extend over the substrate.
[0140] As discussed above, the conduction lines in a given metal
layer above the gate electrode layer may traverse the dynamic array
in a direction coincident with either the first reference direction
(x) or the second reference direction (y). It should be further
appreciated that the conduction lines in a given metal layer above
the gate electrode layer may traverse the dynamic array in a
diagonal direction relative to the first and second reference
directions (x) and (y). FIG. 11 is an illustration showing
conductor tracks 1101 traversing the dynamic array in a first
diagonal direction relative to the first and second reference
directions (x) and (y), in accordance with one embodiment of the
present invention. FIG. 12 is an illustration showing conductor
tracks 1201 traversing the dynamic array in a second diagonal
direction relative to the first and second reference directions (x)
and (y), in accordance with one embodiment of the present
invention.
[0141] As with the metal 1 and metal 2 tracks discussed above, the
diagonal traversing conductor tracks 1101 and 1201 of FIGS. 11 and
12 may be interrupted, i.e., broken, any number of times in
linearly traversing across the dynamic array in order to provide
required electrical connectivity for a particular logic function to
be implemented. When a given diagonal traversing conductor track is
required to be interrupted, the separation between ends of the
diagonal conductor track at the point of interruption is minimized
to the extent possible taking into consideration manufacturing and
electrical effects. Minimizing the separation between ends of the
diagonal conductor track at the points of interruption serves to
maximize the lithographic reinforcement, and uniformity thereof,
provided from neighboring diagonal conductor tracks.
[0142] An optimal layout density within the dynamic array is
achieved by implementing the following design rules: [0143] at
least two metal 1 tracks be provided across the n-channel device
area; [0144] at least two metal 1 tracks be provided across the
p-channel device area; [0145] at least two gate electrode tracks be
provided for the n-channel device; and [0146] at least two gate
electrode tracks be provided for the p-channel device.
[0147] Contacts and vias are becoming the most difficult mask from
a lithographic point of view. This is because the contacts and vias
are getting smaller, more closely spaced, and are randomly
distributed. The spacing and density of the cuts (contact or vias)
makes it extremely difficult to reliably print the shapes. For
example, cut shapes may be printed improperly due to destructive
interference patterns from neighboring shapes or lack of energy on
lone shapes. If a cut is properly printed, the manufacturing yield
of the associated contact or via is extremely high. Sub-resolution
contacts can be provided to reinforce the exposure of the actual
contacts, so long as the sub-resolution contacts do not resolve.
Also, the sub-resolution contacts can be of any shape so long as
they are smaller than the resolution capability of the lithographic
process.
[0148] FIG. 13A is an illustration showing an example of a
sub-resolution contact layout used to lithographically reinforce
diffusion contacts and gate electrode contacts, in accordance with
one embodiment of the present invention. Sub-resolution contacts
1301 are drawn such that they are below the resolution of the
lithographic system and will not be printed. The function of the
sub-resolution contacts 1301 is to increase the light energy at the
desired contact locations, e.g., 503, 601, through resonant
imaging. In one embodiment, sub-resolution contacts 1301 are placed
on a grid such that both gate electrode contacts 601 and diffusion
contacts 503 are lithographically reinforced. For example,
sub-resolution contacts 1301 are placed on a grid that is equal to
one-half the diffusion contact 503 grid spacing to positively
impact both gate electrode contacts 601 and diffusion contacts 503.
In one embodiment, a vertical spacing of the sub-resolution
contacts 1301 follows the vertical spacing of the gate electrode
contacts 601 and diffusion contacts 503.
[0149] Grid location 1303 in FIG. 13A denotes a location between
adjacent gate electrode contacts 601. Depending upon the
lithographic parameters in the manufacturing process, it is
possible that a sub-resolution contact 1301 at this grid location
would create an undesirable bridge between the two adjacent gate
electrode contacts 601. If bridging is likely to occur, a
sub-resolution contact 1301 at location 1303 can be omitted.
Although FIG. 13A shows an embodiment where sub-resolution contacts
are placed adjacent to actual features to be resolved and not
elsewhere, it should be understood that another embodiment may
place a sub-resolution contact at each available grid location so
as to fill the grid.
[0150] FIG. 13B is an illustration showing the sub-resolution
contact layout of FIG. 13A with sub-resolution contacts defined to
fill the grid to the extent possible, in accordance with one
embodiment of the present invention. It should be appreciated that
while the embodiment of FIG. 13B fills the grid to the extent
possible with sub-resolution contacts, placement of sub-resolution
contacts is avoided at locations that would potentially cause
undesirable bridging between adjacent fully resolved features.
[0151] FIG. 13C is an illustration showing an example of a
sub-resolution contact layout utilizing various shaped
sub-resolution contacts, in accordance with one embodiment of the
present invention. Alternative sub-resolution contact shapes can be
utilized so long as the sub-resolution contacts are below the
resolution capability of the manufacturing process. FIG. 13C shows
the use of "X-shaped" sub-resolution contacts 1305 to focus light
energy at the corners of the adjacent contacts. In one embodiment,
the ends of the X-shaped sub-resolution contact 1305 are extended
to further enhance the deposition of light energy at the corners of
the adjacent contacts.
[0152] FIG. 13D is an illustration showing an exemplary
implementation of alternate phase shift masking (APSM) with
sub-resolution contacts, in accordance with one embodiment of the
present invention. As in FIG. 13A, sub-resolution contacts are
utilized to lithographically reinforce diffusion contacts 503 and
gate electrode contacts 601. APSM is used to improve resolution
when neighboring shapes create destructive interference patterns.
The APSM technique modifies the mask so that the phase of light
traveling through the mask on neighboring shapes is 180 degrees out
of phase. This phase shift serves to remove destructive
interference and allowing for greater contact density. By way of
example, contacts in FIG. 13D marked with a plus "+" sign represent
contacts exposed with light waves of a first phase while contacts
marked with a minus sign "-" represent contacts exposed with light
waves that are shifted in phase by 180 degrees relative to the
first phase used for the "+" sign contacts. It should be
appreciated that the APSM technique is utilized to ensure that
adjacent contacts are separated from each other.
[0153] As feature sizes decrease, semiconductor dies are capable of
including more gates. As more gates are included, however, the
density of the interconnect layers begins to dictate the die size.
This increasing demand on the interconnect layers drives higher
levels of interconnect layers. However, the stacking of
interconnect layers is limited in part by the topology of the
underlying layers. For example, as interconnect layers are built
up, islands, ridges, and troughs can occur. These islands, ridges,
and troughs can cause breaks in the interconnect lines that cross
them.
[0154] To mitigate these islands and troughs, the semiconductor
manufacturing process utilizes a chemical mechanical polishing
(CMP) procedure to mechanically and chemically polish the surface
of the semiconductor wafer such that each subsequent interconnect
layer is deposited on a substantially flat surface. Like the
photolithography process the quality of the CMP process is layout
pattern dependent. Specifically, an uneven distribution of a layout
features across a die or a wafer can cause too much material to be
removed in some places and not enough material to be removed in
other places, thus causing variations in the interconnect thickness
and unacceptable variations in the capacitance and resistance of
the interconnect layer. The capacitance and resistance variation
within the interconnect layer may alter the timing of a critical
net causing design failure.
[0155] The CMP process requires that dummy fill be added in the
areas without interconnect shapes so that a substantially uniform
wafer topology is provided to avoid dishing and improve
center-to-edge uniformity. Traditionally, dummy fill is placed
post-design. Thus, in the traditional approach the designer is not
aware of the dummy fill characteristics. Consequently, the dummy
fill placed post-design may adversely influence the design
performance in a manner that has not been evaluated by the
designer. Also, because the conventional topology prior to the
dummy fill is unconstrained, i.e., non-uniform, the post-design
dummy fill will not be uniform and predictable. Therefore, in the
conventional process, the capacitive coupling between the dummy
fill regions and the neighboring active nets cannot be predicted by
the designer.
[0156] As previously discussed, the dynamic array disclosed herein
provides optimal regularity by maximally filling all interconnect
tracks from gate electrode layer upward. If multiple nets are
required in a single interconnect track, the interconnect track is
split with a minimally spaced gap. For example, track 809
representing the metal 1 conduction line in FIG. 8A represents
three separate nets in the same track, where each net corresponds
to a particular track segment. More specifically, there are two
poly contact nets and a floating net to fill the track with minimal
spacing between the track segments. The substantially complete
filling of tracks maintains the regular pattern that creates
resonant images across the dynamic array. Also, the regular
architecture of the dynamic array with maximally filled
interconnect tracks ensures that the dummy fill is placed in a
uniform manner across the die. Therefore, the regular architecture
of the dynamic array assists the CMP process to produce
substantially uniform results across the die/wafer. Also, the
regular gate pattern of the dynamic array assists with gate etching
uniformity (microloading). Additionally, the regular architecture
of the dynamic array combined with the maximally filled
interconnect tracks allows the designer to analyze the capacitive
coupling effects associated with the maximally filled tracks during
the design phase and prior to fabrication.
[0157] Because the dynamic array sets the size and spacing of the
linearly shaped features, i.e., tracks and contacts, in each mask
layer, the design of the dynamic array can be optimized for the
maximum capability of the manufacturing equipment and processes.
That is to say, because the dynamic array is restricted to the
regular architecture for each layer above diffusion, the
manufacturer is capable of optimizing the manufacturing process for
the specific characteristics of the regular architecture. It should
be appreciated that with the dynamic array, the manufacturer does
not have to be concerned with accommodating the manufacture of a
widely varying set of arbitrarily-shaped layout features as is
present in conventional unconstrained layouts.
[0158] An example of how the capability of manufacturing equipment
can be optimized is provided as follows. Consider that a 90 nm
process has a metal 2 pitch of 280 nm. This metal 2 pitch of 280 nm
is not set by the maximum capability of equipment. Rather, this
metal 2 pitch of 280 nm is set by the lithography of the vias. With
the via lithography issues removed, the maximum capability of the
equipment allows for a metal 2 pitch of about 220 nm. Thus, the
design rules for metal 2 pitch include about 25% margin to account
for the light interaction unpredictability in the via
lithography.
[0159] The regular architecture implemented within the dynamic
array allows the light interaction unpredictability in the via
lithography to be removed, thus allowing for a reduction in the
metal 2 pitch margin. Such a reduction in the metal 2 pitch margin
allows for a more dense design, i.e., allows for optimization of
chip area utilization. Additionally, with the restricted, i.e.,
regular, topology afforded by the dynamic array, the margin in the
design rules can be reduced. Moreover, not only can the excess
margin beyond the capability of the process be reduced, the
restricted topology afforded by the dynamic array also allows the
number of required design rules to be substantially reduced. For
example, a typical design rule set for an unconstrained topology
could have more than 600 design rules. A design rule set for use
with the dynamic array may have about 45 design rules. Therefore,
the effort required to analyze and verify the design against the
design rules is decreased by more than a factor of ten with the
restricted topology of the dynamic array.
[0160] When dealing with line end-to-line end gaps (i.e., track
segment-to-track segment gaps) in a given track of a mask layer in
the dynamic array, a limited number of light interactions exist.
This limited number of light interactions can be identified,
predicted, and accurately compensated for ahead of time,
dramatically reducing or completely eliminating the requirement for
OPC/RET. The compensation for light interactions at line
end-to-line end gaps represents a lithographic modification of the
as-drawn feature, as opposed to a correction based on modeling of
interactions, e.g., OPC/RET, associated with the as-drawn
feature.
[0161] Also, with the dynamic array, changes to the as-drawn layout
are only made where needed. In contrast, OPC is performed over an
entire layout in a conventional design flow. In one embodiment, a
correction model can be implemented as part of the layout
generation for the dynamic array. For example, due to the limited
number of possible line end gap interactions, a router can be
programmed to insert a line break having characteristics defined as
a function of its surroundings, i.e., as a function of its
particular line end gap light interactions. It should be further
appreciated that the regular architecture of the dynamic array
allows the line ends to be adjusted by changing vertices rather
than by adding vertices. Thus, in contrast with unconstrained
topologies that rely on the OPC process, the dynamic array
significantly reduces the cost and risk of mask production. Also,
because the line end gap interactions in the dynamic array can be
accurately predicted in the design phase, compensation for the
predicted line end gap interactions during the design phase does
not increase risk of design failure.
[0162] In conventional unconstrained topologies, designers are
required to have knowledge of the physics associated with the
manufacturing process due to the presence of design dependent
failures. With the grid-based system of the dynamic array as
disclosed herein, the logical design can be separated from the
physical design. More specifically, with the regular architecture
of the dynamic array, the limited number of light interactions to
be evaluated within the dynamic array, and the design independent
nature of the dynamic array, designs can be represented using a
grid point based netlist, as opposed to a physical netlist.
[0163] With the dynamic array, the design is not required to be
represented in terms of physical information. Rather, the design
can be represented as a symbolic layout. Thus, the designer can
represent the design from a pure logic perspective without having
to represent physical characteristics, e.g., sizes, of the design.
It should be understood that the grid-based netlist, when
translated to physical, matches the optimum design rules exactly
for the dynamic array platform. When the grid-based dynamic array
moves to a new technology, e.g., smaller technology, a grid-based
netlist can be moved directly to the new technology because there
is no physical data in the design representation. In one
embodiment, the grid-based dynamic array system includes a rules
database, a grid-based (symbolic) netlist, and the dynamic array
architecture.
[0164] It should be appreciated that the grid-based dynamic array
eliminates topology related failures associated with conventional
unconstrained architectures. Also, because the manufacturability of
the grid-based dynamic array is design independent, the yield of
the design implemented on the dynamic array is independent of the
design. Therefore, because the validity and yield of the dynamic
array is preverified, the grid-based netlist can be implemented on
the dynamic array with preverified yield performance.
[0165] FIG. 14 is an illustration showing a semiconductor chip
structure 1400, in accordance with one embodiment of the present
invention. The semiconductor chip structure 1400 represents an
exemplary portion of a semiconductor chip, including a diffusion
region 1401 having a number of conductive lines 1403A-1403G defined
thereover. The diffusion region 1401 is defined in a substrate
1405, to define an active region for at least one transistor
device. The diffusion region 1401 can be defined to cover an area
of arbitrary shape relative to the substrate 1405 surface.
[0166] The conductive lines 1403A-1403G are arranged to extend over
the substrate 1405 in a common direction 1407. It should also be
appreciated that each of the number of conductive lines 1403A-1403G
are restricted to extending over the diffusion region 1401 in the
common direction 1407. In one embodiment, the conductive lines
1403A-1403G defined immediately over the substrate 1405 are
polysilicon lines. In one embodiment, each of the conductive lines
1403A-1403G is defined to have essentially the same width 1409 in a
direction perpendicular to the common direction 1407 of extension.
In another embodiment, some of the conductive lines 1403A-1403G are
defined to have different widths relative to the other conductive
lines. However, regardless of the width of the conductive lines
1403A-1403G, each of the conductive lines 1403A-1403G is spaced
apart from adjacent conductive lines according to essentially the
same center-to-center pitch 1411.
[0167] As shown in FIG. 14, some of the conductive lines
(1403B-1403E) extend over the diffusion region 1401, and other
conductive lines (1403A, 1403F, 1403G) extend over non-diffusion
portions the substrate 1405. It should be appreciated that the
conductive lines 1403A-1403G maintain their width 1409 and pitch
1411 regardless of whether they are defined over diffusion region
1401 or not. Also, it should be appreciated that the conductive
lines 1403A-1403G maintain essentially the same length 1413
regardless of whether they are defined over diffusion region 1401
or not, thereby maximizing lithographic reinforcement between the
conductive lines 1403A-1403G across the substrate. In this manner,
some of the conductive lines, e.g., 1403D, defined over the
diffusion region 1401 include a necessary active portion 1415, and
one or more uniformity extending portions 1417.
[0168] It should be appreciated that the semiconductor chip
structure 1400 represents a portion of the dynamic array described
above with respect to FIGS. 2-13D. Therefore, it should be
understood that the uniformity extending portions 1417 of the
conductive lines (1403B-1403E) are present to provide lithographic
reinforcement of neighboring conductive lines 1403A-1403G. Also,
although they may not be required for circuit operation, each of
conductive lines 1403A, 1403F, and 1403G are present to provide
lithographic reinforcement of neighboring conductive lines
1403A-1403G.
[0169] The concept of the necessary active portion 1415 and the
uniformity extending portions 1417 also applies to higher level
interconnect layers. As previously described with regard to the
dynamic array architecture, adjacent interconnect layers traverse
over the substrate in transverse directions, e.g., perpendicular or
diagonal directions, to enable routing/connectivity required by the
logic device implemented within the dynamic array. As with the
conductive lines 1403A-1403G, each of the conductive lines within
an interconnect layer may include a required portion (necessary
active portion) to enable required routing/connectivity, and a
non-required portion (uniformity extending portion) to provide
lithographic reinforcement to neighboring conductive lines. Also,
as with the conductive lines 1403A-1403G, the conductive lines
within an interconnect layer extend in a common direction over the
substrate, have essentially the same width, and are spaced apart
from each other according to an essentially constant pitch.
[0170] In one embodiment, conductive lines within an interconnect
layer follow essentially the same ratio between line width and line
spacing. For example, at 90 nm the metal 4 pitch is 280 nm with a
line width and line spacing equal to 140 nm. Larger conductive
lines can be printed on a larger line pitch if the line width is
equal to the line spacing.
[0171] The dynamic array architecture as described herein
represents a semiconductor device design paradigm in which linear
conductive features are defined along a virtual grate in each of a
plurality of levels. The plurality of levels are defined above a
portion of a semiconductor substrate that may have one or more
diffusion regions defined therein. The virtual grate of a given
level is oriented to be substantially perpendicular to the virtual
grate in an adjacent level. Also, the linear conductive features
are defined along each line of each virtual grate so as to be
devoid of a substantial change in direction. It should be
appreciated that each conductive feature within each of the
plurality of levels is defined by one of the linear conductive
features. Therefore, the dynamic array architecture specifically
avoids the use of non-linear conductive features, wherein a
non-linear conductive feature includes one or more bends within a
plane of the associated level.
[0172] In one embodiment the plurality of levels of the dynamic
array architecture extends upward from the substrate through the
entire chip to the outer packaging of the chip. In another
embodiment, the plurality of levels of the dynamic array
architecture extends upward from the substrate through a number of
levels that is less than the total number of levels within the
entire chip. In this embodiment, the number of levels defined
according to the dynamic array architecture includes those levels
which benefit from or require the high probability of accurate
manufacturing prediction as afforded by the dynamic array
architecture. For example, the dynamic array architecture may be
used to define each level above the substrate through a third
interconnect level. Then, due to the increased size and spacing of
features and/or decreased number of features above the third
interconnect level, an arbitrary layout technique may be used to
define the features above the third interconnect level. It should
be appreciated that any portion of a chip that employs the dynamic
array architecture in any number of levels thereof is considered to
represent a dynamic array architecture region.
[0173] Within a given level defined according to the dynamic array
architecture, proximate ends of adjacent linear conductive features
may be separated from each other by a substantially uniform gap.
More specifically, adjacent ends of linear conductive features
defined along a common line of a virtual grate are separated by a
gap, and such gaps within the level associated with the virtual
grate may be defined to span a substantially uniform distance.
Also, within the dynamic array architecture, vias and contacts are
defined to interconnect a number of the linear conductive features
in various levels so as to form a number of functional electronic
devices, e.g., transistors, and electronic circuits. Thus, a number
of the linear conductive features in the plurality of levels form
functional components of an electronic circuit. Additionally, some
of the linear conductive features within the plurality of levels
may be non-functional with respect to an electronic circuit, but
are manufactured nonetheless so as to reinforce manufacturing of
neighboring linear conductive features. It should be understood
that the dynamic array architecture is defined to enable accurate
prediction of semiconductor device manufacturability with a high
probability.
[0174] FIG. 15 is an illustration showing an exemplary chip 1501
implementing the dynamic array architecture, in accordance with one
embodiment of the present invention. The exemplary chip includes a
dynamic array architecture region 1509. The exemplary chip 1501
also includes a memory region 1503, an input/output (I/O) region
1505, and a processor region 1507. It should be understood that the
memory region 1503, the I/O region 1505, and the processor region
1507 are shown by way of example and are not intended to represent
required portions of a chip, required chip architecture, or
required accompaniments to the dynamic array architecture.
[0175] It should be also be understood that in one embodiment, such
as that of FIG. 15, the dynamic array architecture can be used to
define one or more portions of a larger chip, i.e., die, wherein
the circuitry defined within the one or more dynamic array
architecture portions is defined to interface, as necessary, with
circuitry in other portions of the chip. In another embodiment, an
entire chip can be defined according to the dynamic array
architecture. In this embodiment, although the entire chip is
defined according to the dynamic array architecture, the chip can
be partitioned into a number of distinct regions, where each
distinct region is defined according to the dynamic array
architecture. In accordance with the foregoing, a semiconductor
chip can be configured to include one or more dynamic array
architecture regions defined over a portion of the substrate of the
chip, wherein each dynamic array architecture region includes one
or more distinct but functionally interfaced dynamic array
sections.
[0176] FIG. 16 is an illustration showing a blank canvas of the
dynamic array architecture region 1509, in accordance with one
embodiment of the present invention. A dynamic array section (DAS)
grid 1601 is defined across the blank canvas of the dynamic array
architecture region 1509 to facilitate placement and alignment of
dynamic array sections. The DAS grid 1601 is defined by a virtual
network of perpendicular lines 1603A/1603B, i.e., gridlines, for
locating dynamic array sections (DAS s) on the substrate. As
previously discussed, the DAS grid 1601 may be defined on a portion
of a die, or over an entire die. The virtual network of
perpendicular lines 1603A/1603B that represent the DAS grid 1601
are present in effect, although not present as physical entities.
The DAS grid 1601 is defined within a plane substantially
coincident with an upper surface of the substrate upon which the
DAS s are built. Thus, the DAS grid 1601 is defined within a plane
that is parallel with a top surface of the substrate of the chip.
The spacing between the lines 1603A/1603B of the DAS grid 1601 in
each of the two perpendicular directions, respectively, can be the
same or different. However, in one embodiment, the lines
1603A/1603B of the DAS grid 1601 having a common direction are
uniformly spaced.
[0177] The spacing between adjacent parallel lines (1603A or 1603B)
of the DAS grid 1601 is defined as a pitch of the adjacent parallel
lines (1603A or 1603B). In one embodiment, the pitch of the DAS
grid 1601 lines (1603A or 1603B) that run parallel with gate
electrode features is defined to be equal to one-half of the
minimum center-to-center separation between adjacent contacted gate
electrode features. For ease of discussion, one-half of the minimum
center-to-center separation between adjacent contacted gate
electrode features is referred to as the gate electrode half-pitch.
In the present embodiment, a DAS boundary that is coincident with a
DAS grid line defined based on the gate electrode half-pitch will
itself lie on the gate electrode half-pitch. Therefore, a cell
defined within and at the edge of such a DAS will have a cell
boundary that falls on the gate electrode half-pitch.
[0178] The dynamic array section (DAS) is defined as a subdivision
of dynamic array architecture in which the features present in each
vertically delineated level of the subdivision are defined with
consideration of other features in the subdivision according to a
set of rules, wherein the rules are established to govern
relationships between features in a given level of the subdivision
and between features in separate levels of the subdivision. A DAS
can be defined to occupy a substrate area of arbitrary shape and
size. A DAS can also be defined to occupy an area of arbitrary
shape and size above the substrate. Also, the perpendicular lines
1603A/1603B of the DAS grid 1601 can be used to define DAS
boundaries.
[0179] FIG. 17A is an illustration showing a number of exemplary
dynamic array sections (DAS1-DAS11) defined within the dynamic
array architecture region 1509, in accordance with one embodiment
of the present invention. Each boundary of each DAS (DAS1-DAS11) is
defined along on a gridline 1603A/1603B of the DAS grid 1601, as
described with regard to FIG. 16. It should be appreciated that the
uniformity of the DAS grid 1601 facilitates placement and
functional interfacing of the various DASs. The particular shapes
of the exemplary DASs (DAS1-DAS11) are defined for descriptive
purposes and should not be considered limiting with regard to the
potential shape of a given DAS. More specifically, a given DAS can
be defined to have essentially any shape and size as is necessary
to define the devices and circuitry present within the DAS, so long
as the DAS is compliant with the dynamic array architecture.
[0180] It should also be understood that a DAS is not required to
include the substrate portion of the chip, or be defined
immediately above and in contact with the substrate portion of the
chip. More specifically, a DAS can be vertically defined to occupy
a number of layers of the chip over a particular substrate area,
but not immediately above and in contact with the substrate of the
chip. In this regard, one embodiment can include a number of
stacked DASs, wherein each stacked DAS is defined independently
from an adjacent DAS present either thereabove or therebelow. Also,
vertically stacked DASs can be defined to have different sizes and
shapes relative to each other. In this regard, a higher vertically
positioned DAS may cover: 1) more than a single lower vertically
positioned DAS, or 2) portions of multiple lower vertically
positioned DASs, or 3) a portion of a single lower vertically
positioned DAS.
[0181] FIG. 17B is an illustration showing a number of dynamic
array sections (DAS12-DAS15) defined at a higher vertical position
within the dynamic array architecture region 1509, in accordance
with one embodiment of the present invention. In the example of
FIG. 17B, the collection of DAS12-DAS15 is positioned above the
collection of DAS1-DAS11 of FIG. 17A. FIG. 17C is an illustration
showing a side view of the DAS stack of FIG. 17B, in accordance
with one embodiment of the present invention. It should be
understood that the DAS arrangement depicted in FIGS. 17A-17C is
provided for discussion purposes, and is not intended to represent
an inclusive set of possible DAS arrangements. Also, it should be
appreciated that in various embodiments DASs can be horizontally
and vertically arranged over a portion of a substrate in
essentially any manner consistent with the dynamic array
architecture.
[0182] To enable a more detailed description of the dynamic array
architecture, an exemplary implementation of the dynamic array
architecture with regard to DAS10 of FIG. 17A is described in FIGS.
18-24D. FIG. 18 is an illustration showing a substrate level of
DAS10, in accordance with one embodiment of the present invention.
The substrate level of a DAS can include any number of diffusion
regions. For example, DAS10 includes diffusion regions 1801A-1801D
defined within the substrate portion 1803 over which DAS10 is
built. The shape of each diffusion region within the substrate
portion of the DAS is defined based on knowledge of the devices,
i.e., transistors, that are to be formed within the DAS, and based
on knowledge of the higher level linear conductive feature spacings
and orientations that are to be utilized. It should be understood
that the diffusion layer layout as previously described with regard
to FIG. 4 is equally applicable to the substrate level of any DAS,
including the DAS10 example. Thus, each diffusion region within a
given DAS can be defined to have an arbitrary two-dimensional
shape. However, in one embodiment, the diffusion regions are
defined to not include extraneous jogs or corners, so as to improve
lithographic resolution and enable more accurate device
extraction.
[0183] Each DAS is defined to have a surrounding DAS manufacturing
assurance halo (DAS halo). For example, in FIG. 18, DAS10 is shown
to have a DAS halo 1805. The DAS halo is defined as a region
surrounding a given DAS within a given level of the chip, wherein
the manufacture of features within the DAS halo may impact the
manufacturing predictability of features within the given DAS. The
DAS halo is sized and managed to ensure that the manufacturing
predictability of features within the associated DAS is preserved
or enhanced. Upon placement of the DAS on the DAS grid, a portion
of the associated DAS halo may represent a buffer region devoid of
features from a neighboring DAS. Also, upon placement of the DAS on
the DAS grid, a portion of the associated DAS halo may include a
portion of a neighboring DAS, wherein the manufacture of features
within the portion of the neighboring DAS does not adversely affect
the manufacture of features within the DAS about which the DAS halo
exists, vice-versa. Thus, a DAS halo or portion thereof is allowed
to overlap a neighboring DAS halo or encroach within a neighboring
DAS, so long as the function of the DAS halo for each of the
neighboring DASs is satisfied to ensure that the manufacturing
predictability of features within each of the neighboring DAS s is
preserved or enhanced. The DAS halo is described in more detail
with regard to FIGS. 25-27.
[0184] A gate electrode level is defined above the substrate level
of the DAS10 example. The gate electrode level is defined to
include a number linear conductive features defined according to a
virtual grate associated with the gate electrode level. A virtual
grate of any DAS level, including the gate electrode level, is
defined as a virtual network of parallel lines for locating linear
conductive features within a DAS level. The virtual network of
parallel lines that represent a virtual grate for a given DAS level
are present in effect, although not present as physical entities.
The virtual grate for any DAS level is defined within a plane that
is substantially parallel to an upper surface of an underlying
substrate upon which the DAS is built. Also, in one embodiment, the
parallel lines of the virtual grate for a given DAS level are
spaced according to a constant pitch. The constant pitch used to
defined the virtual grate for a given DAS level can be set at
essentially any value required to facilitate appropriate placement
of linear conductive features within the given DAS level.
[0185] Generally speaking, in each DAS level, linear conductive
features are defined along the lines of the virtual grate
associated with the DAS level. Each linear conductive feature is
defined along a particular line of a virtual grate such that a
centerline of the linear conductive feature is substantially
centered upon the particular line of the virtual grate. A linear
conductive feature is considered to be substantially centered upon
a particular line of a virtual grate when a deviation in alignment
between of the centerline of the linear conductive feature and the
particular line of the virtual grate is sufficiently small so as to
not reduce a manufacturing process window from what would be
achievable with a true alignment between of the centerline of the
linear conductive feature and the line of the virtual grate. In one
embodiment, the above-mentioned manufacturing process window is
defined by a lithographic domain of focus and exposure that yields
an acceptable fidelity of the linear conductive feature. In one
embodiment, the fidelity of a linear conductive feature is defined
by a characteristic dimension of the linear conductive feature.
Also, it should be understood that the centerline of a given linear
conductive feature as referenced above is defined as a virtual line
that passes through the cross-sectional centroid of the linear
conductive feature at all points along its length, wherein the
cross-sectional centroid of the linear conductive feature at any
given point along its length is the centroid of its vertical
cross-section area at the given point.
[0186] It should be appreciated that each linear conductive feature
defined within a given DAS level will have associated sidewall
profiles corresponding to the shape contours of the sidewalls of
the linear conductive feature. The sidewalls of the linear
conductive feature in this regard are defined as the sides of the
linear conductive feature when viewed as a vertical cross-section
cut perpendicular to the centerline of the linear conductive
feature. The DAS architecture accommodates variation in the
sidewall profiles of a given linear conductive feature along its
length, so long as the sidewall profile variation is predictable
from a manufacturing perspective and does not adversely impact the
manufacture of the given linear conductive feature or its
neighboring linear conductive features. It should be appreciated
that sidewall variation along the length of a linear conductive
feature will correspond to width variation along the length of the
linear conductive feature. Therefore, the DAS architecture also
accommodates variation in the width of a given linear conductive
feature along its length, so long as the width variation is
predictable from a manufacturing perspective and does not adversely
impact the manufacture of the given linear conductive feature or
its neighboring linear conductive features.
[0187] In additional to the foregoing, it should be understood that
each linear conductive feature, or segment thereof, in each level
of the dynamic array architecture is defined to be devoid of a
substantial change in direction along its length. Thus, the lack of
substantial change in direction of a linear conductive feature is
considered relative to the line of the virtual grate along which
the linear conductive feature is defined. In one embodiment, a
substantial change in direction of a linear conductive feature
exists when the width of the linear conductive feature at any point
thereon changes by more than 50% of the nominal width of the linear
conductive feature along its entire length. In another embodiment,
a substantial change in direction of a linear conductive feature
exists when the width of the linear conductive feature changes from
any first location on the linear conductive feature to any second
location on the linear conductive feature by more that 50% of the
linear conductive feature width at the first location.
[0188] In the dynamic array architecture, each DAS level can be
defined to have any number of the lines of its virtual grate
occupied by any number of linear conductive features. In one
example, a given DAS level may be defined such that all lines of
its virtual grate are occupied by at least one linear conductive
feature. In another example, a given DAS level may be defined such
that some lines of its virtual grate are occupied by at least one
linear conductive feature, and other lines of its virtual grate are
vacant, i.e., not occupied by any number of linear conductive
features. Furthermore, in a given DAS level, any number of
successively adjacent virtual grate lines can be left vacant.
Additionally, in a given DAS level, any number of successively
adjacent virtual grate lines can be respectively occupied by any
number of linear conductive features. Also, in some DAS level
instances, the occupancy versus vacancy of the virtual grate lines,
with regard the presence of linear conductive features thereon, may
follow a pattern or repeating pattern across the DAS level.
[0189] Additionally, different linear conductive features within a
given level of the DAS can be designed to have the same width or
different widths. Also, the widths of a number of linear conductive
features defined along adjacent lines of a given virtual grate can
be designed such that the number of linear conductive features
contact each other so as to form a single linear conductive feature
having a width equal to the sum of the widths of the number of
linear conductive features.
[0190] FIG. 19A is an illustration showing a gate electrode level
virtual grate for the DAS10 example, in accordance with one
embodiment of the present invention. The gate electrode level
virtual grate is defined by a framework of parallel lines 1901
spaced at a constant pitch P1. The gate electrode level virtual
grate is oriented such that the lines thereof extend in a first
direction, i.e., y direction, over the substrate portion 1803 upon
which DAS10 is built. The position of the gate electrode level
virtual grate (in a second direction, i.e., x direction) and the
associated pitch P1 are established to ensure that lines of the
virtual grate along which linear conductive features are to be
defined will be properly positioned relative to the underlying
diffusion regions 1801A-1801D such that a number of the linear
conductive features defined within the gate electrode level can
serve as gate electrode components of transistor devices.
[0191] In the exemplary embodiment of FIG. 19A, the pitch P1 of the
virtual grate is equal to a minimum center-to-center spacing to be
used between adjacent contacted gate electrode features. However,
it should be understood that in other embodiments, the pitch P1 of
the gate electrode level virtual grate can be set at essentially
any value deemed appropriate for the particular DAS. For example,
FIG. 19A1 shows a virtual grate of the gate electrode level set at
a pitch HA equal to one-half of the minimum center-to-center
spacing between adjacent contacted gate electrode features. As
previously mentioned, one-half of the minimum center-to-center
separation between adjacent contacted gate electrode features is
referred to as the gate electrode half-pitch.
[0192] In one embodiment, the pitch that defines the virtual grate
of the gate electrode level is set to optimize lithographic
reinforcement during manufacture of linear conductive features
defined along the lines of the virtual grate. In another
embodiment, the pitch that defines the virtual grate of the gate
electrode level is set to optimize a density of the linear
conductive features defined along the lines of the virtual grate.
It should be appreciated that optimization of the density of the
linear conductive features, as defined along the lines of the
virtual grate, may not correspond to feature-to-feature
lithographic reinforcement during manufacturing. Also, in another
embodiment, the pitch that defines the virtual grate of the gate
electrode level can be set based on optimization of circuit
performance, manufacturability, or reliability.
[0193] FIG. 19B is an illustration showing full-length linear
conductive features 1903 defined along each line 1901 of the gate
electrode level virtual grate of FIG. 19A, in accordance with one
embodiment of the present invention. It should be understood that
while the example of FIG. 19B shows each line of the gate electrode
level virtual grate occupied by a linear conductive feature, there
is no requirement that every line of the gate electrode level
virtual grate, or any virtual grate for that matter, be occupied by
a linear conductive feature. It should be further appreciated that
each line of a virtual grate, in any given DAS level, represents a
potential linear conductive feature track along which one or more
linear conductive features can be defined. Each full-length linear
conductive feature 1903 represents a maximum feature occupancy of a
given line 1901 of the virtual grate. However, some of the
full-length linear conductive features 1903 in the gate electrode
level may need to be segmented to enable creation of transistor
devices. FIG. 19C is an illustration showing a segmentation of the
linear conductive features 1903 of FIG. 19B, in accordance with one
embodiment of the present invention.
[0194] Each linear conductive feature, or segment thereof, in each
level of the dynamic array architecture is defined to have a
substantially uniform width along its length. For example, with
regard to the gate electrode level of FIG. 19B, each linear
conductive feature 1903, or segment thereof, is defined to have a
substantially uniform width W1 along its length. The width of each
linear conductive feature within the dynamic array architecture is
measured in a coplanar and perpendicular relationship relative to
the framework of parallel lines that define the virtual grate along
which the linear conductive feature is defined. Correspondingly,
the length of each linear conductive feature within the dynamic
array architecture is measured in the direction of the line of the
virtual grate along which the linear conductive feature is
defined.
[0195] In one embodiment, such as that shown in FIG. 19B, each
linear conductive feature within a given DAS level is defined to
have a substantially equal width. However, in another embodiment,
linear conductive features defined along various lines of the
virtual grate within a given DAS level can be defined to have
different widths. For example, FIG. 19B1 is an illustration showing
linear conductive features 1904A, 1904B, 1904C defined along
various lines 1902 of the gate electrode level virtual grate of
FIG. 19A1, in accordance with one embodiment of the present
invention. FIG. 19B1 demonstrates several of the previously
mentioned options with regard to defining linear conductive
features along a virtual grate. In particular, areas 1906 in FIG.
19B1 demonstrate leaving a number of virtual grate lines vacant.
FIG. 19B1 also demonstrates how linear conductive features within a
given DAS level can be defined to have different widths, e.g., W1A,
W1B, W1C. Areas 1908 in FIG. 19B1 also demonstrate how widths of a
number of adjacent linear conductive features can be defined such
that the number of adjacent linear conductive features combine to
form a single linear conductive feature.
[0196] As shown in FIG. 19C, the actual layout of the gate
electrode level is achieved by segmenting a number of the
full-length linear conductive features 1903 of FIG. 19B.
Segmentation of full-length linear conductive features in any given
DAS level is performed by placing a number of gaps along its
length. For example, in the gate electrode level example of FIG.
19C a number of gaps of distance G1 are placed along various
full-length linear conductive features 1903. In various
embodiments, the size of the gaps used to separate adjacent ends of
co-aligned linear conductive feature segments may be either uniform
or non-uniform across a given DAS level. In one embodiment, each
gap used to segment the full-length linear conductive features in a
given level of the dynamic array architecture is defined to be
substantially uniform. Thus, in this embodiment, a substantially
uniform gap is maintained between proximate ends of adjacent linear
conductive feature segments that occupy a common line in the
virtual grate. Also in this embodiment, the substantially uniform
gap between the proximate ends of adjacent linear conductive
feature segments is maintained within each line in the virtual
grate that is occupied by multiple linear conductive feature
segments.
[0197] In one embodiment, the size of the gap maintained between
proximate ends of adjacent linear conductive features in a given
level of the dynamic array architecture is minimized within
electrical performance constraints so as to maximize an overall
linear conductive feature occupancy amount of the lines that define
the virtual grate of the given level. In another embodiment, size
of the gap maintained between proximate ends of adjacent linear
conductive features in a given level of the dynamic array
architecture is defined to ensure that the manufacturability of the
adjacent linear conductive features and neighboring linear
conductive features can be accurately predicted. In another
embodiment, the gaps maintained between proximate ends of adjacent
linear conductive features in a given level of the dynamic array
architecture are placed to avoid adjacent gaps in adjacent lines
that define the virtual grate of the given level. Also, in another
embodiment, the gaps between proximate ends of adjacent linear
conductive feature in a given DAS level are defined for circuit
performance, manufacturability, or reliability purposes.
[0198] Upon segmentation of the linear conductive features in a
given level of the dynamic array architecture, some of the linear
conductive feature segments may represent non-functional linear
conductive features. A non-functional linear conductive feature is
defined as a linear conductive feature that is not required for
circuit functionality, but is manufactured nonetheless so as to
assist with the manufacture of neighboring linear conductive
features. In one embodiment, some of the non-functional linear
conductive features are defined to enhance prediction of
semiconductor chip manufacturability. For example, FIG. 19C shows a
number of non-functional linear conductive features 1903B and a
number of functional linear conductive features 1903A, following
segmentation of the full-length conductive features 1903 to form
the gate electrode level layout of DAS10.
[0199] It should be understood that the dynamic array architecture
does not strictly require the retention of all non-functional
linear conductive feature segments, when such retention is not
necessary to enhance manufacturing of neighboring linear conductive
feature segments. For example, within a given level of the dynamic
array architecture, one or more non-functional linear conductive
features that do not positively impact or support the manufacture
of adjacent functional linear conductive features can be removed
from the layout. For example, FIG. 19D is an illustration showing
the gate electrode level segmented features of FIG. 19C with a
region 1905 within which a non-functional linear conductive feature
has been eliminated. The eliminated non-functional linear
conductive feature in the example of FIG. 19D was deemed
unnecessary with regard to supporting the manufacture of
neighboring functional linear conductive features.
[0200] Further with regard to FIG. 19C, it should be noted that the
linear conductive features 1903 of the gate electrode level are
defined to end at a location inside the boundary of the DAS, as
identified by location 1910. By having each of the linear
conductive features of the gate electrode level end inside the
boundary of the DAS, a gap will exist between colinearly aligned
gate electrode level linear conductive features within two adjacent
DAS's. In this instance, one half of the gap between the colinearly
aligned gate electrode level linear conductive features within the
two adjacent DAS's will reside in each of the two adjacent DAS's.
Also, although not explicitly depicted, is should be understood
that the segmentation and functional versus non-functional feature
concepts of FIGS. 19C and 19D are equally applicable to the
exemplary embodiments of FIGS. 19A1 and 19B1.
[0201] As previously discussed with regard to FIG. 7B, the dynamic
array architecture includes a number of gate electrode contacts
defined to electrically connect the linear conductive features
defined to serve as gate electrodes of transistor devices to
conductive features defined in one or more layers of the
semiconductor chip. Each of the number of gate electrode contacts
is defined to perpendicularly overlap a linear conductive feature
defined to serve as a gate electrode of a transistor device. As
shown in the exemplary embodiment of FIG. 7B, the gate electrode
contact 601 can be defined to have a rectangular shape. In another
embodiment, the gate electrode contact can be defined to have a
substantially square shape.
[0202] FIG. 20A is an illustration showing a first interconnect
level virtual grate for the DAS10 example, in accordance with one
embodiment of the present invention. The first interconnect level
virtual grate is defined by a framework of parallel lines 2001
spaced at a constant pitch P2. The first interconnect level virtual
grate is oriented such that the lines thereof extend in a direction
(x direction) over the substrate portion 1803 upon which DAS10 is
built, so as to extend in a direction perpendicular to the virtual
grate of the gate electrode level. The position of the first
interconnect level virtual grate in the y direction and the
associated pitch P2 are established to ensure that lines of the
first interconnect level virtual grate along which linear
conductive features are to be defined will be properly positioned
relative to the underlying gate electrode features such that the
associated transistor devices can be interconnected to form a
functional electronic circuit.
[0203] In the exemplary embodiment of FIG. 20A, the pitch P2 of the
virtual grate is equal to a minimum center-to-center spacing to be
used between adjacent contacted linear conductive features of the
first interconnect level. However, it should be understood that in
other embodiments, the pitch P2 of the first interconnect level
virtual grate can be set at essentially any value deemed
appropriate for the particular DAS. For example, FIG. 20A1 shows a
virtual grate of the first interconnect level set at a pitch P2A
equal to one-half of the minimum center-to-center spacing between
adjacent contacted linear conductive features of the first
interconnect level. For discussion purposes, one-half of the
minimum center-to-center spacing between adjacent contacted linear
conductive features of the first interconnect level is referred to
as the metal one half-pitch. Also, in the example of FIG. 20A1, the
power rail features are replaced by linear conductive features
defined along the virtual grate of the first interconnect level, as
opposed to being defined along power rail virtual lines defined
separate from the first interconnect level virtual grate.
[0204] In one embodiment, the pitch that defines the virtual grate
of the first interconnect level is set to optimize lithographic
reinforcement during manufacture of linear conductive features
defined along the lines of the virtual grate. In another
embodiment, the pitch P2 that defines the virtual grate of the
first interconnect level is set to optimize a density of the linear
conductive features defined along the lines of the virtual grate.
It should be appreciated that optimization of the density of the
linear conductive features, as defined along the lines of the
virtual grate, may not correspond to feature-to-feature
lithographic reinforcement during manufacturing. Also, in another
embodiment, the pitch that defines the virtual grate of the first
interconnect level can be set based on optimization of circuit
performance, manufacturability, or reliability.
[0205] FIG. 20A also shows virtual lines 2003 for power rail
placement. The virtual lines 2003 are defined in a manner similar
to the lines 2001 of the first interconnect level virtual grate.
Each of the power rail virtual lines 2003 is spaced apart from its
neighboring virtual grate line by a distance referred to as the
power rail pitch PP1. As with the virtual grate lines 2001, the
power rail virtual lines 2003 are defined to have linear conductive
features defined thereon. It should be understood that the power
rail pitch PP1 is defined independently from the pitch P2 of the
first interconnect level virtual grate.
[0206] In one embodiment, the power rail pitch PP1 is the same as
the pitch P2 of the first interconnect level virtual grate. For
example, when the first interconnect level virtual grate pitch P2
is equal to the third interconnect level virtual grate pitch P5,
the power rail pitch PP1 may be equal to the first interconnect
level virtual grate pitch P2. In another example, when the third
interconnect level virtual grate pitch P5 is greater than the first
interconnect level virtual grate pitch P2, the power rail pitch PP1
may different than the first interconnect level virtual grate pitch
P2 to make up for a difference in virtual grate line count between
the first and third interconnect levels, thereby allowing the first
and third interconnect level virtual grates to be aligned at the
boundary of the DAS.
[0207] FIG. 20B is an illustration showing full-length linear
conductive features 2005 defined along each line 2001 of the first
interconnect level virtual grate of FIG. 20A, in accordance with
one embodiment of the present invention. It should be understood
that while the example of FIG. 20B shows each line of the first
interconnect level virtual grate occupied by a linear conductive
feature, there is no requirement that every line of the first
interconnect level virtual grate, or any virtual grate for that
matter, be occupied by a linear conductive feature. Each linear
conductive feature 2005, or segment thereof, is defined to have a
substantially uniform width W3 along its length. The first
interconnect level also includes linear conductive power rail
features 2007 defined along the power rail virtual lines 2003. Each
linear conductive power rail feature 2007 is defined to have a
substantially uniform width W2 along its length. Within the first
interconnect level, each full-length linear conductive feature 2005
represents a maximum feature occupancy of a given line 2001 of the
virtual grate. However, some of the full-length linear conductive
features 2005 in the first interconnect level may need to be
segmented to enable interconnection of transistor devices and other
electronic components (e.g., resistors, diodes, capacitors, etc.)
to form a functional electronic circuit.
[0208] It should be understood that while the DAS10 example of
FIGS. 18-24D shows the linear conductive features of a given level
extending into the DAS halo region, the presence of linear
conductive features within the DAS halo region represents the
content of the DAS halo region following placement of the DAS on
the DAS grid. In various embodiments, the specific content of the
DAS halo region may be defined before or after placement of the DAS
on the DAS grid. This is discussed further with regard to FIGS.
25A-26D-2.
[0209] In one embodiment, such as that shown in FIG. 20B, each
linear conductive feature within a given DAS level is defined to
have a substantially equal width. However, as previously mentioned,
linear conductive features defined along various lines of the
virtual grate within a given DAS level can be defined to have
different widths. For example, FIG. 20B1 is an illustration showing
linear conductive features 2004A, 2004B, 2004C defined along
various lines 2002 of the first interconnect level virtual grate of
FIG. 20A1, in accordance with one embodiment of the present
invention. FIG. 20B1 demonstrates several of the previously
mentioned options with regard to defining linear conductive
features along a virtual grate. In particular, areas 2006 in FIG.
20B1 demonstrate leaving a number of virtual grate lines vacant.
FIG. 20B1 also demonstrates how linear conductive features within a
given DAS level can be defined to have different widths, e.g., W3A,
W3B, W3C. Areas 2008 in FIG. 20B1 also demonstrate how widths of a
number of adjacent linear conductive features can be defined such
that the number of adjacent linear conductive features combine to
form a single linear conductive feature.
[0210] FIG. 20C is an illustration showing a segmentation of the
linear conductive features 2005 of FIG. 20B, in accordance with one
embodiment of the present invention. As shown in FIG. 20C, the
actual layout of the first interconnect level is achieved by
segmenting a number of the full-length linear conductive features
defined therein. For example, a number of gaps of distance G2 are
placed along various full-length linear conductive features 2005.
In one embodiment, each gap of distance G2 used to segment the
full-length linear conductive features in the first interconnect
level of the dynamic array architecture is defined to be
substantially uniform. In another embodiment, the gaps used to
segment the full-length linear conductive features in the first
interconnect level can vary in size as necessary to ensure
manufacturability.
[0211] With regard to FIG. 20C, it should be understood that
segmentation of the linear conductive features 2005 can also
include removal of a portion of a linear conductive feature 2005 at
a location near the boundary of the DAS, as illustrated at
locations 2012. In one embodiment, removal of a portion of a given
linear conductive feature 2005 at the boundary of the DAS is
performed when continuity of the given linear conductive feature
2005 from the DAS to a neighboring DAS is not desired. In another
embodiment, removal of a portion of a given linear conductive
feature 2005 at the boundary of the DAS is performed to satisfy
functional requirements of the circuitry to be defined within the
DAS. In yet another embodiment, removal of a portion of a given
linear conductive feature 2005 at the boundary of the DAS is
performed to support manufacturability of one or more features
within the DAS. In one embodiment a portion of a given linear
conductive feature 2005 is removed at the boundary of the DAS while
leaving a portion of the linear conductive feature 2005 in the DAS
halo region, as illustrated at locations 2012. It should be
appreciated that the length of the portion of the linear conductive
features 2005 removed at the location near the boundary of the DAS
can vary depending on the DAS requirements or DAS-to-DAS interface
requirements. However, it should also be understood that removal of
the portion of the linear conductive feature 2005 at the boundary
of the DAS should be done so as to avoid adversely impacting the
manufacturability of neighboring linear conductive features 2005
within the DAS.
[0212] FIG. 21A is an illustration showing a second interconnect
level virtual grate for the DAS10 example, in accordance with one
embodiment of the present invention. The second interconnect level
virtual grate is defined by a framework of parallel lines 2101
spaced at a constant pitch P3. The second interconnect level
virtual grate is oriented such that the lines thereof extend in a
direction (y direction) over the substrate portion 1803 upon which
DAS10 is built, so as to extend in a direction perpendicular to the
virtual grate of the first interconnect level.
[0213] The position of the second interconnect level virtual grate
in the x direction and the associated pitch P3 are established
based upon a relationship between the virtual grates of the gate
electrode level and second interconnect level. FIG. 21B is an
illustration showing the spatial relationship between the second
interconnect level and gate electrode level virtual grates for the
DAS10 example, as defined based on a 3-to-2 pitch relationship
between second interconnect level and gate electrode level
conductive features, in accordance with one embodiment of the
present invention. The virtual grate of the second interconnect
level of DAS10 is defined such that the pitch ratio of second
interconnect level virtual grate lines 2101 to gate electrode level
virtual grate lines 1901 is 3-to-2. In this example, the pitch P3
of the second interconnect level virtual grate is defined such that
three pitches of the virtual grate lines 2101 of the second
interconnect level are provided for every two pitches of the
virtual grate lines 1901 of the gate electrode level.
[0214] It should be appreciated that the 3-to-2 virtual grate pitch
ratio between the second interconnect level and gate electrode
level of the dynamic array architecture is provided as an example
for one particular embodiment. In other embodiments a different
virtual grate pitch ratio can be defined between the second
interconnect level and gate electrode level of the dynamic array
architecture. Generally speaking, the virtual grate pitch ratio
between the second interconnect level and the gate electrode level
can be represented by an integer ratio (a/b), where the integer (a)
represents a number of second interconnect level conductive feature
pitches and the integer (b) represents a number of gate electrode
level conductive feature pitches that occur between successive
alignments of the second interconnect level and gate electrode
level conductive features. In one embodiment, an attempt is made to
set the virtual grate pitch ratio (a/b) as close to one as
possible. In this embodiment, an alignment pattern between the
second interconnect level and gate electrode level conductive
features will repeat at a minimum interval across the DAS. However,
regardless of the particular embodiment, the point to be understood
is that a specific spatial relationship in terms of pitch and
alignment exists between the second interconnect level virtual
grate and the gate electrode level virtual grate.
[0215] FIG. 21C is an illustration showing full-length linear
conductive features 2103 defined along each line 2101 of the second
interconnect level virtual grate, in accordance with one embodiment
of the present invention. It should be understood that while the
example of FIG. 21C shows each line of the second interconnect
level virtual grate occupied by a linear conductive feature, there
is no requirement that every line of the second interconnect level
virtual grate, or any virtual grate for that matter, be occupied by
a linear conductive feature. In the example of FIG. 21C, each
linear conductive feature 2103, or segment thereof, is defined to
have a substantially uniform width W4 along its length. However, it
should be understood that in other embodiments the various linear
conductive features defined across the second interconnect level of
the DAS can be defined to have different widths, with the width of
a given linear conductive feature along its length being
substantially uniform. Also, within the second interconnect level,
each full-length linear conductive feature 2103 represents a
maximum feature occupancy of a given line 2101 of the virtual
grate. However, some of the full-length linear conductive features
2103 in the second interconnect level may need to be segmented to
enable interconnection of transistor devices and other electronic
components (e.g., resistors, diodes, capacitors, etc.) to form a
functional electronic circuit.
[0216] FIG. 21D is an illustration showing a segmentation of the
linear conductive features 2103 within the second interconnect
level, in accordance with one embodiment of the present invention.
As shown in FIG. 21D, the actual layout of the second interconnect
level is achieved by segmenting a number of the full-length linear
conductive features 2103. For example, a number of gaps of distance
G3 are placed along various full-length linear conductive features
2103. In one embodiment, each gap of distance G3 used to segment
the full-length linear conductive features in the second
interconnect level of the dynamic array architecture is defined to
be substantially uniform. In another embodiment, the gaps used to
segment the full-length linear conductive features in the second
interconnect level can vary in size as necessary to ensure
manufacturability.
[0217] FIG. 22A is an illustration showing a second interconnect
level virtual grate for the DAS10 example, as defined based on a
4-to-3 pitch relationship between second interconnect level and
gate electrode level conductive features, in accordance with one
embodiment of the present invention. The second interconnect level
virtual grate in the example of FIG. 22A is defined by a framework
of parallel lines 2201 spaced at a constant pitch P4. The second
interconnect level virtual grate of FIG. 22A is oriented such that
the lines thereof extend in the direction perpendicular to the
virtual grate of the first interconnect level.
[0218] The position of the second interconnect level virtual grate
in the x direction and the associated pitch P4 are established
based on a 4-to-3 pitch relationship between second interconnect
level and gate electrode level conductive features. FIG. 22B is an
illustration showing the spatial relationship between the second
interconnect level and gate electrode level virtual grates for the
dynamic array section, as defined based on a 4-to-3 pitch
relationship between second interconnect level and gate electrode
level conductive features, in accordance with one embodiment of the
present invention. As shown in FIG. 22B, the pitch P4 of the second
interconnect level virtual grate is defined such that four virtual
grate line pitches of the second interconnect level are provided
for every three virtual grate line pitches of the gate electrode
level.
[0219] FIG. 22C is an illustration showing full-length linear
conductive features 2203 defined along each line 2201 of the second
interconnect level virtual grate, in accordance with one embodiment
of the present invention. Each linear conductive feature 2203, or
segment thereof, is defined to have a substantially uniform width
W5 along its length. Within the second interconnect level, each
full-length linear conductive feature 2203 represents a maximum
feature occupancy of a given line 2201 of the virtual grate.
However, some of the full-length linear conductive features 2203 in
the second interconnect level may need to be segmented to enable
interconnection of transistor devices and other electronic
components (e.g., resistors, diodes, capacitors, etc.) to form a
functional electronic circuit.
[0220] FIG. 22D is an illustration showing a segmentation of the
linear conductive features 2203 of FIG. 22C within the second
interconnect level, in accordance with one embodiment of the
present invention. As shown in FIG. 22D, the actual layout of the
second interconnect level is achieved by segmenting a number of the
full-length linear conductive features 2203. For example, a number
of gaps of distance G4 are placed along various full-length linear
conductive features 2203. In one embodiment, each gap of distance
G4 used to segment the full-length linear conductive features in
the second interconnect level of the dynamic array architecture is
defined to be substantially uniform. In another embodiment, the
gaps used to segment the full-length linear conductive features in
the second interconnect level can vary in size as necessary to
ensure manufacturability.
[0221] FIG. 23 is an illustration showing the second interconnect
level of FIG. 22D with a number of exemplary via locations 2301
identified thereon, in accordance with one embodiment of the
present invention. Within each DAS, each location at which virtual
grate lines cross each other is a potential via location.
Therefore, a virtual via grid is defined by the various locations
at which virtual grate lines of two different DAS levels cross each
other, where each of the crossing locations represents a potential
via location. For example, the exemplary via locations 2301 are
defined at locations where virtual grate lines of the second
interconnect level cross virtual grate lines of the first
interconnect level. To ensure full seating of a via on the
underlying conductive feature, it is may be necessary to extend the
underlying conductive feature a distance beyond the actual via
location. This extension distance, i.e., end overlap, of the
underlying conductive feature ensures that a line-end shortening
effect associated with the underlying conductive feature will not
preclude a full seating of the via on the underlying conductive
feature. To illustrate this point the gap G2 between the linear
conductive features of the first interconnect level beneath the
exemplary via locations 2301 is positioned so as to allow
extension, i.e., end overlap, of each of the linear conductive
features upon which vias are seated at the exemplary via locations
2301.
[0222] FIG. 24A is an illustration showing a third interconnect
level virtual grate for the DAS10 example, in accordance with one
embodiment of the present invention. The third interconnect level
virtual grate is defined by a framework of parallel lines 2401
spaced at a constant pitch P5. The third interconnect level virtual
grate is oriented such that the lines thereof extend in the x
direction over the substrate portion 1803 upon which DAS10 is
built, so as to extend in a direction perpendicular to the virtual
grate of the second interconnect level.
[0223] The position of the third interconnect level virtual grate
in the y direction and the associated pitch P5 are established
based upon a relationship between the virtual grates of the first
interconnect level (see FIGS. 20A through 20C) and third
interconnect level. FIG. 24B is an illustration showing a spatial
relationship between the third interconnect level and first
interconnect level virtual grates for the DAS10 example, in
accordance with one embodiment of the present invention. In one
embodiment, the spatial relationship between the third interconnect
level and first interconnect level virtual grates of a DAS is
defined as follows:
P 5 = [ ( 2 ) ( PP 1 ) ] + [ ( b - 1 ) ( P 2 ) ] ( a - 1 ) .
Equation 1 ##EQU00001##
where P5 is the pitch of the third interconnect level virtual
grate, P2 is the pitch of the first interconnect level virtual
grate, PP1 is the power rail pitch used in the first interconnect
level, (a) is the number of parallel lines defined within the
virtual grate of the third interconnect level, and (b) is the
number of parallel lines defined within the virtual grate of the
first interconnect level not including the number of power rail
virtual lines of the first interconnect level. In the DAS10
example, (a) is 10 and (b) is 9. Therefore, in the example of
DAS10, P5 is defined as a function of PP1 and P2 by the following:
P5=(1/9)[(2*PP1)+(8*P2)].
[0224] It should be appreciated that while Equation 1 defines a
relationship between the virtual grates of the third and first
interconnect levels for one DAS embodiment, other DAS embodiments
may utilize a different relationship between the virtual grates of
the third and first interconnect levels. Regardless of the
particular embodiment, the point to be understood is that a
specific spatial relationship in terms of pitch and alignment
exists between the third interconnect level virtual grate and the
first interconnect level virtual grate.
[0225] FIG. 24C is an illustration showing full-length linear
conductive features 2403 defined along each line 2401 of the third
interconnect level virtual grate, in accordance with one embodiment
of the present invention. It should be understood that while the
example of FIG. 24C shows each line of the third interconnect level
virtual grate occupied by a linear conductive feature, there is no
requirement that every line of the third interconnect level virtual
grate, or any virtual grate for that matter, be occupied by a
linear conductive feature. Each linear conductive feature 2403, or
segment thereof, is defined to have a substantially uniform width
W6 along its length. However, it should be understood that in other
embodiments the various linear conductive features defined across
the third interconnect level of the DAS can be defined to have
different widths, with the width of a given linear conductive
feature along its length being substantially uniform. Also, within
the third interconnect level, each full-length linear conductive
feature 2403 represents a maximum feature occupancy of a given line
2401 of the virtual grate. However, some of the full-length linear
conductive features 2403 in the third interconnect level may need
to be segmented to enable interconnection of transistor devices and
other electronic components (e.g., resistors, diodes, capacitors,
etc.) to form a functional electronic circuit.
[0226] FIG. 24D is an illustration showing a segmentation of the
linear conductive features 2403 within the third interconnect
level, in accordance with one embodiment of the present invention.
As shown in FIG. 24D, the actual layout of the third interconnect
level is achieved by segmenting a number of the full-length linear
conductive features 2403. For example, a number of gaps of distance
G5 are placed along various full-length linear conductive features
2403. In one embodiment, each gap of distance G5 used to segment
the full-length linear conductive features in the third
interconnect level of the dynamic array architecture is defined to
be substantially uniform. In another embodiment, the gaps used to
segment the full-length linear conductive features in the third
interconnect level can vary in size as necessary to ensure
manufacturability.
[0227] With regard to FIGS. 21D, 22D, and 24D, it should be
understood that segmentation of a given linear conductive feature
2103, 2203, 2403 can also include removal of a portion of the given
linear conductive feature at a location near the boundary of the
DAS. In one embodiment, removal of a portion of a given linear
conductive feature 2103, 2203, 2403 at the boundary of the DAS is
performed when continuity of the given linear conductive feature
from the DAS to a neighboring DAS is not desired. It should be
appreciated that the length of the portion of the given linear
conductive feature 2103, 2203, 2403 removed at the location near
the boundary of the DAS can vary depending on DAS-to-DAS interface
requirements. However, it should also be understood that removal of
the portion of the given linear conductive feature 2103, 2203, 2403
at the boundary of the DAS should be done so as to avoid adversely
impacting the manufacturability of neighboring linear conductive
features within the DAS.
[0228] As previously mentioned with regard to FIG. 18, each DAS has
an associated manufacturing assurance halo (DAS halo). Each DAS
halo is defined to facilitate placement of its associated DAS on
the DAS grid (see FIG. 17) such that functional features within the
associated DAS will be protected from adverse manufacturing impact
caused by neighboring DASs, and such that characteristics of the
associated DAS can be appropriately considered with regard to their
impact on the manufacture of each neighboring DAS. In other words,
the DAS halo defines a mechanism by which the proximate placement
of a DAS to another DAS can be controlled to ensure the
manufacturability of each DAS, while enabling optimization of chip
area utilization.
[0229] The DAS halo for a given DAS can be segmented to include a
number of compatibility designations. For example, given the linear
characteristics of the dynamic array architecture in each level of
the DAS, it can be expected that in one embodiment different
compatibility designations may be applied to segments of the DAS
halo about the boundaries of a given DAS, depending upon whether
the particular boundary runs parallel to a first direction of the
DAS grid or a second direction of the DAS grid (the second
direction being perpendicular to the first direction).
Additionally, in one embodiment, each DAS halo segment defined
along a boundary of the DAS that runs in the first direction of the
DAS grid may have a common compatibility designation. Similarly,
each DAS halo segment defined along a boundary of the DAS that runs
in the second direction of the DAS grid may have a common
compatibility designation.
[0230] FIG. 25A is an illustration showing a number of exemplary
DASs (DAS1-DAS11) with their respective boundary compatibility
designations (c1-c5), in accordance with one embodiment of the
present invention. With regard to FIG. 25A, the dashed lines around
each DAS (DAS1-DAS11) represents the DAS halo for the DAS. The
boundary compatibility designations for each DAS halo are
identified by labels c1, c2, c3, c4, or c5. In one embodiment, each
boundary segment of a DAS is given a boundary compatibility
designation. Thus, by way of the DAS boundary compatibility
designations, the placement of each boundary of each DAS can be
considered relative to each boundary of each DAS proximate
thereto.
[0231] In one embodiment, a number of DASs may be defined to form a
DAS library. A given DAS library may be defined to include a number
of DASs that form various electronic logic gates, devices,
circuits, or components, wherein each DAS in the given DAS library
is defined to have similar characteristics such that a common DAS
boundary compatibility designation can be applied to each DAS in
the given DAS library. Also, in this embodiment, a common DAS
boundary compatibility designation can be applied to each boundary
of each DAS in the given DAS library that extends in a common
direction. Furthermore, different DAS boundary compatibility
designations can be commonly applied to the given DAS library such
that each boundary of each DAS that extends in a first direction is
assigned a first DAS boundary compatibility designation, and each
boundary of each DAS that extends in a second direction is assigned
a second DAS boundary compatibility designation.
[0232] FIG. 25B is an illustration showing an exemplary assembly of
the DASs of FIG. 25A on a DAS grid according to their respective
DAS boundary compatibility designations, in accordance with one
embodiment of the present invention. A DAS cluster is defined as an
assembly of DASs on the DAS grid, wherein each DAS in the assembly
of DASs shares at least a portion of one DAS boundary with another
DAS in the assembly of DASs. In following, with regard to FIG. 25B,
a first DAS cluster is defined by DAS1, DAS3, DAS4, DAS7, DAS8,
DAS9, and DAS10. Also, with regard to FIG. 25B, a second DAS
cluster is defined by DAS3, DASS, DAS6, and DAS11. In one
embodiment, like DAS boundary compatibility designations for
particular boundaries of separate DASs indicates that the separate
DASs can be placed on the DAS grid such that the particular
boundaries thereof having like DAS boundary compatibility
designations can be aligned in a colinear manner. For example, DAS1
and DAS2 each have an adjacent boundary with a DAS boundary
compatibility designation of c2. Therefore, DAS1 and DAS2 can be
placed on the DAS grid with respect to each other such that their
adjacent boundaries having the DAS boundary compatibility
designation of c2 are aligned in a colinear manner. In this manner
other DAS boundaries can be colinearly aligned on the DAS grid, as
exemplified by DAS1 and DAS4, DAS1 and DAS7, DAS4 and DAS8, DAS7
and DAS8, DAS7 and DAS9, DAS8 and DAS9, DAS9 and DAS10, DAS3 and
DASS, DAS5 and DAS6, and DAS6 and DAS11.
[0233] In one embodiment, different DAS boundary compatibility
designations for particular boundaries of separate DASs indicates
that the separate DASs should be placed on the DAS grid such that
the particular boundaries thereof having different DAS boundary
compatibility designations are separated from each other to ensure
that the manufacture of the separate DASs does not adversely impact
each other. In one embodiment, adjacent boundaries of separate DASs
having different DAS boundary compatibility designations are spaced
apart from each other such that the DAS halo portions associated
with the adjacent boundaries of the separate DASs do not overlap.
For example, DAS2 and DAS3 have adjacent boundaries with DAS
boundary compatibility designations of c2 and c3, respectively.
Therefore, DAS2 and DAS3 are placed on the DAS grid with respect to
each other such that their DAS halo portions associated with their
adjacent boundaries do not overlap. In this manner other DAS
boundaries having incompatible DAS boundary designations are
separated from each other, as exemplified by DAS41 and DAS5, DAS8
and DAS5, DAS10 and DAS11, DAS3 and DAS6, and DAS5 and DAS11.
[0234] It should be understood that although boundaries of separate
DASs having like DAS boundary compatibility designations can be
aligned in a colinear manner on the DAS grid, such colinear
alignment is not strictly required. For example, DASs having like
DAS boundary compatibility designations on proximate boundaries may
be placed on the DAS grid so as to intentionally provide separation
between the proximate boundaries. FIG. 25C is an illustration
showing an exemplary assembly of the DASs of FIG. 25A on a DAS grid
according to their respective DAS boundary compatibility
designations with intentionally defined empty areas 2501, in
accordance with one embodiment of the present invention.
Specifically, in the example of FIG. 25C, although the DAS boundary
compatibility designations for the upper boundaries of DAS8 and the
lower boundaries of DAS4 allow their colinear placement on the DAS
grid, DAS8 is placed on the DAS grid so as to be separated from
DAS4, thereby forming empty areas 2501. Because chip area is
usually at a premium, intentional formation of such empty areas
2501 may not be a common occurrence. However, it should be
appreciated that the dynamic array architecture is flexible enough
to enable the intentional formation of such empty areas 2501, if
necessary.
[0235] FIG. 26A-1 is an illustration showing a level of an
exemplary DAS 2600, in accordance with one embodiment of the
present invention. The exemplary DAS 2600 has an associated DAS
boundary 2601 and an associated DAS halo boundary 2603, thereby
forming a DAS halo region 2605 outside the DAS boundary 2601. A
number of linear conductive features 2607 are shown within the
level of the DAS 2600. In one embodiment, an initial content of a
DAS halo region, e.g., DAS halo region 2605, for a given level of a
DAS is pre-defined along with the given level of the DAS prior to
placement of the DAS on the DAS grid. FIG. 26A-2 is an illustration
showing the exemplary DAS 2600 with its DAS halo region 2605
pre-defined to include a number of reinforcement features 2609. It
should be understood that the reinforcement features 2609 are shown
by way of example, and are not intended to convey a particular
requirement with regard to length, placement, number, or
segmentation of reinforcement features to be defined within a DAS
halo region.
[0236] FIG. 26B-1 is an illustration showing a level of another
exemplary DAS 2602, in accordance with one embodiment of the
present invention. The exemplary DAS 2602 has an associated DAS
boundary 2611 and an associated DAS halo boundary 2617, thereby
forming a DAS halo region 2615 outside the DAS boundary 2611. A
number of linear conductive features 2613 are shown within the
level of the DAS 2602. FIG. 26B-2 is an illustration showing the
exemplary DAS 2602 with its DAS halo region 2615 pre-defined to
include a number of reinforcement features 2619. It should be
understood that the reinforcement features 2619 are shown by way of
example, and are not intended to convey a particular requirement
with regard to length, placement, number, or segmentation of
reinforcement features to be defined within a DAS halo region.
[0237] In one embodiment, a number of DAS s are placed on a DAS
grid along with their respective DAS halo region contents to form a
DAS cluster. In this embodiment, the pre-defined content of the DAS
halo region for a given level of each DAS is subject to change upon
placement of the DAS on the DAS grid. More specifically, upon
placement of the given DAS on the DAS grid, a portion of the DAS
halo region associated with the given DAS can be eliminated through
occupancy of the location of the portion of the DAS halo region by
a neighboring DAS. Additionally, in this embodiment, the
pre-defined content of a portion of a DAS halo region is subject to
change depending on the context in which the DAS halo region finds
itself upon placement of the DAS on the DAS grid.
[0238] FIG. 26C-1 is an illustration showing an exemplary placement
of DAS 2600 of FIG. 26A-2 and DAS 2602 of FIG. 26B-2 on a DAS grid,
in accordance with one embodiment of the present invention. In the
embodiment of FIG. 26C-1, the pre-defined content of the DAS halo
region 2605 is placed on the DAS grid along with the DAS 2600.
Also, in the embodiment of FIG. 26C-1, the pre-defined content of
the DAS halo region 2615 is placed on the DAS grid along with the
DAS 2602. Each of DASs 2600 and 2602 are placed on the DAS grid
such that the bottom boundary of DAS 2600 and the top boundary of
DAS 2602 are colinearly aligned, wherein the bottom boundary of DAS
2600 and the top boundary of DAS 2602 are referenced relative to
the illustrated orientations of the DASs 2600 and 2602. Thus, the
bottom boundary of DAS 2600 and the top boundary of DAS 2602 share
a common DAS boundary compatibility designation.
[0239] Because the central lower portion of the DAS halo region
2605 of DAS 2600 is occupied by DAS 2602, the central lower portion
of the DAS halo region 2605 of DAS 2600 is eliminated. Similarly,
because the central upper portion of the DAS halo region 2615 of
DAS 2602 is occupied by DAS 2600, the central upper portion of the
DAS halo region 2615 of DAS 2602 is eliminated. Also, upon
placement of DASs 2600 and 2602 on the DAS grid, as shown in FIG.
26C-1, a DAS halo overlap region 2621 results. Specifically, in the
overlap region 2621, the outer lower portions of DAS halo region
2605 of DAS 2600 and the outer upper portions of DAS halo region
2615 of DAS 2602 overlap each other.
[0240] In one embodiment, placement of multiple DASs on the DAS
grid is controlled such that the pre-defined content of DAS halo
region portions within the DAS halo overlap region are compatible
so as to not adversely impact the manufacturability of features in
any of the multiple DAS s. For example, with regard to FIG. 26C-1,
the content of the DAS halo region 2605 and the DAS halo region
2615 within the DAS halo overlap region 2621 actually aligns so as
to maintain the original pre-defined content of DAS halo regions
2605 and 2615. However, it should be understood that the resulting
content of a DAS halo overlap region is not strictly required to
maintain the original pre-defined content of the respective DAS
halo regions involved in the overlap, so long as the resulting
content of the DAS halo overlap region does not adversely impact
the manufacturability of features within a neighboring DAS.
[0241] In another embodiment, a number of DAS s are placed on a DAS
grid without their respective DAS halo region contents to form a
DAS cluster. In this embodiment, the various DASs are placed
according to their DAS boundary compatibility designations without
regard to associated DAS halo contents. For example, FIG. 26C-2 is
an illustration showing an exemplary placement of DAS 2600 and DAS
2602 on a DAS grid without regard to their respective DAS halos, in
accordance with one embodiment of the present invention. In the
embodiment of FIG. 26C-2, each of DASs 2600 and 2602 are placed on
the DAS grid such that the bottom boundary of DAS 2600 and the top
boundary of DAS 2602 are colinearly aligned, in accordance with
their common DAS boundary compatibility designation. The assembly
of DAS 2600 and DAS 2602 represents a DAS cluster.
[0242] Following placement of the various DASs according to their
DAS boundary compatibility designations to form a DAS cluster, a
DAS halo boundary can be placed around a periphery of the DAS
cluster. For example, FIG. 26C-3 is an illustration showing the DAS
cluster of FIG. 26C-2 having a DAS halo boundary 2625 defined
around the periphery of the DAS cluster to form a DAS halo region
2623. The content of the DAS halo region 2623 can then be defined
as necessary to reinforce/support manufacturability of the various
features in the DASs that make up the DAS cluster. For example,
FIG. 26C-4 is an illustration showing the defined content of the
DAS halo region 2623. A number of reinforcement features 2627 are
shown within the DAS halo region 2623. It should be understood that
the reinforcement features 2627 are shown by way of example, and
are not intended to convey a particular requirement with regard to
length, placement, number, or segmentation of reinforcement
features to be defined within a DAS halo region. In another
embodiment, all or a portion of a DAS halo region defined around a
periphery of the DAS cluster can be left empty, if appropriate for
the successful manufacture of features within the DASs of the DAS
cluster. For example, in this embodiment, all or a portion of the
DAS halo region 2623 may be left empty, i.e., without reinforcement
features 2627.
[0243] Once the DASs are placed on the DAS grid, it may be
necessary to functionally interconnect linear conductive features
from one DAS to another DAS. In one embodiment, a number of DAS
interconnection segments are defined during a place and route
process, wherein each DAS interconnection segment is defined to
connect a linear conductive feature in a given level of a first DAS
to a coaligned linear conductive feature in the given level of a
second DAS adjacent to the first DAS. For example, FIG. 26C-5 is an
illustration showing the particular level of the DAS cluster of
FIG. 26C-4 having a number of DAS interconnection segments 2629
defined therein. It should be understood that the DAS
interconnection segments 2629 are shown by way of example, and are
not intended to convey a particular requirement with regard to
length, placement, or number of DAS interconnection segments to be
defined between DASs.
[0244] FIG. 26D-1 is an illustration showing a flowchart of a
method for defining a dynamic array architecture region of a
semiconductor chip, in accordance with one embodiment of the
present invention. The method includes an operation 2631 for
placing a number of DASs with their corresponding DAS halos on a
DAS grid to form a DAS cluster. When placing the number of DAS s on
the DAS grid, each DAS halo portion that would overlie an interior
region of another DAS is excluded. Thus, each location on the DAS
grid can be occupied by either a DAS interior region or a DAS halo
region, but not both. This concept is previously described with
regard to FIG. 26C-1. Upon placement of the DASs with their
corresponding DAS halos on the DAS grid, the remaining portions of
the DAS halos and their respective contents in a given level of the
chip are adopted to form the DAS halo for the DAS cluster in the
given level of the chip.
[0245] The method also includes an operation 2633 for defining
necessary DAS-to-DAS functional interconnections within each level
of the DAS cluster. The DAS-to-DAS functional interconnections
correspond to the DAS interconnections as previously described with
regard to FIG. 26C-5. In one embodiment, operation 2633 for
defining the necessary DAS interconnections is performed during a
place and route process. However, in other embodiments, operation
2633 can be performed outside of a place and route process.
[0246] FIG. 26D-2 is an illustration showing a flowchart of a
method for defining a dynamic array architecture region of a
semiconductor chip, in accordance with one embodiment of the
present invention. The method includes an operation 2641 for
placing a number of DASs on a DAS grid to form a DAS cluster,
without regard to the various DAS halos associated with the number
of DASs. The method also includes an operation 2643 for defining a
DAS halo boundary around a periphery of the DAS cluster, so as to
form a DAS halo region outside the periphery of the DAS cluster. An
operation 2645 is then performed to define the contents of the DAS
halo region to ensure manufacturability of features within the DASs
than form the DAS cluster. In various embodiments, the contents of
the DAS halo region can include a number of reinforcement features
defined with regard to orientation, size, and spacing, so as to
reinforce the manufacture of features within the DASs of the DAS
cluster. Also, in some embodiments, one or more portions of the DAS
halo region can be left empty, i.e., without reinforcement
features.
[0247] The method further includes an operation 2647 for defining
necessary DAS-to-DAS functional interconnections within each level
of each DAS that forms the DAS cluster. The DAS-to-DAS functional
interconnections correspond to the DAS interconnections as
previously described with regard to FIG. 26C-5. In one embodiment,
operation 2647 for defining the necessary DAS interconnections is
performed during a place and route process. However, in other
embodiments, operation 2647 can be performed outside of a place and
route process.
[0248] It should be understood that a DAS can be defined to form a
portion of one or more logic cells, one or more complete logic
cells, or a combination of complete and partial logic cells. In one
embodiment, logic cell boundaries contain an integer multiple of
gate electrode features. More specifically, in this embodiment,
logic cell boundaries that run parallel to the gate electrode
features fall on the gate electrode half-pitch. Thus, in this
embodiment, logic cell boundaries are defined based on the gate
electrode level virtual grate, such that the logic cell boundaries
fall on the gate electrode half-pitch. Each logic cell is defined
to have a cell height and a cell width when viewed in a direction
perpendicular to the plane of the substrate. In one embodiment, the
relationship between the conductive feature spacings in the first
and third interconnect levels allows for a selection of the logic
cell height so that the conductive features of the first and third
interconnect levels align at the height-defining logic cell
borders.
[0249] The conductive features in a given level of the logic cell,
i.e., in a given level of the DAS containing the logic cell, are
indexed relative to an origin of the logic cell. For discussion
purposes, the origin of the logic cell in a given level is
considered to be located at a lower left corner of the logic cell
when viewed in a direction perpendicular to the plane of the
substrate. Because logic cell widths are variable, a logic cell
boundary in the width direction may not always fall on a conductive
feature pitch or half-pitch within a given DAS level (above the
gate electrode level). Therefore, depending on the origin of the
logic cell relative to the virtual grate of the given DAS level,
the conductive features in the given DAS level may need to be
shifted relative to the logic cell origin in order to align with
the virtual grate of the given DAS level. The shifting of
conductive features in a given level of a logic cell relative of
the origin of the logic cell is called phasing. Therefore, phasing
provides for alignment of conductive features in a given level of a
logic cell to the virtual grate of the DAS for the given level,
depending on the location of the origin of the logic cell. For
example, in the case where the gate electrode virtual grate extends
across logic cell boundaries, phasing may be required to maintain
alignment of second interconnect level conductive features in a
given logic cell to the second interconnect level virtual
grate.
[0250] FIG. 33 is an illustration showing an example of different
phasings in a second interconnect level of adjacently disposed
logic cells defined within a DAS, in accordance with one embodiment
of the present invention. FIG. 33 shows three exemplary cells (Cell
1, Phase A; Cell 1, Phase B; and Cell 1, Phase C) disposed adjacent
to each other in a DAS. Therefore, each of the three cells share a
virtual grate in each level of the DAS. To facilitate description
of the phasing concept, the second interconnect level conductive
features 3303 of each cell are shown superimposed over the gate
electrode level conductive features 3301 of each cell. The cell
boundaries in the width direction fall on the gate electrode
half-pitch. Also, the second interconnect level and gate electrode
level conductive features spacings are defined based on a 4:3 pitch
ratio, such that four second interconnect level conductive feature
pitches are provided for every three gate electrode level
conductive feature pitches. The original of each cell is shown to
reside at the cell's lower left corner.
[0251] Each phasing of Cell 1 for the second interconnect level is
defined by an indexing of the second interconnect level conductive
features to the origin of the cell. As shown in the example of FIG.
33, the index, i.e., spacing, of the second interconnect level
conductive features relative to the origin is consecutively reduced
for each of Phases A, B, and C. By defining each level of each
logic cell to have an appropriate phase, it is possible to place
logic cells next to one another in a common DAS such that
conductive features defined within the various logic cells within a
given DAS level can be aligned to a common virtual grate associated
with the given DAS level. Additionally, it should be appreciated
that adjacent cells within a DAS can be defined and placed so as to
share conductive features in one or more levels of the DAS. For
example, the Phase B and C instances of Cell 1 in FIG. 33 are
depicted as sharing gate electrode level and second interconnect
level conductive features.
[0252] FIG. 27A is an illustration showing an exemplary DAS 2700
that defines a logic cell, in accordance with one embodiment of the
present invention. By way of example, the DAS 2700 defines a
complete logic cell. The view of DAS 2700 in FIG. 27A shows a
number of diffusion regions 2703 defined within a portion of a
substrate, a number of diffusion contacts 2705, a number of gate
electrode linear conductive features 2707, and a number gate
electrode contacts 2709. A DAS boundary 2701 is defined about the
periphery of the DAS 2700. In some embodiments, such as the DAS10
example previously described with regard to FIGS. 18-24D, each
component of the DAS is defined within the DAS boundary. However,
in some embodiments, DAS interior features such as diffusion
regions and diffusion contacts can be defined to extend beyond the
DAS boundary and continue to be considered an integral component of
the DAS. For example, in the DAS 2700, the diffusion regions 2703
and a number of the diffusion contacts 2705 are defined to extend
beyond the DAS boundary 2701. The portions of the diffusion regions
2703 and diffusion contacts 2705 that extend outside of the DAS
boundary 2701 remain integral components of the DAS 2700.
[0253] Extension of DAS components beyond the DAS boundary may
enable sharing of the extended DAS components by one or more
neighboring DASs. For example, FIG. 27B shows a number of instances
of the example DAS 2700 placed adjacent to each other so as to
share DAS components that extend beyond the DAS boundary. More
specifically, DAS instances 2701A and 2701B are oriented in the
same way as the example DAS 2700, and are placed next to each other
such that their neighboring boundary segments are colinear. The
placement of DAS instances 2701A and 2701B enables a sharing of
diffusion region portions and diffusion contact portions between
the DAS instances 2701A and 2701B. Each of DAS instances 2701C and
2701D represents the example DAS 2700 having been flipped in the
y-direction. Each of DAS instances 2701C and 2701D are placed next
to each other such that their neighboring boundary segments are
colinear. The placement of DAS instances 2701C and 2701D enables a
sharing of diffusion region portions and diffusion contact portions
between the DAS instances 2701C and 2701D. Also, placement of DAS
instances 2701C and 2701D enables sharing of diffusion region
portions and diffusion contact portions between the DAS instances
2701C and 2701A, between the DAS instances 2701C and 2701B, and
between the DAS instances 2701D and 2701B.
[0254] FIG. 28A is an illustration showing a flowchart of a method
for designing a semiconductor chip having one or more functionally
interfaced dynamic array sections (DASs), in accordance with one
embodiment of the present invention. The method includes an
operation 2801 for laying out a virtual grate for conductive
features used to define a gate electrode level of a DAS. The
virtual grate is defined by a framework of parallel lines defined
at a substantially constant pitch. An operation 2803 is provided
for arranging one or more conductive features along every line of
the virtual grate. Each conductive feature is arranged on a given
line of a given virtual grate such that a width of the conductive
feature is substantially centered upon the given line of the given
virtual grate. As previously mentioned, the width of the conductive
feature is measured in a coplanar and perpendicular relationship
relative to the framework of parallel lines that define the virtual
grate along which the conductive feature is arranged.
[0255] It should be appreciated that the arrangement of conductive
features in operation 2803 is performed to form transistor devices
and enable interconnection of the transistor devices and other
electronic components (e.g., resistors, diodes, capacitors, etc.)
to form a functional electronic circuit. For each line of the
virtual grate, an operation 2805 is performed to define a gap
between proximate ends of each pair of adjacent conductive features
which are arranged along a common line of the virtual grate. Each
gap is defined to maintain a substantially consistent separation
between proximate ends of conductive features. Within the gate
electrode level of the DAS, some of the conductive features are
designed to define gate electrodes of transistor devices. In one
embodiment, a size of each gap defined between proximate ends of
each pair of adjacent conductive features in a given level of the
dynamic array section is minimized within electrical performance
constraints so as to maximize an overall conductive feature
occupancy of the lines that define the virtual grate of the given
level. Also, in one embodiment, arrangement of the one or more
conductive features along every line of the virtual grate of a
given level of the DAS is performed to avoid adjacent gaps in
adjacent lines that define the virtual grate of the given
level.
[0256] The method further includes an operation 2807 for defining
each conductive feature to be devoid of a substantial change in
direction, such that the conductive features remain substantially
aligned to the framework of parallel lines of the virtual grate. In
one embodiment, a substantial change in direction of any given
conductive feature exists when a width of the given conductive
feature at any point thereon changes by more than 50% of a nominal
width of the given conductive feature. In another embodiment, a
substantial change in direction of any given conductive feature
exists when a width of the given conductive feature changes from
any first location on the given conductive feature to any second
location on the given conductive feature by more than 50% of the
given conductive feature width at the first location.
[0257] FIG. 28B is an illustration showing a continuation of the
flowchart of the method of FIG. 28A, in accordance with one
embodiment of the present invention. An operation 2809 is performed
to lay out another virtual grate for conductive features used to
define conductive lines of another level of the DAS. The other
virtual grate of operation 2809 is defined by a framework of
parallel lines defined at a substantially constant pitch. Also, the
other virtual grate of operation 2809 is defined such that each
virtual grate of the DAS is perpendicular to an adjacent level
virtual grate. An operation 2811 is performed to arrange one or
more conductive features along every line of the other virtual
grate laid out in operation 2809. In operation 2811, the conductive
features are arranged along every line of the virtual grate laid
out in operation 2809 so as to enable interconnection of the
transistor devices and other electronic components (e.g.,
resistors, diodes, capacitors, etc.) to form a functional
electronic circuit.
[0258] For each line of the virtual grate laid out in operation
2809, an operation 2813 is performed to define a gap between
proximate ends of each pair of adjacent conductive features which
are arranged along a common line of the virtual grate, such that
each gap is defined to maintain a substantially consistent
separation between proximate ends of each pair of adjacent
conductive features arranged along the virtual grate. Also, in an
operation 2815 each conductive feature arranged in operation 2811
is defined to be devoid of a substantial change in direction, such
that the conductive features remain substantially aligned to the
framework of parallel lines of the virtual grate. The method
further includes an operation 2817 for designing additional levels
of the DAS by repeating operations 2809 through 2815.
[0259] Additionally, the method includes an operation 2819 for
defining a number of gate electrode contacts to electrically
connect the conductive features designed to define gate electrodes
of transistor devices in the gate electrode level of the DAS to
conductive features defined in one or more other levels of the DAS.
Each gate electrode contact is defined to perpendicularly overlap a
conductive feature designed to define a gate electrode of a
transistor device in the gate electrode level of the DAS. An
operation 2820 is also provided for defining a number of diffusion
contacts to electrically connect the source/drain regions of the
transistor devices in the DAS to conductive features defined in one
or more levels of the DAS. An operation 2821 is also provided for
defining a number of vias within the DAS so as to electrically
connect conductive features within different levels of the DAS so
as to form the functional electronic circuit.
[0260] FIG. 28C is an illustration showing an expansion of the
operation 2809 of FIG. 28B, in accordance with one embodiment of
the present invention. An operation 2823 is provided to identify
the substantially constant pitch used to define the virtual grate
for a given one of the levels of the DAS that is oriented in the
same direction as the other virtual grate to be laid out in
operation 2809. An operation 2825 is then performed to determine a
pitch relationship between the substantially constant pitch
identified in operation 2823 and the substantially constant pitch
to be used to define the other virtual grate to be laid out in
operation 2809. An operation 2827 is then performed to use the
substantially constant pitch identified in operation 2823 and the
pitch relationship determined in operation 2825 to determine the
substantially constant pitch to be used to define the other virtual
grate to be laid out in 2809.
[0261] In one embodiment, the pitch relationship determined in
operation 2825 defines a pitch multiplier by which the
substantially constant pitch identified in operation 2823 is to be
multiplied to determine the substantially constant pitch to be used
to define the other virtual grate laid out in operation 2809. In
one embodiment, considering that the level of the DAS for which the
substantially constant pitch is identified in operation 2823 is the
first interconnect level of the dynamic array section (above the
gate electrode level of the DAS), and considering that the other
level of the DAS defined by the other virtual grate to be laid out
in 2809 is a third interconnect level of the DAS, the pitch
relationship determined in operation 2825 is given by,
3 rd_level _pitch = [ ( 2 ) ( 1 st_level _power _pitch ) ] + [ ( b
- 1 ) ( 1 st_level _pitch ) ] ( a - 1 ) . Equation 2
##EQU00002##
wherein (3rd_level_pitch) is the substantially constant pitch by
which the virtual grate of the third interconnect level is defined,
wherein (1st_level_power_pitch) is a center-to-center separation
between a power rail in the first interconnect level and an
adjacent conductive feature in the first interconnect level,
wherein the power rail is a conductive feature used to supply
either power or ground to the dynamic array section, wherein
(1st_level_pitch) is the substantially constant pitch by which the
virtual grate of the first interconnect level is defined, wherein
(a) is the number of parallel lines defined within the virtual
grate of the third interconnect level, and wherein (b) is the
number of parallel lines defined within the virtual grate of the
first interconnect level not including the virtual lines for power
rails.
[0262] In one embodiment, the substantially constant pitch that
defines the framework of parallel lines of the virtual grate for a
given level is set to optimize lithographic reinforcement during
manufacture of the conductive features arranged along the lines of
the virtual grate for the given level. In another embodiment, the
substantially constant pitch that defines the framework of parallel
lines of the virtual grate for a given level is set to optimize a
density of the conductive features arranged along the lines of the
virtual grate for the given level. In yet another embodiment, the
substantially constant pitch that defines the framework of parallel
lines of the virtual grate for a given level is set to enable
accurate prediction of the manufacturability of the conductive
features arranged along the lines of the virtual grate for the
given level.
[0263] It should be understood that some of the conductive features
in one or more levels of the dynamic array section can be
non-functional features with respect to electrical circuit
functionality. Such non-functional features are defined to enhance
manufacturability of other conductive features. In one embodiment,
some of the non-functional features are omitted in locations where
enhancement of manufacturability of other conductive features by
the non-functional features is not required. Additionally, it
should be understood that a given line of a virtual grate used to
define any of the levels of the DAS can have arranged thereon one
or more non-functional features such that the given line is
completely occupied by the one or more non-functional features.
Also, it should be understood that a given line of a virtual grate
used to define any of the levels of the DAS can have arranged
thereon one or more conductive features that do not include any
non-functional features. It should be further understood that a
given line of a virtual grate used to define any of the levels of
the DAS can have arranged thereon a number of conductive features
that are functional features with respect to electrical circuit
functionality, and a number of non-functional features.
[0264] FIG. 29A is an illustration showing a flowchart of a method
for designing a semiconductor chip having one or more functionally
interfaced dynamic array sections, in accordance with one
embodiment of the present invention. The method includes an
operation 2901 for defining a DAS grid on a portion of the chip.
The DAS grid is defined by a virtual network of perpendicular
gridlines projected upon the portion of the chip. An operation 2903
is performed to define boundaries of a DAS, such that each of the
defined boundaries of the DAS aligns with a gridline of the DAS
grid. The DAS represents a portion of the chip defined according to
the dynamic array architecture. It should be understood that the
DAS can be defined to have essentially any two-dimensional shape
having each boundary thereof defined along a gridline of the DAS
grid. The method also includes an operation 2905 for defining one
or more diffusion regions to be formed within a substrate portion
of the DAS. An operation 2907 is further provided for defining a
plurality of levels of the chip above the substrate portion within
the DAS.
[0265] FIG. 29B is an illustration showing an expansion of the
operation 2907 of FIG. 29A, in accordance with one embodiment of
the present invention. An operation 2909 is provided for defining a
virtual grate for each of the plurality of levels of the DAS. The
virtual grate of operation 2909 is defined by a framework of
parallel lines spaced at a substantially constant pitch, such that
the framework of parallel lines that define the virtual grate for a
particular level of the DAS are oriented to be substantially
perpendicular to the framework of parallel lines that define the
virtual grate for either a level above or a level below the
particular level. In one embodiment, the substantially constant
pitch used to define the virtual grate for a particular level of
the DAS is determined by a relationship with the substantially
constant pitch used to define the virtual grate for another level
of the DAS having a same orientation as the virtual grate for the
particular level. Also, in one embodiment, the substantially
constant pitch that defines the framework of parallel lines of the
virtual grate for a given level of the DAS is set to enable
accurate prediction of the manufacturability of the linear
conductive features defined along the framework of lines that
define the virtual grate for the given level.
[0266] The method further includes an operation 2911 for defining a
number of linear conductive features along the framework of lines
that define the virtual grate in each of the plurality of levels of
the DAS. Each of the linear conductive features is defined to be
devoid of a substantial change in direction relative to the line of
the virtual grate along which the linear conductive feature is
defined. Some of the lines that define the virtual grates in the
plurality of levels of the DAS have defined thereon multiple linear
conductive features having proximate ends separated by a gap. In
one embodiment, each of these gaps is defined to maintain a
substantially uniform distance between proximate ends of linear
conductive features within a given level of the chip within the
DAS.
[0267] Within a gate electrode level of the DAS, a number of linear
gate electrode features are formed by some of the linear conductive
features defined over one or more of the diffusion regions formed
within the substrate portion. The method further includes an
operation 2913 for defining a number of gate electrode contacts to
electrically connect the linear gate electrode features to linear
conductive features defined in one or more levels above the gate
electrode level. In one embodiment, each of the gate electrode
contacts is defined to perpendicularly overlap a linear gate
electrode feature. An operation 2914 is also provided for defining
a number of diffusion contacts to electrically connect the
source/drain regions of the transistor devices in the DAS to
conductive features defined in one or more levels of the DAS. The
method also includes an operation 2915 for defining a number of
vias within the DAS so as to electrically connect linear conductive
features within different levels of the DAS.
[0268] FIG. 30 is an illustration showing a flowchart of a method
for designing a DAS of a semiconductor chip, in accordance with one
embodiment of the present invention. The method includes an
operation 3001 for defining one or more diffusion regions to be
formed within a substrate portion of the chip. The method also
includes an operation 3003 for defining a plurality of levels of
the DAS above the substrate portion of the chip. Each level of the
DAS is defined to include linear conductive features arranged along
a virtual grate associated with the level. The virtual grate of
each level of the DAS is defined by a framework of parallel lines
spaced at a substantially constant pitch. The virtual grates in
adjacent levels of the DAS are oriented to be perpendicular to each
other.
[0269] The method also includes an operation 3005 for laying out a
full-length linear conductive feature along a full length of each
line of each virtual grate of each level of the DAS. In an
operation 3007, some of the full-length linear conductive features
are segmented into a number of linear conductive segments.
Segmenting of a given full-length linear conductive feature is
performed by placing one or more gaps along the full-length linear
conductive feature. In one embodiment, gaps placed along the
full-length conductive features within a given level of the DAS are
uniformly defined.
[0270] Throughout the DAS, a first portion of the linear conductive
segments are defined to form conductive elements of an electronic
circuit. Correspondingly, a remaining portion of the linear
conductive segments are defined to support manufacturing of the
first portion and do not form conductive elements of the electronic
circuit. Additionally, each linear conductive segment throughout
the DAS is defined to be devoid of a substantial change in
direction relative to the line of the virtual grate along which the
linear conductive segment is laid out.
[0271] The method further includes an operation 3009 for defining a
number of gate electrode contacts to electrically connect
conductive features within a gate electrode level of the DAS, i.e.,
linear gate electrode features, to linear conductive features
defined in one or more levels above the gate electrode level of the
DAS. In one embodiment, each of the gate electrode contacts is
defined to perpendicularly overlap a linear gate electrode feature.
An operation 3010 is also provided for defining a number of
diffusion contacts to electrically connect the source/drain regions
of the transistor devices in the DAS to conductive features defined
in one or more levels of the DAS. The method further includes an
operation 3011 for defining a number of vias within the dynamic
array section so as to electrically connect linear conductive
features or segments thereof within different levels of the
DAS.
[0272] FIG. 31 is an illustration showing a flowchart of a method
for defining a dynamic array section to be manufactured on a
semiconductor chip, in accordance with one embodiment of the
present invention. The method includes an operation 3101 for
defining a peripheral boundary of the dynamic array section. The
method also includes an operation 3103 for defining a manufacturing
assurance halo outside the boundary of the dynamic array section.
An extent of the manufacturing assurance halo in a perpendicular
direction away from the peripheral boundary of the dynamic array
section is defined to ensure that each chip layout feature defined
outside of the manufacturing assurance halo is not capable of
adversely affecting the manufacturing of conductive features inside
the boundary of the dynamic array section. In one embodiment, a
number of the conductive features inside the boundary of the
dynamic array section are defined to extend beyond the boundary of
the dynamic array section through the manufacturing assurance halo.
Also, in one embodiment, an outer periphery of the manufacturing
assurance halo aligns with gridlines of a dynamic array section
grid used to align the peripheral boundary of the dynamic array
section. Also in one embodiment, the dynamic array section is
defined by a plurality of levels of the chip within the boundary of
the dynamic array section, and a separate manufacturing assurance
halo is independently and respectively defined for each of the
plurality of levels of the dynamic array section.
[0273] The method further includes an operation 3105 for
controlling chip layout features within the manufacturing assurance
halo to ensure that manufacturing of conductive features inside the
boundary of the dynamic array section is not adversely affected by
chip layout features within the manufacturing assurance halo. In
one embodiment, controlling chip layout features within the
manufacturing assurance halo is performed by placing the dynamic
array section on the chip such that chip layout features not
associated with the dynamic array section are only allowed to
encroach within the manufacturing assurance halo when such
encroachment does not adversely affect manufacturing of conductive
features inside the boundary of the dynamic array section.
[0274] In one embodiment, the boundary of the dynamic array section
is defined by a circuitous arrangement of boundary segments. Each
boundary segment has an associated manufacturing assurance halo
segment. Also, each manufacturing assurance halo segment is
assigned a manufacturing compatibility identifier. In this
embodiment, controlling chip layout features within the
manufacturing assurance halo is performed by placing the dynamic
array section on the chip such that each manufacturing assurance
halo segment is allowed to overlap a manufacturing assurance halo
segment of a neighboring dynamic array section having a same
manufacturing compatibility identifier. Also in this embodiment,
controlling chip layout features within the manufacturing assurance
halo is performed by placing the dynamic array section on the chip
such that each manufacturing assurance halo segment is not allowed
to overlap a manufacturing assurance halo segment of a neighboring
dynamic array section having a different manufacturing
compatibility identifier.
[0275] FIG. 32 is an illustration showing a flowchart of a method
for designing a semiconductor chip having one or more functionally
interfaced dynamic array sections, in accordance with one
embodiment of the present invention. The method includes an
operation 3201 for selecting a dynamic array section to be defined
on a portion of the chip. The selected dynamic array section has an
associated manufacturing assurance halo defined outside a boundary
of the selected dynamic array section. The method also includes an
operation 3203 for placing the selected dynamic array section
within a layout of the portion of the chip, such that layout
features not associated with the selected dynamic array section and
within the manufacturing assurance halo are compatible with the
manufacturing assurance halo so as to avoid adversely impacting
manufacturability of the selected dynamic array section.
[0276] In one embodiment, the selected dynamic array section is
defined by a plurality of levels of the chip within the boundary of
the selected dynamic array section. In this embodiment, a separate
manufacturing assurance halo is independently and respectively
associated with each of the plurality of levels of the selected
dynamic array section. An extent of each manufacturing assurance
halo in a perpendicular direction away from the boundary of the
selected dynamic array section is defined to ensure that each chip
layout feature defined outside of the manufacturing assurance halo
is not capable of adversely affecting the manufacturing of
conductive features inside the boundary of the selected dynamic
array section.
[0277] In one embodiment of the method of FIG. 32, the boundary of
the selected dynamic array section is defined by a circuitous
arrangement of boundary segments, and each boundary segment has an
associated manufacturing assurance halo segment. Each manufacturing
assurance halo segment is assigned a manufacturing compatibility
identifier. In this embodiment, operation 3203 is performed by
placing the selected dynamic array section within the layout of the
portion of the chip such that each manufacturing assurance halo
segment is allowed to overlap a manufacturing assurance halo
segment of a neighboring dynamic array section having a same
manufacturing compatibility identifier. Also in this embodiment,
operation 3203 is performed by placing the selected dynamic array
section within the layout of the portion of the chip such that each
manufacturing assurance halo segment is not allowed to overlap a
manufacturing assurance halo segment of a neighboring dynamic array
section having a different manufacturing compatibility
identifier.
[0278] In one embodiment, operation 3203 is performed by placing
the selected dynamic array section within the layout of the portion
of the chip such that a number of manufacturing assurance halo
segments are separated from a number of manufacturing assurance
halo segments of one or more neighboring dynamic array sections
having a same manufacturing compatibility identifier, thereby
leaving a space between the selected dynamic array section and the
one or more neighboring dynamic array sections. In a further
instance of this embodiment, a chip layout feature not associated
with a dynamic array section is defined within the space between
the selected dynamic array section and the one or more neighboring
dynamic array sections.
[0279] The invention described herein can be embodied as computer
readable code on a computer readable medium. The computer readable
medium is any data storage device that can store data which can be
thereafter be read by a computer system. Examples of the computer
readable medium include hard drives, network attached storage
(NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs,
CD-RWs, magnetic tapes, and other optical and non-optical data
storage devices. The computer readable medium can also be
distributed over a network coupled computer systems so that the
computer readable code is stored and executed in a distributed
fashion. Additionally, a graphical user interface (GUI) implemented
as computer readable code on a computer readable medium can be
developed to provide a user interface for performing any embodiment
of the present invention.
[0280] While this invention has been described in terms of several
embodiments, it will be appreciated that those skilled in the art
upon reading the preceding specifications and studying the drawings
will realize various alterations, additions, permutations and
equivalents thereof. Therefore, it is intended that the present
invention includes all such alterations, additions, permutations,
and equivalents as fall within the true spirit and scope of the
invention.
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