U.S. patent application number 16/593459 was filed with the patent office on 2020-01-30 for cell circuit and layout with linear finfet structures.
The applicant listed for this patent is Tela Innovations, Inc.. Invention is credited to Scott T. Becker.
Application Number | 20200035663 16/593459 |
Document ID | / |
Family ID | 43063125 |
Filed Date | 2020-01-30 |
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United States Patent
Application |
20200035663 |
Kind Code |
A1 |
Becker; Scott T. |
January 30, 2020 |
Cell Circuit and Layout with Linear Finfet Structures
Abstract
A cell circuit and corresponding layout is disclosed to include
linear-shaped diffusion fins defined to extend over a substrate in
a first direction so as to extend parallel to each other. Each of
the linear-shaped diffusion fins is defined to project upward from
the substrate along their extent in the first direction. A number
of gate level structures are defined to extend in a conformal
manner over some of the number of linear-shaped diffusion fins.
Portions of each gate level structure that extend over any of the
linear-shaped diffusion fins extend in a second direction that is
substantially perpendicular to the first direction. Portions of
each gate level structure that extend over any of the linear-shaped
diffusion fins form gate electrodes of a corresponding transistor.
The diffusion fins and gate level structures can be placed in
accordance with a diffusion fin virtual grate and a gate level
virtual grate, respectively.
Inventors: |
Becker; Scott T.; (Scotts
Valley, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Tela Innovations, Inc. |
Los Gatos |
CA |
US |
|
|
Family ID: |
43063125 |
Appl. No.: |
16/593459 |
Filed: |
October 4, 2019 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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15426674 |
Feb 7, 2017 |
10446536 |
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16593459 |
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12775429 |
May 6, 2010 |
9563733 |
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15426674 |
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61176058 |
May 6, 2009 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06F 2119/18 20200101;
H01L 21/845 20130101; H01L 27/088 20130101; Y02P 90/02 20151101;
G06F 2111/04 20200101; G06F 30/392 20200101; H01L 29/785 20130101;
H01L 27/0207 20130101; H01L 21/302 20130101; H01L 27/092 20130101;
G06F 30/39 20200101; Y02P 90/265 20151101; H01L 27/0924
20130101 |
International
Class: |
H01L 27/02 20060101
H01L027/02; H01L 27/092 20060101 H01L027/092; H01L 27/088 20060101
H01L027/088; H01L 29/78 20060101 H01L029/78; G06F 17/50 20060101
G06F017/50 |
Claims
1. An integrated circuit, comprising: a substrate; a diffusion fin
of a first diffusion type extending over the substrate; a first
local interconnect structure electrically contacting the diffusion
fin of the first diffusion type; a diffusion fin of a second
diffusion type extending over the substrate; a second local
interconnect structure electrically contacting the diffusion fin of
the second diffusion type, the first and second local interconnect
structures extending lengthwise along a same line; a first gate
structure extending over and electrically contacting both the
diffusion fin of the first diffusion type and the diffusion fin of
the second diffusion type, the first gate structure extending along
at least a portion of a first side of the first local interconnect
structure and along at least a portion of a first side of the
second local interconnect structure; and a second gate structure
extending over and electrically contacting both the diffusion fin
of the first diffusion type and the diffusion fin of the second
diffusion type, the second gate structure extending along at least
a portion of a second side of the first local interconnect
structure and along at least a portion of a second side of the
second local interconnect structure.
2. The integrated circuit as recited in claim 1, wherein the first
local interconnect structure is linear-shaped, and wherein the
second local interconnect structure is linear-shaped.
3. The integrated circuit as recited in claim 2, wherein the first
gate structure is linear-shaped, and wherein the second gate
structure is linear-shaped.
4. The integrated circuit as recited in claim 3, wherein the first
gate structure is spaced apart from the first local interconnect
structure by a first distance as measured perpendicularly between
lengthwise centerlines of the first gate structure and the first
local interconnect structure, and wherein the second gate structure
is spaced apart from the first local interconnect structure by a
second distance as measured perpendicularly between lengthwise
centerlines of the second gate structure and the first local
interconnect structure, wherein the second distance is
substantially equal to the first distance.
5. The integrated circuit as recited in claim 1, wherein an overall
length of the first gate structure as measured along a lengthwise
centerline of the first gate structure is substantially equal to an
overall length of the second gate structure as measured along a
lengthwise centerline of the second gate structure.
6. The integrated circuit as recited in claim 5, wherein a first
end of the first gate structure and a first end of the second gate
structure are positioned at a first line that extends perpendicular
to the lengthwise centerline of the first local interconnect
structure, and wherein a second end of the first gate structure and
a second end of the second gate structure are positioned at a
second line that extends perpendicular to the lengthwise centerline
of the second local interconnect structure.
7. The integrated circuit as recited in claim 1, wherein a width of
the first gate structure as measured perpendicular to a lengthwise
centerline of the first gate structure is substantially equal to a
width of the second gate structure as measured perpendicular to a
lengthwise centerline of the second gate structure.
8. The integrated circuit as recited in claim 1, wherein a width of
the first local interconnect structure as measured perpendicular to
a lengthwise centerline of the first local interconnect structure
is substantially equal to a width of the second local interconnect
structure as measured perpendicular to a lengthwise centerline of
the second local interconnect structure.
9. The integrated circuit as recited in claim 1, wherein the first
local interconnect structure is electrically connected to a first
power line, and wherein the second local interconnect structure is
electrically connected to a second power line.
10. The integrated circuit as recited in claim 1, further
comprising: a plurality of diffusion fins of the first diffusion
type, wherein said diffusion fin of the first diffusion type is one
of the plurality of diffusion fins of the first diffusion type,
wherein the first local interconnect structure electrically
contacts each of the plurality of diffusion fins of the first
diffusion type.
11. The integrated circuit as recited in claim 10, wherein the
first gate structure extends over and electrically contacts each of
the plurality of diffusion fins of the first diffusion type.
12. The integrated circuit as recited in claim 11, wherein the
second gate structure extends over and electrically contacts each
of the plurality of diffusion fins of the first diffusion type.
13. The integrated circuit as recited in claim 12, further
comprising: a plurality of diffusion fins of the second diffusion
type, wherein said diffusion fin of the second diffusion type is
one of the plurality of diffusion fins of the second diffusion
type, wherein the second local interconnect structure electrically
contacts each of the plurality of diffusion fins of the second
diffusion type.
14. The integrated circuit as recited in claim 13, wherein the
plurality of diffusion fins of the first diffusion type includes
three diffusion fins of the first diffusion type.
15. The integrated circuit as recited in claim 14, wherein the
plurality of diffusion fins of the second diffusion type includes
three diffusion fins of the second diffusion type.
16. The integrated circuit as recited in claim 1, wherein the first
gate structure and the second gate structure are positioned in
accordance with a fixed centerline-to-centerline pitch.
17. The integrated circuit as recited in claim 1, further
comprising: a third local interconnect structure electrically
contacting both the diffusion fin of the first diffusion type and
the diffusion fin of the second diffusion type.
18. The integrated circuit as recited in claim 17, wherein the
third local interconnect structure is linear-shaped.
19. The integrated circuit as recited in claim 18, wherein the
third local interconnect structure is electrically connected to a
higher level interconnect structure.
20. The integrated circuit as recited in claim 18, wherein the
third local interconnect structure is positioned next to either the
first gate structure or the second gate structure.
Description
CLAIM OF PRIORITY
[0001] This application is a continuation application under 35
U.S.C. 120 of prior U.S. application Ser. No. 15/426,674, filed on
Feb. 7, 2017, which is a continuation application under 35 U.S.C.
120 of prior U.S. application Ser. No. 12/775,429, filed on May 6,
2010, issued as U.S. Pat. No. 9,563,733, on Feb. 7, 2017, which
claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent
Application No. 61/176,058, filed May 6, 2009. The disclosure of
each above-identified patent application is incorporated herein by
reference in its entirety for all purposes.
BACKGROUND
[0002] It is known that optical lithography has reached the end of
its capability at the 193 nm light wavelength and 1.35 numerical
aperture (NA) immersion system. The minimum straight line
resolution capability of this equipment is approximately 40 nm with
an approximate 80 nm feature-to-feature pitch. A feature-to-feature
pitch requirement lower than about 80 nm would require multiple
patterning steps for a given structure type within a given chip
level. Also, line end resolution becomes more challenging as
lithography is pushed toward its resolution limits. One solution to
line end shortening is to add a subsequent patterning step to cut
features so as to form the line ends. Such line end cutting allows
two line ends to be placed in closer proximity, and therefore may
improve overall feature placement density, but at the cost of an
additional patterning step. It should be understood that the added
lithography steps for multiple patterning and/or line end cutting
increases manufacturing cost, possibly to the point where any
improvement in feature placement density is financially
negated.
[0003] In semiconductor device layout, a typical metal line pitch
at the 32 nm critical dimension is approximately 100 nm. In order
to achieve the cost benefit of feature scaling, a scaling factor of
0.7 to 0.75 is desirable. The scaling factor of about 0.75 to reach
the 22 nm critical dimension would require a metal line pitch of
about 75 nm, which is below the capability of current single
exposure lithography systems and technology.
SUMMARY
[0004] In one embodiment, a cell circuit of a semiconductor device
is disclosed. The cell circuit includes a substrate, and a number
of linear-shaped diffusion fins defined to extend over the
substrate in a first direction so as to extend parallel to each
other. Each of the number of linear-shaped diffusion fins is
defined to project upward from the substrate along their extent in
the first direction. The cell circuit also includes a number of
gate level structures defined to extend in a conformal manner over
some of the number of linear-shaped diffusion fins. Portions of
each gate level structure that extend over any of the number of
linear-shaped diffusion fins extend in a second direction that is
substantially perpendicular to the first direction. Portions of
each gate level structure that extend over any of the number of
linear-shaped diffusion fins form gate electrodes of a
corresponding transistor.
[0005] In one embodiment, a semiconductor device cell layout is
disclosed. The cell layout includes a diffusion level layout and a
gate level layout. The diffusion level layout includes a number of
diffusion fin layout shapes defined to extend in only a first
direction across the cell layout so as to extend parallel to each
other. Each of the number of diffusion fin layout shapes
corresponds to diffusion fin structures defined to project upward
from a substrate along their extent in the first direction. The
gate level layout includes a number of gate level layout shapes
defined to extend in a second direction across the cell layout that
is substantially perpendicular to the first direction. Each of the
gate level layout shapes corresponds to gate level structures
defined to extend in a conformal manner over some of the diffusion
fin structures that correspond to the diffusion fin layout shapes.
Portions of each gate level structure that extend over any of the
diffusion fin structures form gate electrodes of a corresponding
transistor.
[0006] Other aspects and advantages of the invention will become
more apparent from the following detailed description, taken in
conjunction with the accompanying drawings, illustrating by way of
example the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIGS. 1A and 1B show a layout view of a finfet transistor,
in accordance with one embodiment of the present invention;
[0008] FIG. 2A shows an exemplary cell layout incorporating finfet
transistors, in accordance with one embodiment of the present
invention;
[0009] FIG. 2B shows a vertical cross-section view B-B as called
out in FIG. 2A, in accordance with one embodiment of the present
invention;
[0010] FIG. 2C shows a vertical cross-section view C-C as called
out in FIG. 2A, in accordance with one embodiment of the present
invention;
[0011] FIG. 3A shows an example of gate electrode tracks defined
within the restricted gate level layout architecture, in accordance
with one embodiment of the present invention; and
[0012] FIG. 3B shows the exemplary restricted gate level layout
architecture of FIG. 3A with a number of exemplary gate level
features defined therein, in accordance with one embodiment of the
present invention.
DETAILED DESCRIPTION
[0013] In the following description, numerous specific details are
set forth in order to provide a thorough understanding of the
present invention. It will be apparent, however, to one skilled in
the art that the present invention may be practiced without some or
all of these specific details. In other instances, well known
process operations have not been described in detail in order not
to unnecessarily obscure the present invention.
[0014] A "finfet" is a transistor constructed from a vertical
silicon island. The finfet transistor can also be referred to as a
tri-gate transistor. FIGS. 1A and 1B show a layout view of a finfet
transistor 100, in accordance with one embodiment of the present
invention. The finfet transistor 100 is constructed from a
diffusion island 102 and a gate electrode layer 104. The diffusion
island 102 projects vertically upward from a substrate 105, as
shown in FIG. 1B. A gate oxide layer 106 is disposed between the
diffusion island 102 and the gate electrode layer 104. The
diffusion island 102 can be doped to form either a p-type
transistor or an n-type transistor. The portion of the gate
electrode layer 104 that covers the diffusion island 102 forms the
gate electrode of the finfet transistor 100. Therefore, the gate
electrode of the finfet transistor 100 exists on three sides of the
diffusion island 102, thereby providing for control of the finfet
transistor channel from three sides, as opposed to from one side as
in a non-finfet transistor.
[0015] Transistor scaling has slowed below the 45 nanometers (nm)
critical dimension due to gate oxide limitations and/or
source/drain leakage scaling issues. The finfet transistor
mitigates these issues by controlling the channel of the finfet
transistor from three sides. The increased electrical fields in the
channel of the finfet transistor improve the relationship between
I-on (on drive current) and I-off (sub-threshold leakage current).
Finfet transistors can be employed at the 22 nm critical dimension
and below. However, due to their vertical projection, finfet
transistors can have restricted placement in various circuit
layouts. For instance, there can be a required finfet-to-finfet
minimum spacing and/or a required finfet-to-finfet minimum pitch,
among other restrictions. Embodiments are disclosed herein for cell
layouts that utilize finfet transistors in a manner which
complements layout scaling.
[0016] FIG. 2A shows an exemplary cell layout incorporating finfet
transistors, in accordance with one embodiment of the present
invention. The cell layout is defined by a cell width W and a cell
height H. The cell layout includes a diffusion level within which a
number of diffusion islands 102 are defined for subsequent
formation of finfet transistors and associated connections. The
diffusion islands 102 are also referred to as diffusion fins 102.
In an as-drawn layout state, the diffusion fins 102 are
linear-shaped. The diffusion fins 102 are oriented to be parallel
to each other such that their lengths extend in the direction of
the cell width W.
[0017] In one embodiment, the diffusion fins 102 are placed along a
number of diffusion tracks 201A-201H. The diffusion tracks
201A-201H represent virtual lines that extend in the direction of
the cell width W and are equally spaced at a fixed pitch. The pitch
of the diffusion tracks 201A-201H is related to the cell height H,
such that the diffusion track pitch can be continued across cell
boundaries. Therefore, the diffusion fins 102 for multiple
neighboring cells will be placed in accordance with a common global
set of equally spaced diffusion tracks, thereby facilitating chip
level manufacturing of the diffusion fins 102 in multiple
cells.
[0018] It should be understood that the diffusion fins 102 can be
placed as needed, so long as they are placed in accordance with the
diffusion tracks 201A-201H which have the controlled spatial
relationship with the cell height H. Therefore, some diffusion
tracks 201A-201H may not have a diffusion fin 102 placed thereon.
Also, portions of some diffusion tracks 201A-201H may be vacant
with regard to diffusion fin 102 placement. In other words, some
diffusion tracks 201A-201H will have one or more portions occupied
by diffusion fins 102 and one or more portions not occupied by
diffusion fins 102.
[0019] The cell layout also includes a number of linear-shaped gate
electrode structures 104. The linear-shaped gate electrode
structures 104 extend in a substantially perpendicular direction to
the diffusion fins 102, i.e., in the direction of the cell height
H. The linear-shaped gate electrode structures 104 wrap over the
diffusion fins 102 to form gate electrodes of finfet transistors.
It should be understood that an appropriate gate oxide material is
disposed between the diffusion fins 102 and the gate electrode
structures 104 formed thereover.
[0020] In one embodiment, the linear-shaped gate electrode
structures 104 are placed in accordance with a gate level virtual
grate defined by a set of parallel equally spaced virtual lines
202A-202T that extend in the direction of the cell height H. The
set of virtual lines 202A-202T of the gate level virtual grate are
spaced at a fixed gate pitch. In one embodiment, the gate pitch is
related to the cell width W, such that the gate pitch can be
continued across cell boundaries. Therefore, the gate electrode
structures 104 for multiple neighboring cells will be placed in
accordance with a common global set of equally spaced gate level
virtual grate lines, thereby facilitating chip level manufacturing
of the linear-shaped gate electrode structures 104 in multiple
cells.
[0021] It should be understood that some of the gate level virtual
grate lines 202A-202T may be occupied by gate electrode structures
104, while others of the gate level virtual grate lines 202A-202T
are left vacant. Also, along a given gate level virtual grate line
202A-202T, one or more linear-shaped gate electrode structures 104
can be placed as needed and spaced apart as needed.
[0022] The cell layout also includes a number of linear-shaped
local interconnect structures 203. The local interconnect
structures 203 are oriented parallel to the gate electrode
structures 104. In one embodiment, placement of the local
interconnect structures 203 is defined to be out of phase from
placement of the gate electrode structures 104 by one-half of the
gate pitch. Thus, in this embodiment, each local interconnect
structure 203 is centered between its neighboring gate level
virtual grate lines 202A-202T. And, if its neighboring gate level
virtual grate lines 202A-202T are occupied by gate electrode
structures 104, the local interconnect structure 203 will be
correspondingly centered between the neighboring gate electrode
structures 104. Therefore, in this embodiment, adjacently placed
local interconnect structures 203 will have a center-to-center
spacing equal to the gate pitch.
[0023] In one embodiment, the cell layout also includes a number of
linear-shaped metal 1 (M1) interconnect structures 205. The M1
interconnect structures 205 are oriented parallel to the diffusion
fins 102 and perpendicular to the gate electrode structures 104. In
one embodiment, placement of the M1 interconnect structures 205 is
defined to be out of phase from placement of the diffusion fins 102
by one-half of the diffusion track 201A-201H pitch. Thus, in this
embodiment, each M1 interconnect structure 205 is centered between
its neighboring diffusion tracks 201A-201H. And, if its neighboring
diffusion tracks 201A-201H are occupied by diffusion fins 102, the
M1 interconnect structure 205 will be correspondingly centered
between its neighboring diffusion fins 102, albeit within a higher
chip level. Therefore, in this embodiment, adjacently placed M1
interconnect structures 205 will have a center-to-center spacing
equal to the diffusion track pitch. In one embodiment, the M1
interconnect structure 205 pitch, and hence the diffusion track
pitch, is set at the single exposure lithographic limit, e.g., 80
nm for 193 nm wavelength light and 1.35 NA. In this embodiment, no
double exposure lithography, i.e., multiple patterning, is required
to manufacture the M1 interconnect structures 205.
[0024] The cell layout also includes a number of contacts 207
defined to connect various M1 interconnect structures 205 to
various local interconnect structures 203 and gate electrode
structures 104, thereby providing electrical connectivity between
the various finfet transistors as necessary to implement the logic
function of the cell. In one embodiment, the contacts 205 are
defined to satisfy single exposure lithographic limits. For
example, in one embodiment, layout features to which the contacts
207 are to connect are sufficiently separated to enable single
exposure manufacture of the contacts 207. For instance, the M1
interconnect structures 205 are defined such that their line ends
which are to receive contacts 207 are sufficiently separated from
neighboring M1 interconnect structure 205 line ends which are also
to receive contacts 207, such that a spatial proximity between the
contacts 207 is sufficiently large to enable single exposure
lithography of the contacts 207. In one embodiment, neighboring
contacts 207 are separated from each other by at least 1.5 times
the gate pitch. It should be appreciated that line end cutting and
the associated increased expense of double exposure lithography can
be eliminated by sufficiently separating opposing line ends of the
M1 interconnect structures 205.
[0025] As previously mentioned, the cell height H and diffusion
track pitch, i.e., diffusion fin pitch, are related. In one
embodiment, the cell height H is an integer multiple of the
diffusion track pitch. The cell layout techniques described herein
can be used to reduce the cell height H by the approximate
difference between the single exposure lithographic capability and
an applicable scaling requirement. For example, consider that the
cell height H is based on the single exposure straight line
lithographic limit, e.g., 80 nm diffusion fin pitch. Therefore, the
diffusion track pitch of the cell cannot be scaled down further
without incurring the cost of multiple patterning. However, the
cell layout techniques described herein can be utilized to scale
down the overall size of the cell layout while maintaining the
single exposure straight line lithographic limit with regard to the
diffusion track pitch.
[0026] For example, if a 9 diffusion track cell was used at 32 nm,
then a scaled down version of the cell having 8 tracks at 22 nm is
created to provide the overall cell layout scaling requirements.
Specifically, the M1 interconnect structure 205 layout of the cell
is drawn in fewer tracks, e.g., 8 tracks rather than 9 tracks, and
the opposing line ends of the M1 interconnect structures 205 are
arranged so that the single exposure lithography design rules can
be satisfied. Reduction of the cell height H by one diffusion track
can add up to significant layout area savings across the chip.
[0027] FIG. 2B shows a vertical cross-section view B-B as called
out in FIG. 2A, in accordance with one embodiment of the present
invention. The diffusion fins 102 are shown to project upward from
the substrate 105. An insulating material 211, such as an oxide, is
disposed between and around the diffusion fins 102 to provide
structural support and electrical insulation. The local
interconnect feature 203 is shown to extend perpendicular to the
diffusion fins 102 and across the tops of the diffusion fins 102 so
as to establish electrical connections between the local
interconnect feature 203 and each of the diffusion fins 102. The
contact 207 is shown to extend vertically through the layout to
electrically connect the M1 interconnect structure 205 to the local
interconnect structure 203. The contact 207 and M1 interconnect
structure 205 are also surrounded by the insulating material 211,
which again provides structural support and electrical insulation.
It should be appreciated that the M1 interconnect structure 205 is
positioned in a centered manner with respect to its neighboring
underlying diffusion fins 102, as discussed above.
[0028] FIG. 2C shows a vertical cross-section view C-C as called
out in FIG. 2A, in accordance with one embodiment of the present
invention. The diffusion fin 102 is shown to project upward from
the substrate 105. The gate oxide material 106 is disposed
conformally over the diffusion fin 102. The gate electrode
structure 104 is shown to extend perpendicular to the diffusion fin
102 and conformally over the diffusion fin 102. The contact 207 is
shown to extend vertically to electrically connect the M1
interconnect structure 205 to the gate electrode structure 104. The
insulating material 211, such as an oxide, is disposed over and
around the gate electrode structure 104, the contact 207, and the
M1 interconnect structure 205 to provide structural support and
electrical insulation.
[0029] It should be understood that the relative sizes of the
different layout features as shown in FIGS. 2A-2C are exemplary,
and in no way limit the principles of the present invention as
disclosed herein. For example, in other embodiments, the M1 power
lines shown at the top and bottom of the cell layout in FIG. 2A can
be of different width, e.g., larger width, than the M1 lines within
an interior of the cell. Additionally, the relative vertical
heights of the layout features as shown in the cross-sections of
FIGS. 2B and 2C can vary from what is depicted therein. For
example, in FIG. 2C, the gate electrode 104 may extend further
vertically than what is shown.
Restricted Gate Level Layout Architecture
[0030] The cell layout incorporating finfet transistors, as
discussed above, can implemented a restricted gate level layout
architecture. For the gate level, a number of parallel virtual
lines are defined to extend across the layout. These parallel
virtual lines are referred to as gate electrode tracks, as they are
used to index placement of gate electrodes of various transistors
within the layout. In one embodiment, such as the cell layout
discussed above with regard to FIG. 2A, the parallel virtual lines
which form the gate electrode tracks are defined by a perpendicular
spacing therebetween equal to a specified gate electrode pitch.
Therefore, placement of gate electrode segments on the gate
electrode tracks corresponds to the specified gate electrode pitch.
In another embodiment the gate electrode tracks can be spaced at
variable pitches greater than or equal to a specified gate
electrode pitch.
[0031] FIG. 3A shows an example of gate electrode tracks 301A-301E
defined within the restricted gate level layout architecture, in
accordance with one embodiment of the present invention. Gate
electrode tracks 301A-301E are formed by parallel virtual lines
that extend across the gate level layout of the chip, with a
perpendicular spacing therebetween equal to a specified gate
electrode pitch 307.
[0032] Within the restricted gate level layout architecture, a gate
level feature layout channel is defined about a given gate
electrode track so as to extend between gate electrode tracks
adjacent to the given gate electrode track. For example, gate level
feature layout channels 301A-1 through 301E-1 are defined about
gate electrode tracks 301A through 301E, respectively. It should be
understood that each gate electrode track has a corresponding gate
level feature layout channel. Also, for gate electrode tracks
positioned adjacent to an edge of a prescribed layout space, e.g.,
adjacent to a cell boundary, the corresponding gate level feature
layout channel extends as if there were a virtual gate electrode
track outside the prescribed layout space, as illustrated by gate
level feature layout channels 301A-1 and 301E-1. It should be
further understood that each gate level feature layout channel is
defined to extend along an entire length of its corresponding gate
electrode track. Thus, each gate level feature layout channel is
defined to extend across the gate level layout within the portion
of the chip to which the gate level layout is associated.
[0033] Within the restricted gate level layout architecture, gate
level features associated with a given gate electrode track are
defined within the gate level feature layout channel associated
with the given gate electrode track. A contiguous gate level
feature can include both a portion which defines a gate electrode
of a transistor, i.e., of a finfet transistor as disclosed herein,
and a portion that does not define a gate electrode of a
transistor. Thus, a contiguous gate level feature can extend over
both a diffusion region, i.e., diffusion fin, and a dielectric
region of an underlying chip level.
[0034] In one embodiment, each portion of a gate level feature that
forms a gate electrode of a transistor is positioned to be
substantially centered upon a given gate electrode track.
Furthermore, in this embodiment, portions of the gate level feature
that do not form a gate electrode of a transistor can be positioned
within the gate level feature layout channel associated with the
given gate electrode track. Therefore, a given gate level feature
can be defined essentially anywhere within a given gate level
feature layout channel, so long as gate electrode portions of the
given gate level feature are centered upon the gate electrode track
corresponding to the given gate level feature layout channel, and
so long as the given gate level feature complies with design rule
spacing requirements relative to other gate level features in
adjacent gate level layout channels. Additionally, physical contact
is prohibited between gate level features defined in gate level
feature layout channels that are associated with adjacent gate
electrode tracks.
[0035] FIG. 3B shows the exemplary restricted gate level layout
architecture of FIG. 3A with a number of exemplary gate level
features 309-323 defined therein, in accordance with one embodiment
of the present invention. The gate level feature 309 is defined
within the gate level feature layout channel 301A-1 associated with
gate electrode track 301A. The gate electrode portions of gate
level feature 309 are substantially centered upon the gate
electrode track 301A. Also, the non-gate electrode portions of gate
level feature 309 maintain design rule spacing requirements with
gate level features 311 and 313 defined within adjacent gate level
feature layout channel 301B-1. Similarly, gate level features
311-323 are defined within their respective gate level feature
layout channel, and have their gate electrode portions
substantially centered upon the gate electrode track corresponding
to their respective gate level feature layout channel. Also, it
should be appreciated that each of gate level features 311-323
maintains design rule spacing requirements with gate level features
defined within adjacent gate level feature layout channels, and
avoids physical contact with any another gate level feature defined
within adjacent gate level feature layout channels.
[0036] A gate electrode corresponds to a portion of a respective
gate level feature that extends over a diffusion structure, i.e.,
over a diffusion fin, wherein the respective gate level feature is
defined in its entirety within a gate level feature layout channel.
Each gate level feature is defined within its gate level feature
layout channel without physically contacting another gate level
feature defined within an adjoining gate level feature layout
channel. As illustrated by the example gate level feature layout
channels 301A-1 through 301E-1 of FIG. 3B, each gate level feature
layout channel is associated with a given gate electrode track and
corresponds to a layout region that extends along the given gate
electrode track and perpendicularly outward in each opposing
direction from the given gate electrode track to a closest of
either an adjacent gate electrode track or a virtual gate electrode
track outside a layout boundary.
[0037] Some gate level features may have one or more contact head
portions defined at any number of locations along their length. A
contact head portion of a given gate level feature is defined as a
segment of the gate level feature having a height and a width of
sufficient size to receive a gate contact structure. In this
instance, "width" is defined across the substrate in a direction
perpendicular to the gate electrode track of the given gate level
feature, and "height" is defined across the substrate in a
direction parallel to the gate electrode track of the given gate
level feature. The gate level feature width and height may or may
not correspond to the cell width W and cell height H, depending on
the orientation of the gate level features within the cell. It
should be appreciated that a contact head of a gate level feature,
when viewed from above, can be defined by essentially any layout
shape, including a square or a rectangle. Also, depending on layout
requirements and circuit design, a given contact head portion of a
gate level feature may or may not have a gate contact defined
thereabove.
[0038] A gate level of the various embodiments disclosed herein is
defined as a restricted gate level, as discussed above. Some of the
gate level features form gate electrodes of transistor devices.
Others of the gate level features can form conductive segments
extending between two points within the gate level. Also, others of
the gate level features may be non-functional with respect to
integrated circuit operation. It should be understood that the each
of the gate level features, regardless of function, is defined to
extend across the gate level within their respective gate level
feature layout channels without physically contacting other gate
level features defined with adjacent gate level feature layout
channels.
[0039] In one embodiment, the gate level features are defined to
provide a finite number of controlled layout shape-to-shape
lithographic interactions which can be accurately predicted and
optimized for in manufacturing and design processes. In this
embodiment, the gate level features are defined to avoid layout
shape-to-shape spatial relationships which would introduce adverse
lithographic interaction within the layout that cannot be
accurately predicted and mitigated with high probability. However,
it should be understood that changes in direction of gate level
features within their gate level layout channels are acceptable
when corresponding lithographic interactions are predictable and
manageable.
[0040] It should be understood that each of the gate level
features, regardless of function, is defined such that no gate
level feature along a given gate electrode track is configured to
connect directly within the gate level to another gate level
feature defined along a different gate electrode track without
utilizing a non-gate level feature. Moreover, each connection
between gate level features that are placed within different gate
level layout channels associated with different gate electrode
tracks is made through one or more non-gate level features, which
may be defined in higher interconnect levels, i.e., through one or
more interconnect levels above the gate level, or by way of local
interconnect features at or below the gate level.
Exemplary Embodiments
[0041] In one embodiment, a cell circuit of a semiconductor device
is disclosed. The cell circuit includes a substrate and a number of
linear-shaped diffusion fins defined to extend over the substrate
in a first direction, so as to extend parallel to each other. Each
of the number of linear-shaped diffusion fins is defined to project
upward from the substrate along their extent in the first
direction. In one embodiment, each of the number of linear-shaped
diffusion fins is formed from a doped silicon-based material to
form either a p-type or an n-type transistor diffusion region.
[0042] The cell circuit also includes a number of gate level
structures defined to extend in a conformal manner over some of the
number of linear-shaped diffusion fins. Portions of each gate level
structure that extend over any of the number of linear-shaped
diffusion fins extend in a second direction that is substantially
perpendicular to the first direction. Portions of each gate level
structure that extend over any of the number of linear-shaped
diffusion fins form gate electrodes of a corresponding transistor.
In one embodiment, each of the number of gate level structures is
formed from an electrically conductive material.
[0043] In one embodiment, the number of linear-shaped diffusion
fins are positioned on diffusion tracks that correspond to virtual
lines of a diffusion fin virtual grate. The diffusion tracks extend
in the first direction over the substrate. In a particular
embodiment, the diffusion tracks are positioned based on a fixed
diffusion track pitch. The fixed diffusion track pitch corresponds
to an equal perpendicular spacing between adjacent diffusion
tracks. In one instance of this particular embodiment, a size of
the fixed diffusion track pitch is set at a single exposure
lithographic limit.
[0044] Also, in one embodiment, the first direction corresponds to
a width direction of the cell circuit. In this embodiment, the
fixed diffusion track pitch is related to a height of the cell
circuit, such that a continuity of the fixed diffusion track pitch
is maintained across boundaries of the cell circuit to form a
global set of equally spaced diffusion tracks across a group of
neighboring cell circuits. In one instance of this embodiment, the
height of the cell circuit is an integer multiple of the fixed
diffusion track pitch.
[0045] The number of linear-shaped diffusion fins are positioned on
diffusion tracks as needed for cell circuit functionality. In
various embodiments, some diffusion tracks are partially filled
with linear-shaped diffusion fins, some diffusion tracks are
completely filled with linear-shaped diffusion fins, some diffusion
tracks are vacant and do not have a linear-shaped diffusion fin
positioned thereon, or any combination thereof.
[0046] In one embodiment, the portions of the gate level structures
that extend over any of the number of linear-shaped diffusion fins
are positioned on gate electrode tracks that correspond to virtual
lines of a gate level virtual grate. The gate electrode tracks
extend in the second direction over the substrate. In one
embodiment, the gate electrode tracks are positioned based on a
fixed gate electrode track pitch. The fixed gate electrode track
pitch corresponds to an equal perpendicular spacing between
adjacent gate electrode tracks.
[0047] In one embodiment, the second direction corresponds to a
height direction of the cell circuit. The fixed gate electrode
track pitch can be related to a width of the cell circuit, such
that a continuity of the fixed gate electrode track pitch is
maintained across boundaries of the cell circuit to form a global
set of equally spaced gate electrode tracks across a group of
neighboring cell circuits. In one embodiment, the width of the cell
circuit is an integer multiple of the fixed gate electrode track
pitch.
[0048] The gate level structures are positioned on gate electrode
tracks as needed for cell circuit functionality. In various
embodiments, some gate electrode tracks are partially filled with
gate level structures, some gate electrode tracks are completely
filled with gate level structures, some gate electrode tracks are
vacant and do not have a gate level structure positioned thereon,
or any combination thereof.
[0049] Also, in another embodiment, the gate level structures are
positioned to maximally fill gate electrode tracks. In this
embodiment, breaks are defined between multiple gate level
structures along individual gate electrode tracks as needed for
cell circuit functionality. In one instance of this embodiment, the
breaks defined between multiple gate level structures along
individual gate electrode tracks are uniform in size through the
cell circuit.
[0050] The cell circuit can also include a number of local
interconnect structures defined between neighboring gate level
structures so as to extend in the second direction parallel to the
neighboring gate level structures. The number of local interconnect
structures are formed of an electrically conductive material. Also,
the number of local interconnect structures are formed at or below
a gate level of the cell circuit. Additionally, the cell circuit
can include a number of higher level interconnect structures
defined in an interconnect level above a gate level of the cell
circuit. In one embodiment, the number of higher level interconnect
structures are linear-shaped and extend in the first direction. In
another embodiment, the number of higher level interconnect
structures are unrestricted with regard to shape and are formed as
necessary for circuit functionality. The cell circuit can also
include a number of contact structures, and any other type of
structure previously discussed with regard to the examples of FIGS.
2A-2C.
[0051] In another embodiment, a semiconductor device cell layout is
disclosed. This embodiment is essentially a layout of the cell
circuit embodiment discussed above. Therefore, any features
discussed above with regard to the cell circuit embodiment can be
represented within this cell layout embodiment. The cell layout
includes a diffusion level layout and a gate level layout. The
diffusion level layout includes a number of diffusion fin layout
shapes defined to extend in only a first direction across the cell
layout, so as to extend parallel to each other. The number of
diffusion fin layout shapes correspond to diffusion fin structures
defined to project upward from a substrate along their extent in
the first direction.
[0052] In one embodiment, the diffusion fin layout shapes are
positioned on diffusion tracks that correspond to virtual lines of
a diffusion fin virtual grate. The diffusion tracks extend in the
first direction across the cell layout. In one embodiment, the
diffusion tracks are positioned based on a fixed diffusion track
pitch. The fixed diffusion track pitch corresponds to an equal
perpendicular spacing between adjacent diffusion tracks. In one
embodiment, the first direction corresponds to a width direction of
the cell layout. In this embodiment, the fixed diffusion track
pitch is related to a height of the cell layout, such that a
continuity of the fixed diffusion track pitch is maintained across
boundaries of the cell layout to form a global set of equally
spaced diffusion tracks across a group of neighboring cell layouts.
In one instance of this embodiment, the height of the cell layout
is an integer multiple of the fixed diffusion track pitch.
[0053] The gate level layout of the cell layout includes a number
of gate level layout shapes defined to extend in a second direction
across the cell layout that is substantially perpendicular to the
first direction. The gate level layout shapes correspond to gate
level structures defined to extend in a conformal manner over some
of the diffusion fin structures which correspond to the diffusion
fin layout shapes. Portions of each gate level structure that
extend over any of the diffusion fin structures form gate
electrodes of a corresponding transistor.
[0054] In one embodiment, portions of the gate level layout shapes
that extend over any of the diffusion fin layout shapes are
positioned on gate electrode tracks that correspond to virtual
lines of a gate level virtual grate. The gate electrode tracks
extend in the second direction across the cell layout, i.e.,
perpendicular to the first direction. In one embodiment, the gate
electrode tracks are positioned based on a fixed gate electrode
track pitch. The fixed gate electrode track pitch corresponds to an
equal perpendicular spacing between adjacent gate electrode tracks.
In one embodiment, the second direction corresponds to a height
direction of the cell layout. In this embodiment, the fixed gate
electrode track pitch is related to a width of the cell layout,
such that a continuity of the fixed gate electrode track pitch is
maintained across boundaries of the cell layout to form a global
set of equally spaced gate electrode tracks across a group of
neighboring cell layouts. In one instance of this embodiment, the
width of the cell layout is an integer multiple of the fixed gate
electrode track pitch. It should be understood that the cell layout
can also include a number of additional layout shapes and levels
corresponding to other circuit structures, including any other type
of circuit structure previously discussed with regard to the
examples of FIGS. 2A-2C.
[0055] It should be understood that any cell layout incorporating
finfet transistors as disclosed herein can be stored in a tangible
form, such as in a digital format on a computer readable medium.
For example, a given cell layout can be stored in a layout data
file, and can be selectable from one or more libraries of cells.
The layout data file can be formatted as a GDS II (Graphic Data
System) database file, an OASIS (Open Artwork System Interchange
Standard) database file, or any other type of data file format
suitable for storing and communicating semiconductor device
layouts. Also, multi-level layouts of a cell incorporating finfet
transistors as disclosed herein can be included within a
multi-level layout of a larger semiconductor device. The
multi-level layout of the larger semiconductor device can also be
stored in the form of a layout data file, such as those identified
above.
[0056] Also, the invention described herein can be embodied as
computer readable code on a computer readable medium. For example,
the computer readable code can include a layout data file within
which a layout of a cell incorporating finfet transistors as
disclosed herein is stored. The computer readable code can also
include program instructions for selecting one or more layout
libraries and/or cells that include finfet transistors as disclosed
herein. The layout libraries and/or cells can also be stored in a
digital format on a computer readable medium.
[0057] The computer readable medium mentioned herein is any data
storage device that can store data which can thereafter be read by
a computer system. Examples of the computer readable medium include
hard drives, network attached storage (NAS), read-only memory,
random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and
other optical and non-optical data storage devices. Multiple
computer readable media distributed within a network of coupled
computer systems can also be used to store respective portions of
the computer readable code such that the computer readable code is
stored and executed in a distributed fashion within the
network.
[0058] It should be further understood that any cell layout
incorporating finfet transistors as disclosed herein can be
manufactured as part of a semiconductor device or chip. In the
fabrication of semiconductor devices such as integrated circuits,
memory cells, and the like, a series of manufacturing operations
are performed to define features on a semiconductor wafer. The
wafer includes integrated circuit devices in the form of
multi-level structures defined on a silicon substrate. At a
substrate level, transistor devices with diffusion regions and/or
diffusion fins are formed. In subsequent levels, interconnect
metallization lines are patterned and electrically connected to the
transistor devices to define a desired integrated circuit device.
Also, patterned conductive layers are insulated from other
conductive layers by dielectric materials.
[0059] While this invention has been described in terms of several
embodiments, it will be appreciated that those skilled in the art
upon reading the preceding specifications and studying the drawings
will realize various alterations, additions, permutations and
equivalents thereof. Therefore, it is intended that the present
invention includes all such alterations, additions, permutations,
and equivalents as fall within the true spirit and scope of the
invention.
* * * * *