U.S. patent number D778,851 [Application Number D/564,507] was granted by the patent office on 2017-02-14 for substrate for an electronic circuit.
This patent grant is currently assigned to Kabushiki Kaisha Toshiba. The grantee listed for this patent is Kabushiki Kaisha Toshiba. Invention is credited to Manabu Matsumoto, Isao Ozawa.
United States Patent |
D778,851 |
Matsumoto , et al. |
February 14, 2017 |
Substrate for an electronic circuit
Claims
CLAIM The ornamental design for a substrate for an electronic
circuit, as shown and described.
Inventors: |
Matsumoto; Manabu (Yokohama,
JP), Ozawa; Isao (Chigasaki, JP) |
Applicant: |
Name |
City |
State |
Country |
Type |
Kabushiki Kaisha Toshiba |
Minato-ku, Tokyo |
N/A |
JP |
|
|
Assignee: |
Kabushiki Kaisha Toshiba
(Minato-ku, Tokyo, JP)
|
Appl.
No.: |
D/564,507 |
Filed: |
May 13, 2016 |
Related U.S. Patent Documents
|
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
|
29500896 |
Aug 29, 2014 |
D764424 |
|
|
|
Foreign Application Priority Data
|
|
|
|
|
May 15, 2014 [JP] |
|
|
2014-010418 |
May 15, 2014 [JP] |
|
|
2014-010419 |
May 15, 2014 [JP] |
|
|
2014-010420 |
May 15, 2014 [JP] |
|
|
2014-010421 |
|
Current U.S.
Class: |
D13/182 |
Current International
Class: |
1303 |
Field of
Search: |
;D13/182,123,133,110,184,199 ;257/177,666,684,689,775
;361/600,601,820 ;29/825,829,830,831,832
;174/68.1,250,253,254,260,261,268 ;216/13 ;428/901 ;D5/4,61 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
|
|
|
|
|
|
|
488834 |
|
May 2002 |
|
CN |
|
1104233 |
|
Mar 2001 |
|
JP |
|
1287854 |
|
Dec 2006 |
|
JP |
|
1426168 |
|
Oct 2011 |
|
JP |
|
1479369 |
|
Sep 2013 |
|
JP |
|
1479370 |
|
Sep 2013 |
|
JP |
|
30-0470075 |
|
Nov 2007 |
|
KR |
|
Primary Examiner: Oswecki; Elizabeth J
Attorney, Agent or Firm: Banner & Witcoff, Ltd.
Description
FIG. 1 is a perspective view of a substrate for an electronic
circuit showing our new design;
FIG. 2 is a rear perspective view thereof;
FIG. 3 is a front elevational view thereof;
FIG. 4 is a rear elevational view thereof;
FIG. 5 is a right side elevational view, a left side elevational
view being a mirror image thereof;
FIG. 6 is a top plan view thereof; and,
FIG. 7 is a bottom plan view thereof.
The broken lines shown in the drawings represent portions of the
substrate for an electronic circuit that form no part of the
claimed design.
* * * * *