U.S. patent application number 17/750417 was filed with the patent office on 2022-09-08 for method of forming semiconductor packages having thermal through vias (ttv).
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Company, Ltd.. The applicant listed for this patent is Taiwan Semiconductor Manufacturing Company, Ltd.. Invention is credited to Yi-Che Chiang, Sen-Kuei Hsu, Hsin-Yu Pan, Kai-Chiang Wu, Ching-Feng Yang.
Application Number | 20220285241 17/750417 |
Document ID | / |
Family ID | 1000006348340 |
Filed Date | 2022-09-08 |
United States Patent
Application |
20220285241 |
Kind Code |
A1 |
Hsu; Sen-Kuei ; et
al. |
September 8, 2022 |
METHOD OF FORMING SEMICONDUCTOR PACKAGES HAVING THERMAL THROUGH
VIAS (TTV)
Abstract
A method of forming a semiconductor package includes the
following steps. A redistribution layer structure is formed over a
first die and a dummy die, wherein the redistribution layer
structure is directly electrically connected to the first die. An
insulating layer is formed, wherein the insulating layer is
disposed opposite to the redistribution layer structure with
respect to the first die. At least one thermal through via is
formed in the insulating layer.
Inventors: |
Hsu; Sen-Kuei; (Kaohsiung
City, TW) ; Yang; Ching-Feng; (Taipei City, TW)
; Pan; Hsin-Yu; (Taipei, TW) ; Wu; Kai-Chiang;
(Hsinchu City, TW) ; Chiang; Yi-Che; (Hsinchu,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Hsinchu |
|
TW |
|
|
Assignee: |
Taiwan Semiconductor Manufacturing
Company, Ltd.
Hsinchu
TW
|
Family ID: |
1000006348340 |
Appl. No.: |
17/750417 |
Filed: |
May 23, 2022 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
16993285 |
Aug 14, 2020 |
11373922 |
|
|
17750417 |
|
|
|
|
15992196 |
May 30, 2018 |
10748831 |
|
|
16993285 |
|
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 24/23 20130101;
H01L 2224/18 20130101; H01L 2224/20 20130101; H01L 23/562 20130101;
H01L 2224/2101 20130101; H01L 2224/22 20130101; H01L 2224/02379
20130101; H01L 21/76816 20130101; H01L 2224/25171 20130101; H01L
24/17 20130101; H01L 2924/15172 20130101; H01L 23/5226 20130101;
H01L 2224/221 20130101; H01L 23/367 20130101; H01L 2224/211
20130101; H01L 2224/2201 20130101; H01L 2924/15173 20130101; H01L
2224/21 20130101; H01L 24/32 20130101; H01L 24/20 20130101; H01L
23/5384 20130101; H01L 24/24 20130101; H01L 24/25 20130101; H01L
24/18 20130101 |
International
Class: |
H01L 23/367 20060101
H01L023/367; H01L 23/00 20060101 H01L023/00; H01L 21/768 20060101
H01L021/768; H01L 23/522 20060101 H01L023/522; H01L 23/538 20060101
H01L023/538 |
Claims
1. A method of forming a semiconductor package, comprising: forming
a redistribution layer structure over a first die and a dummy die,
wherein the redistribution layer structure is directly electrically
connected to the first die; forming an insulating layer, wherein
the insulating layer is disposed opposite to the redistribution
layer structure with respect to the first die; and forming at least
one thermal through via in the insulating layer.
2. The method as claimed in claim 1, wherein the dummy die is
electrically connected to the first die through the redistribution
layer structure.
3. The method as claimed in claim 1, further comprising forming at
least one through via aside the first die between the
redistribution layer structure and the at least one thermal through
via.
4. The method as claimed in claim 1, further comprising forming
connectors over the redistribution layer structure.
5. The method as claimed in claim 4, wherein the first die is
disposed in a first region, the dummy die is disposed in a second
region, a density of the connectors in the first region is equal to
the number of the connectors in the first region divided by an area
of the first region, a density of the connectors in the second
region is equal to the number of the connectors in the second
region divided by an area of the second region, and the density of
the connectors in the second region is larger than the density of
the connectors in the first region.
6. The method as claimed in claim 1, further comprising forming
other redistribution layer structure between the insulating layer
and the first die and the dummy die, wherein the at least one
thermal through via is electrically connected to the redistribution
layer structure through the other redistribution layer
structure.
7. The method as claimed in claim 1, wherein the first die is
disposed in a first region, the dummy die is disposed in a second
region, a density of the at least one thermal through via in the
first region is equal to the number of the at least one thermal
through via in the first region divided by an area of the first
region, a density of the at least one thermal through via in the
second region is equal to the number of the at least one thermal
through via in the second region divided by an area of the second
region, and the density of the at least one thermal through via in
the first region is larger than the density of the at least one
thermal through via in the second region.
8. A method of forming a semiconductor package, comprising: forming
a first die over a conductive paste; and forming at least one
thermal through via over a first die, wherein the conductive paste
is disposed between the first die and the at least one thermal
through via, and the at least one thermal through via is
electrically connected to the first die through the conductive
paste.
9. The method as claimed in claim 8, wherein the conductive paste
is in direct contact with the first die.
10. The method as claimed in claim 8, further comprising forming a
dummy die aside the first die.
11. The method as claimed in claim 10, wherein the conductive paste
is further in direct contact with the dummy die.
12. The method as claimed in claim 8, further comprising forming a
redistribution layer structure electrically connected to the first
die, wherein the redistribution layer structure and the at least
one thermal through via are disposed at opposite sides of the first
die.
13. The method as claimed in claim 12, wherein further comprising
forming a plurality of connectors, wherein the redistribution layer
structure is disposed between the connectors and the first die.
14. The method as claimed in claim 8, further comprising forming an
insulating layer surrounding the at least one thermal through
via.
15. A method of forming a semiconductor package, comprising:
forming at least one first through via in an encapsulant; forming a
redistribution layer structure over the at least one first through
via; and forming at least one thermal through via over the
redistribution layer structure and the encapsulant, wherein the
redistribution layer structure is electrically connected to the at
least one first through via and the at least one thermal through
via.
16. The method as claimed in claim 15, further comprising forming a
die aside the at least one first through via in the encapsulant,
wherein the at least one thermal through via is electrically
connected to the die through the at least one first through
via.
17. The method as claimed in claim 16, further comprising forming a
die attach film between the die and the at least one thermal
through via.
18. The method as claimed in claim 16, further comprising forming a
conductive paste between the die and the redistribution layer
structure.
19. The method as claimed in claim 18, wherein the conductive paste
is in direct contact with the die and the redistribution layer
structure.
20. The method as claimed in claim 15, wherein surfaces of the at
least one first through via and the encapsulant are substantially
coplanar.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation application of and claims
the priority benefit of a prior application Ser. No. 16/993,285,
filed on Aug. 14, 2020 and now allowed, which claims the priority
benefit of a prior application Ser. No. 15/992,196, filed on May
30, 2018 and now allowed. The entirety of the above-mentioned
patent applications is hereby incorporated by reference herein and
made a part of this specification.
BACKGROUND
[0002] In the packaging of integrated circuits, semiconductor dies
may be packaged by a molding compound, and may be bonded to other
package components such as interposers and package substrates. Heat
dissipation is a challenge in the semiconductor packages. There
exists a bottleneck in efficiently dissipating the heat generated
in the inner dies of the semiconductor packages.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
[0004] FIG. 1A to FIG. 1F are cross-sectional views of a method of
forming a semiconductor package in accordance with some
embodiments.
[0005] FIG. 2 is a schematic top view illustrating a semiconductor
package in accordance with some embodiments.
[0006] FIG. 3A to FIG. 3F are cross-sectional views of a method of
forming a semiconductor package in accordance with some
embodiments.
[0007] FIG. 4 is a schematic cross sectional view illustrating a
semiconductor package in accordance with some embodiments.
[0008] FIG. 5 is a schematic cross sectional view illustrating a
semiconductor package in accordance with some embodiments.
DETAILED DESCRIPTION
[0009] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the provided subject matter. Specific examples of components and
arrangements are described below to simplify the present
disclosure. These are, of course, merely examples and are not
intended to be limiting. For example, the formation of a first
feature over or on a second feature in the description that follows
may include embodiments in which the first and second features are
formed in direct contact, and may also include embodiments in which
additional features may be formed between the first and second
features, such that the first and second features may not be in
direct contact. In addition, the present disclosure may repeat
reference numerals and/or letters in the various examples. This
repetition is for the purpose of simplicity and clarity and does
not in itself dictate a relationship between the various
embodiments and/or configurations discussed.
[0010] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
[0011] In addition, terms, such as "first," "second," "third,"
"fourth," and the like, may be used herein for ease of description
to describe similar or different element(s) or feature(s) as
illustrated in the figures, and may be used interchangeably
depending on the order of the presence or the contexts of the
description.
[0012] Other features and processes may also be included. For
example, testing structures may be included to aid in the
verification testing of the 3D packaging or 3DIC devices. The
testing structures may include, for example, test pads formed in a
redistribution layer or on a substrate that allows the testing of
the 3D packaging or 3DIC, the use of probes and/or probe cards, and
the like. The verification testing may be performed on intermediate
structures as well as the final structure. Additionally, the
structures and methods disclosed herein may be used in conjunction
with testing methodologies that incorporate intermediate
verification of known good dies to increase the yield and decrease
costs.
[0013] FIG. 1A to FIG. 1F are cross-sectional views of a method of
forming a semiconductor package in accordance with some
embodiments. FIG. 1F is a simplified top view taken along the line
I-I of FIG. 2. For simplicity and clarity of illustration, only few
elements such as first die, second die and dummy die are shown in
the simplified top view of FIG. 2. In some embodiments, the
semiconductor package is an integrated fan-out package, for
example.
[0014] Referring to FIG. 1A, a carrier C is provided with a
de-bonding layer DB and a dielectric layer DI formed thereon, and
the de-bonding layer DB is between the carrier C and the dielectric
layer DI. In some embodiments, the carrier C is a glass substrate,
the de-bonding layer DB is a light-to-heat conversion (LTHC)
release layer, and the dielectric layer DI is a polymer layer such
as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a
combination thereof or the like.
[0015] Thereafter, a first redistribution layer structure RDL1 is
formed on the dielectric layer DI. The first redistribution layer
structure RDL1 is referred to as a "backside redistribution layer
structure" through the specification. Specifically, the first
redistribution layer structure RDL1 includes redistribution layers
102 and dielectric layers 104 stacked alternately. In some
embodiments, the redistribution layer 102 includes copper, nickel,
titanium, a combination thereof, or the like. In some embodiments,
the dielectric layer 104 includes a photo-sensitive material such
as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a
combination thereof or the like. In alternative embodiments, more
redistribution layers and dielectric layers can be included in the
first redistribution layer structure RDL1, and the dielectric
layers and the redistribution layers are stacked alternately. The
number of the dielectric layers or redistribution layers is not
limited by the present disclosure.
[0016] A plurality of through integrated fan-out vias TIV1 and TIV2
are formed on the first redistribution layer structure RDL1. In
some embodiments, the through integrated fan-out vias TIV1
penetrate through the dielectric layer 104 and are electrically
connected to the redistribution layer 102, and the through
integrated fan-out vias TIV2 are formed on the dielectric layer
104. In some embodiments, the through integrated fan-out vias TIV2
are arranged to form a plurality of dipole antennas DA.
Specifically, the dipole antennas DA are formed during the
formation of the through integrated fan-out vias.
[0017] In some embodiments, the method of forming the through
integrated fan-out vias TIV1 and TIV2 includes the following
operations. A seed material layer (not shown) is formed over the
first redistribution layer structure RDL1. In some embodiments, the
seed material layer includes a titanium/copper composite layer, and
is formed by a sputtering process. Thereafter, a photoresist layer
(not shown) with openings is formed on the seed material layer, and
the openings of the photoresist layer expose the intended locations
for the subsequently formed through integrated fan-out vias.
Afterwards, a plating process is performed to form a metal material
layer (e.g., a copper layer) on the seed material layer exposed by
the openings of the photoresist layer. The photoresist layer and
the underlying seed material layer are then removed to form the
through integrated fan-out vias TIV1 and TIV2.
[0018] In some embodiments, the through integrated fan-out vias
TIV2 or dipole antennas DA have a dimension (e.g., width) greater
than that of the through integrated fan-out vias TIV1. However, the
present disclosure is not limited thereto. In alternative
embodiments, the through integrated fan-out vias TIV2 or dipole
antennas DA have a dimension (e.g., width) substantially equal to
or less than that of the through integrated fan-out vias TIV1. In
some embodiments, the frequency band of the dipole antenna DA is 60
GHz, for example.
[0019] Referring to FIG. 1B, after the through integrated fan-out
vias TIV1 and TIV2 are formed, a first die 110, a second die 130
and a dummy die 140 and are picked and placed on the carrier C. In
some embodiments, the first die 110, the second die 130 and the
dummy die 140 are attached to the dielectric layer DI with a die
attach film DAF therebetween. In some embodiments, the first die
110 is formed in a first region R1, the dummy die 140 is formed in
a second region R2, and the second die 130 is formed in a third
region R3, for example. The first die 110 is a high-power consuming
die or die stack, and the second die 130 is a low-power consuming
die or stack. The first die 110 is a high-power consuming die and
may consume a relatively high amount of power, and hence generate a
relatively large amount of heat, compared to the second die 130
which is a low-power consuming die. In some embodiments, the first
die 110 is a power chip, and the second die 130 is a radio
frequency (RF) die, for example. In some embodiments, the first die
110 and the second die 130 include a substrate 112, a device layer
114 in or on the substrate 112, a conductive structure 116, die
connectors 118 and a die insulating layer 120. The substrate 112
may be a semiconductor substrate, such as a silicon substrate,
although it may be formed of other semiconductor materials
including, and not limited to, silicon germanium, silicon carbon,
gallium arsenide, or the like. The device layer 114 may be formed
in or on the substrate 112. In some embodiments, the device layer
114 include transistors, resistors, capacitors, inductors, and/or
the like. The conductive structure 116 may be formed on and
electrically connected to the device layer 114 and may be an
interconnect structure. The conductive structure 116 may include a
plurality of dielectric layers (not shown), which may include an
Inter-Layer Dielectric (ILD) and Inter-Metal Dielectrics (IMDs),
and conductive layers and vias disposed in the dielectric layers.
The die connectors 118 are formed over and electrically connected
to underlying pads of conductive structure 116. The die connectors
118 include solder bumps, gold bumps, copper pillars or the like,
and are formed with a ball drop process or an electroplating
process. The die insulating layer 120 is formed over the substrate
112 and exposes portions of the die connectors 118. In some
embodiments, the die insulating layer 120 is a polymer layer. For
example, the die insulating layer 120 includes a photo-sensitive
material such as polybenzoxazole (PBO), polyimide, benzocyclobutene
(BCB), a combination thereof, or the like.
[0020] In some embodiments, the dummy die 140 is used to increase
the thermal capacitance and decrease the junction temperature, in
other words, the dummy die 140 does not provide substantial
function and thus may be a device-free die. In some embodiments,
the dummy die 140 does not have a device layer including
transistors, resistors, capacitors, inductors, and/or the like. In
some embodiments, the dummy die 140 includes a substrate 142, a
conductive structure 144, dummy die connectors 146 and a dummy die
insulating layer 148. The conductive structure 144 may be formed on
and electrically connected to vias of the substrate 142 and may be
an interconnect structure. The conductive structure 144 may include
a plurality of dielectric layers (not shown), which may include an
Inter-Layer Dielectric (ILD) and Inter-Metal Dielectrics (IMDs),
and conductive layers and vias disposed in the dielectric layers.
The substrate 142, the dummy die connectors 146 and the dummy die
insulating layer 148 are similar to the substrate 112, the die
connectors 118 and the die insulating layer 120, and thus their
description is omitted herein. In some embodiments, a size of the
dummy die 140 may be adjusted according to a power of the first die
110. In other words, the thermal capacitance may be increased by
enlarge a size of the dummy die 140.
[0021] Conventionally, since sizes of the first die 110 and the
second die 130 are different, the first die 110 and the second die
130 are arranged together to form a non-rotationally symmetrical
shape, which may cause a warpage issue. In some embodiments, by
providing the dummy die 140 with a designed shape and size, the
dummy die 140 may be formed a rotationally symmetrical shape with
the first die 110 and the second die 130. Thus, the warpage is
prevented. It is note that the term "the rotationally symmetrical
shape" means a shape substantially having rotational symmetry and a
shape substantially composed of a shape of the bottom of the first
die 110, a shape of the bottom of the second die 130, a shape of
the bottom of the dummy die 140 and a shape of a gap therebetween.
In some embodiments, the rotationally symmetrical shape is a
rectangle or a regular polygon, for example. The sizes of the first
die, the second die and the dummy die are not limited by the
present disclosure.
[0022] Thereafter, a molding layer 150 is formed over the carrier C
to encapsulate or surround the sidewalls of the through integrated
fan-out vias TIV1 and TIV2 and the sidewalls of the first die 110,
the second die 130 and the dummy die 140. In some embodiments, a
mold with a mold cavity (not shown) is pressed against the first
die 110, the second die 130 and the dummy die 140, and the molding
cavity is then filled with a molding material to form the molding
layer 150. In some embodiments, the molding layer 150 includes a
molding compound, a molding underfill, a resin or the like, such as
epoxy. In some embodiments, the molding layer 150 includes a
photo-sensitive material such as polybenzoxazole (PBO), polyimide,
benzocyclobutene (BCB), a combination thereof, or the like.
[0023] Referring to FIG. 1C, a second redistribution layer RDL2 is
formed over the molding layer 150. The second redistribution layer
structure RDL2 is referred to as a "front-side redistribution layer
structure" through the specification. In some embodiments, the
second redistribution layer structure RDL2 is electrically
connected to the die connectors 118 of the first die 110 and the
second die 130, the dummy die connectors 146 of the dummy die 140
and the through integrated fan-out vias TIV1 and TIV2. In some
embodiments, the second redistribution layer structure RDL2
includes a plurality of redistribution layers 172 and a plurality
of dielectric layers 174 stacked alternately. The number of the
dielectric layers or redistribution layers is not limited by the
disclosure. In some embodiments, the topmost redistribution layer
is also called an under-ball metallurgy (UBM) layer for ball mount.
In some embodiments, each of the dielectric layers includes a
photo-sensitive material such as polybenzoxazole (PBO), polyimide,
benzocyclobutene (BCB), a combination thereof, or the like. In some
embodiments, each of the redistribution layers includes copper,
nickel, titanium, a combination thereof, or the like, and is formed
by an electroplating process. In some embodiments, the dummy die
140 is electrically connected to the first die 110 through the
second redistribution layer structure RDL2, for example. In
alternative embodiments, the dummy die 140 may be not electrically
connected to the first die 110. In alternative embodiments, the
dummy die 140 may be electrically floated.
[0024] Thereafter, connectors 152 such as balls or bumps are formed
over and electrically connected to the second redistribution layer
structure RDL2. In some embodiments, the connectors 152 are made of
a conductive material with low resistivity, such as Sn, Pb, Ag, Cu,
Ni, Bi or an alloy thereof, and are formed by a suitable process
such as evaporation, plating, ball drop, or screen printing.
[0025] Referring to FIG. 1D, the carrier C is de-bonded. In some
embodiments, the carrier C with the first die 110, the second die
130, the dummy die 140, the molding layer 150, the first and second
redistribution layer structures RDL1 and RDL2 is turned over, the
de-bonding layer DB is decomposed under heat of light, and the
carrier C is then released from the backsides or first sides of the
first die 110, the second die 130 and the dummy die 140.
[0026] Referring to FIG. 1E, an insulating layer 154 is formed over
the backsides or first sides of the first die 110, the second die
130 and the dummy die 140. Specifically, the insulating layer 154
is formed on the dielectric layer DI. The first redistribution
layer structure RDL1 and the thermal through vias TTV are disposed
at opposite sides of the first die 110. In some embodiments, the
insulating layer 154 is a polymer layer. For example, the
insulating layer 154 includes a photo-sensitive material such as
polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), a
combination thereof, or the like. The insulating layer 154 is
formed by a suitable fabrication technique such as spin-coating,
lamination, deposition or the like. A thickness of the insulating
layer 154 ranges from 110 .mu.m to 400 .mu.m, for example.
[0027] Then, a plurality of openings 156 are formed in the
insulating layer 154. In some embodiments, the openings 156 are
formed by a suitable fabrication technique such as laser drilling
process, an etching process or the like.
[0028] Referring to FIG. 1F, a plurality of thermal through vias
TTV are formed in the openings 156 of the insulating layer 154. In
some embodiments, the thermal through vias TTV penetrate through
the insulating layer 154 and are electrically connected to the
first die 110 through the first redistribution layer structure
RDL1, the through integrated fan-out vias TIV1 and the second
redistribution layer structure RDL2, for example. In alternative
embodiments, the thermal through vias TTV may be not electrically
connected to the first die 110. In alternative embodiments, the
thermal through vias TTV may be electrically floated. In some
embodiments, the thermal through vias TTV are respectively formed
above the first die 110 in the first region R1, the second die 130
in the third region R3 and the dummy die 140 in the second region
R2, for example. Specifically, the thermal through vias TTV may be
arranged in a row, a column or an array respectively in the first,
second and third regions Ra, R2 and R3, for example. In some
embodiments, the density of the thermal through vias TTV in the
first region R1 is larger than the density of the thermal through
vias TTV in other regions such as the second region R2 or the third
region R3. In the case that the thermal through vias TTV have
substantially the same size, the density of the thermal through
vias TTV in the first region R1 is defined as the number of the
thermal through vias TTV in the first region R1 divided by an area
of the first region R1, the density of the thermal through vias TTV
in the second region R2 is equal to the number of the thermal
through vias TTV in the second region R2 divided by an area of the
second region R2, and the density of the thermal through vias TTV
in the third region R3 is equal to the number of the thermal
through vias TTV in the third region R3 divided by an area of the
third region R3. In some embodiments, the area of the first region
R1 may be an area of a top surface of the first die 110, the area
of the second region R2 may be an area of a top surface of the
dummy die 140, and the area of the third region R2 may be an area
of a top surface of the second die 130.
[0029] In alternative embodiments, the thermal through vias TTV may
be mainly formed directly above the first die 110 in the first
region R1, for example. In alternative embodiments, the thermal
through vias TTV may be only formed in the first region R1, and not
formed in other regions such as the second region R2, the third
region R3 or the region above the through integrated fan-out vias
TIV1 and TIV2, for example. However, the present disclosure is not
limited thereto. In alternative embodiments, the thermal through
vias TTV may be formed at other positions above the first die 110.
In some embodiments, the thermal through vias TTV includes copper,
nickel, titanium, a combination thereof, or the like. The thermal
through vias TTV are formed by a suitable process such as
evaporation, plating, or screen printing. The number, shapes,
sizes, variations, configurations and distributions of the thermal
through vias are not limited by the present disclosure. Rather,
those parameters can be adjusted upon the design requirements.
[0030] In some embodiments, a plurality of patch antennas PA are
disposed over the insulating layer 154 to electrically connect to
thermal through vias TTV. Specifically, the patch antennas PA are
at the backsides or first sides of the first die 110, the second
die 130 and the dummy die 140. In some embodiments, the thermal
through vias TTV and the patch antennas PA are formed integrally,
for example. The patch antennas PA may be square, rectangular,
polygonal, round, elliptical or any suitable shape.
[0031] In some embodiments, the dummy die and the thermal through
vias are formed aside and above the first die, and thus the thermal
capacitances are increased and the junction temperature is
decreased. In other words, the dummy die and the thermal through
vias provide another way for heat dissipation, the temperature of
the first die may be significantly decreased. In addition, the
dummy die may control the warpage to increase the process
capability. Accordingly, the performance and the lifetime of the
semiconductor package may be increased.
[0032] Possible modifications and alterations can be made to the
semiconductor package. These modifications and alterations are
provided for illustration purposes, and are not construed as
limiting the present disclosure. FIG. 3A to FIG. 3F are
cross-sectional views of a method of forming a semiconductor
package in accordance with some embodiments.
[0033] The method of FIG. 3A to FIG. 3F is similar to the method of
FIG. 1A to FIG. 1F, and the difference between them is described
below. Referring to FIG. 3A, a carrier C is provided with a
de-bonding layer DB and a dielectric layer DI formed thereon, and
the de-bonding layer DB is between the carrier C and the dielectric
layer DI. Thereafter, a first redistribution layer structure RDL1
is formed on the dielectric layer DI. In some embodiments, a
redistribution layer 102 of the first redistribution layer
structure RDL1 in a first region R1 is exposed. A plurality of
through integrated fan-out vias TIV1 and TIV2 are formed on the
first redistribution layer structure RDL1. In some embodiments, the
through integrated fan-out vias TIV2 are arranged to form a
plurality of dipole antennas DA.
[0034] Then, a conductive paste 160 is formed on the redistribution
layer 102 in the first region R1. In some embodiments, the
conductive paste 160 is in direct contact with the redistribution
layer 102 and partially embedded in a dielectric layer 104 aside
the redistribution layer 102. The conductive paste 160 is a silver
paste, for example.
[0035] Referring to FIG. 3B, a first die 110, a second die 130 and
a dummy die 140 and are picked and placed on the carrier C. In some
embodiments, the first die 110 is directly placed on the conductive
paste 160 in the first region R1, while the second die 130 and the
dummy die 140 are attached to the dielectric layer DI with a die
attach film DAF therebetween.
[0036] Thereafter, a molding layer 150 is formed over the carrier C
to encapsulate or surround the sidewalls of the through integrated
fan-out vias TIV1 and TIV2, the sidewalls of the conductive paste
160 and the sidewalls of the first die 110, the second die 130 and
the dummy die 140.
[0037] Referring to FIG. 3C, a second redistribution layer RDL2 is
formed over the molding layer 150. Thereafter, connectors 152 such
as balls or bumps are formed over and electrically connected to the
second redistribution layer structure RDL2.
[0038] Referring to FIG. 3D, the carrier C is de-bonded. In some
embodiments, the carrier C with the first die 110, the second die
130, the dummy die 140, the molding layer 150, the first and second
redistribution layer structures RDL1 and RDL2 is turned over, the
de-bonding layer DB is decomposed under heat of light, and the
carrier C is then released from the backsides or first sides of the
first die 110, the second die 130 and the dummy die 140.
[0039] Referring to FIG. 3E, an insulating layer 154 is formed over
the backsides or first sides of the first die 110, the second die
130 and the dummy die 140. Then, a plurality of openings 156 are
formed in the insulating layer 154.
[0040] Referring to FIG. 3F, a plurality of thermal through vias
TTV are formed in the openings 156 of the insulating layer 154. In
some embodiments, the thermal through vias TTV in the first region
R1 are electrically connected to the first die 110 through the
first redistribution layer structure RDL1 and the conductive paste
160.
[0041] In some embodiments, in addition to formation of the thermal
through vias and the dummy die, the thermal through vias are
designed to electrically connect to the first die through the
conductive paste. Accordingly, the heat may be dissipated more
efficiently, and the temperature of the first die may be
significantly decreased.
[0042] In some embodiments, the conductive paste 160 is only formed
on the backside of the first die 110. However, the present
disclosure is not limited thereto. In alternative embodiments, as
shown in FIG. 4, the conductive paste 160 may be continuously
formed on the backsides of the first die 110 and the dummy die 140.
In this case, the first die 110 and the dummy die 140 are
electrically connected to each other through the conductive paste
160. Accordingly, the heat may be dissipated more efficiently, and
the temperature of the first die may be significantly
decreased.
[0043] FIG. 5 is a schematic cross sectional view illustrating a
semiconductor package in accordance with some embodiments. In FIG.
5, a semiconductor package similar to the structure as shown in
FIG. 1F is described, except that the density of connectors is
different in different regions. Referring to FIG. 5, in some
embodiments, the density of connectors 152 above a dummy die 140 is
larger than the density of the connectors 152 above other elements
such as a first die 110 or a second die 130. In other words,
compared with substantially the same density of the connectors 152
in all regions in FIG. 1F, the density of the connectors 152 in a
second region R2 is larger than the density of the connectors 152
in other regions such as the second region R2 or the third region
R3. In the case that the connectors 152 have substantially the same
size, the density of the connectors 152 in the first region R1 is
defined as the number of the connectors 152 in the first region R1
divided by an area of the first region R1, the density of the
connectors 152 in the second region R2 is equal to the number of
the connectors 152 in the second region R2 divided by an area of
the second region R2, and the density of the connectors 152 in the
third region R3 is equal to the number of the connectors 152 in the
third region R3 divided by an area of the third region R3. In some
embodiments, the area of the first region R1 may be an area of a
top surface of the first die 110, the area of the second region R2
may be an area of a top surface of the dummy die 140, and the area
of the third region R2 may be an area of a top surface of the
second die 130. In some embodiments, the connectors 152 in the
second region R2 are electrically connected to the dummy die 140.
In some embodiments, the dummy die 140 may be electrically
connected to the first die 110. In some embodiments, in addition to
formation of the thermal through vias and the dummy die, the
connectors disposed above the dummy die are designed to increase
the thermal capacitance. Accordingly, the heat may be dissipated
more efficiently, and the temperature of the first die may be
significantly decreased.
[0044] According to some embodiments, a semiconductor package
includes a first die, a dummy die, a first redistribution layer
structure, an insulating layer and an insulating layer. The dummy
die is disposed aside the first die. The first redistribution layer
structure is electrically connected to the first die and having
connectors thereover. The insulating layer is disposed over the
first die and the dummy die and opposite to the first
redistribution layer structure. The insulating layer penetrates
through the insulating layer.
[0045] According to some embodiments, a semiconductor package
includes a first die, an insulating layer, thermal through vias and
a conductive paste. The insulating layer is disposed over the first
die. The thermal through vias penetrate through the insulating
layer over the first die. The conductive paste is in direct contact
with the first die and between the first die and a corresponding
one of the thermal through vias. The corresponding one of the
thermal through vias is electrically connected to the first die
through the conductive paste.
[0046] According to some embodiments, a method of forming a
semiconductor package includes the following steps. A first die and
a dummy die are provided. A first redistribution layer structure is
formed over the first die to electrically connect the first die.
The connectors are formed over the first redistribution layer
structure. An insulating layer is formed over the first die and the
dummy die, wherein the insulating layer is disposed opposite to the
redistribution layer structure. Thermal through vias are formed to
penetrates through the insulating layer.
[0047] According to some embodiments, a semiconductor package
includes a die, a dummy die, a plurality of conductive terminals,
an insulating layer and a plurality of thermal through vias. The
dummy die is disposed aside the die. The conductive terminals are
disposed at a first side of the dummy die and the die and
electrically connected to the dummy die and the die. The insulating
layer is disposed at a second side opposite to the first side of
the dummy die and the die. The thermal through vias penetrating
through the insulating layer.
[0048] According to some embodiments, a semiconductor package
includes a die, at least one thermal through via and a conductive
paste. The thermal through via is disposed over the die. The
conductive paste is disposed between the die and the at least one
thermal through via. The at least one thermal through via is
electrically connected to the die through the conductive paste.
[0049] According to some embodiments, a semiconductor package
includes a die, at least one first through via and at least one
thermal through via. The die and the first through via are
encapsulated by an encapsulant, and the at least through via is
electrically connected to the die. The thermal through via is
disposed in an insulating layer over the encapsulant. The at least
one thermal through via is electrically connected to the die
through the at least one first through via.
[0050] According to some embodiments, a method of forming a
semiconductor package includes the following steps. A
redistribution layer structure is formed over a first die and a
dummy die, wherein the redistribution layer structure is directly
electrically connected to the first die. An insulating layer is
formed, wherein the insulating layer is disposed opposite to the
redistribution layer structure with respect to the first die. At
least one thermal through via is formed in the insulating
layer.
[0051] According to some embodiments, a method of forming a
semiconductor package includes the following steps. A first die is
formed over a conductive paste. At least one thermal through via is
formed over a first die, wherein the conductive paste is disposed
between the first die and the at least one thermal through via, and
the at least one thermal through via is electrically connected to
the first die through the conductive paste.
[0052] According to some embodiments, a method of forming a
semiconductor package includes the following steps. At least one
first through via is formed in an encapsulant. A redistribution
layer structure is formed over the at least one first through via.
At least one thermal through via is formed over the redistribution
layer structure and the encapsulant, wherein the redistribution
layer structure is electrically connected to the at least one first
through via and the at least one thermal through via.
[0053] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *