U.S. patent application number 17/541199 was filed with the patent office on 2022-03-24 for source/drain diffusion barrier for germanium nmos transistors.
The applicant listed for this patent is Intel Corporation. Invention is credited to Cory C. BOMBERGER, Siddharth CHOUKSEY, Benjamin CHU-KUNG, Tahir GHANI, Glenn A. GLASS, Karthik JAMBUNATHAN, Jack T. KAVALIEROS, Anand S. MURTHY, Seung Hoon SUNG.
Application Number | 20220093797 17/541199 |
Document ID | / |
Family ID | |
Filed Date | 2022-03-24 |
United States Patent
Application |
20220093797 |
Kind Code |
A1 |
GLASS; Glenn A. ; et
al. |
March 24, 2022 |
SOURCE/DRAIN DIFFUSION BARRIER FOR GERMANIUM NMOS TRANSISTORS
Abstract
Integrated circuit transistor structures are disclosed that
reduce n-type dopant diffusion, such as phosphorous or arsenic,
from the source region and the drain region of a germanium n-MOS
device into adjacent shallow trench isolation (STI) regions during
fabrication. The n-MOS transistor device may include at least 75%
germanium by atomic percentage. In an example embodiment, the
structure includes an intervening diffusion barrier deposited
between the n-MOS transistor and the STI region to provide dopant
diffusion reduction. In some embodiments, the diffusion barrier may
include silicon dioxide with carbon concentrations between 5 and
50% by atomic percentage. In some embodiments, the diffusion
barrier may be deposited using chemical vapor deposition (CVD),
atomic layer deposition (ALD), or physical vapor deposition (PVD)
techniques to achieve a diffusion barrier thickness in the range of
1 to 5 nanometers.
Inventors: |
GLASS; Glenn A.; (Portland,
OR) ; MURTHY; Anand S.; (Portland, OR) ;
JAMBUNATHAN; Karthik; (Hillsboro, OR) ; BOMBERGER;
Cory C.; (Portland, OR) ; GHANI; Tahir;
(Portland, OR) ; KAVALIEROS; Jack T.; (Portland,
OR) ; CHU-KUNG; Benjamin; (Boise, ID) ; SUNG;
Seung Hoon; (Portland, OR) ; CHOUKSEY; Siddharth;
(Portland, OR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Intel Corporation |
Santa Clara |
CA |
US |
|
|
Appl. No.: |
17/541199 |
Filed: |
December 2, 2021 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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16641022 |
Feb 21, 2020 |
11222977 |
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PCT/US2017/053474 |
Sep 26, 2017 |
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17541199 |
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International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 29/167 20060101 H01L029/167; H01L 29/417 20060101
H01L029/417; H01L 29/423 20060101 H01L029/423 |
Claims
1. An integrated circuit (IC) comprising: a body of semiconductor
material, the semiconductor material comprising germanium; a gate
structure on the body, the gate structure including a gate
dielectric and a gate electrode, and the gate structure having a
gate-all-around (GAA) configuration on the body of semiconductor
material; a source region and a drain region both adjacent to the
body such that the body is between the source and drain regions, at
least one of the source region and the drain region including
n-type impurity; a shallow trench isolation (STI) region adjacent
the at least one of the source region and the drain region; and a
layer of insulation material between the at least one of the source
region and the drain region and the STI region, wherein the layer
of insulation material is distinct from the STI region, and wherein
the layer of insulation material comprises silicon, oxygen and
carbon.
2. The IC of claim 1, wherein the body of semiconductor material is
a nanowire.
3. The IC of claim 1, wherein the body of semiconductor material is
a nanoribbon.
4. The IC of claim 1, wherein the body of semiconductor material
includes at least 75% germanium by atomic percentage.
5. The IC of claim 4, wherein the body further includes at least
one of silicon, indium, gallium, arsenic, antimony, and
nitrogen.
6. The IC of claim 4, wherein the germanium concentration of the
body is 98 atomic percent or more.
7. The IC of claim 4, wherein the body further includes up to 2%
tin by atomic percentage, and/or the source region and drain region
include up to 2% tin by atomic percentage.
8. The IC of claim 1, wherein the layer of insulation material
includes silicon dioxide with a carbon concentration between 5 and
50% by atomic percentage.
9. The IC of claim 1, wherein the thickness of the layer of
insulation material is in the range of 1 nanometer to 5 nanometers,
the thickness being the distance between the STI region and the at
least one of the source region and the drain region.
10. The IC of claim 1, wherein the layer of insulation material is
further between the STI region and an underlying substrate.
11. The IC of claim 1, wherein in addition to the n-type impurity,
the source region and drain region are compositionally distinct
from the body, the source region and drain region including at
least one of silicon and germanium.
12. The IC of claim 1, wherein in addition to the n-type impurity,
the source region and drain region are compositionally different
from the body, the source region and drain region further including
at least one of silicon, indium, gallium, arsenic, antimony, and
nitrogen.
13. The IC of claim 1, wherein the n-type impurity is phosphorous
or arsenic.
14. The IC of claim 1, wherein the body is over a fin stub.
15. The IC of claim 1, further comprising interlayer dielectric
(ILD) material on an upper portion of the at least one of the
source region and the drain region, and the ILD material is on an
uppermost surface of the layer of insulation material, wherein the
at least one of the source region and the drain region extends
above the uppermost surface of the layer of insulation
material.
16. A computing device, comprising: a board; and a component
coupled to the board, the component including an integrated circuit
structure, comprising: a body of semiconductor material, the
semiconductor material comprising germanium; a gate structure on
the body, the gate structure including a gate dielectric and a gate
electrode, and the gate structure having a gate-all-around (GAA)
configuration on the body of semiconductor material; a source
region and a drain region both adjacent to the body such that the
body is between the source and drain regions, at least one of the
source region and the drain region including n-type impurity; a
shallow trench isolation (STI) region adjacent the at least one of
the source region and the drain region; and a layer of insulation
material between the at least one of the source region and the
drain region and the STI region, wherein the layer of insulation
material is distinct from the STI region, and wherein the layer of
insulation material comprises silicon, oxygen and carbon.
17. The computing device of claim 16, further comprising: a memory
coupled to the board.
18. The computing device of claim 16, further comprising: a
communication chip coupled to the board.
19. The computing device of claim 16, wherein the component is a
packaged integrated circuit die.
20. The computing device of claim 16, wherein the component is
selected from the group consisting of a processor, a communications
chip, and a digital signal processor.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Continuation of U.S. patent
application Ser. No. 16/641,022, filed Feb. 21, 2020, which is U.S.
national stage entry under 35 U.S.C. .sctn. 371(c) of International
Application No. PCT/US2017/053474, filed Sep. 26, 2017, the
disclosures of which are incorporated by reference herein in their
entirety.
BACKGROUND
[0002] Semiconductor devices are electronic components that exploit
the electronic properties of semiconductor materials, such as
silicon (Si), germanium (Ge), and silicon germanium (SiGe). A
field-effect transistor (FET) is a semiconductor device that
includes three terminals: a gate, a source, and a drain. A FET uses
an electric field applied by the gate to control the electrical
conductivity of a channel through which charge carriers (e.g.,
electrons or holes) flow from the source to the drain. In instances
where the charge carriers are electrons, the FET is referred to as
an n-channel device, and in instances where the charge carriers are
holes, the FET is referred to as a p-channel device. Standard
dopant used for Si, Ge, and SiGe includes boron (B) for p-type
(acceptor) dopant and phosphorous (P) or arsenic (As) for n-type
(donor) dopant. Some FETs have a fourth terminal called the body or
substrate, which can be used to bias the transistor. In addition,
metal-oxide-semiconductor FETs (MOSFETs) include a gate dielectric
between the gate and the channel. MOSFETs may also be known as
metal-insulator-semiconductor FETs (MISFETSs) or insulated-gate
FETs (IGFETs). Complementary MOS (CMOS) structures use a
combination of p-channel MOSFET (p-MOS) and n-channel MOSFET
(n-MOS) to implement logic gates and other digital circuits.
[0003] A FinFET is a MOSFET transistor built around a thin strip of
semiconductor material (generally referred to as a fin). The
conductive channel of the FinFET device resides on the outer
portions of the fin adjacent to the gate dielectric. Specifically,
current runs along/within both sidewalls of the fin (sides
perpendicular to the substrate surface) as well as along the top of
the fin (side parallel to the substrate surface). Because the
conductive channel of such configurations essentially resides along
the three different outer, planar regions of the fin, such a FinFET
design is sometimes referred to as a tri-gate transistor. Other
types of FinFET configurations are also available, such as
so-called double-gate FinFETs, in which the conductive channel
principally resides only along the two sidewalls of the fin (and
not along the top of the fin).
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] Features and advantages of embodiments of the claimed
subject matter will become apparent as the following Detailed
Description proceeds, and upon reference to the Drawings, wherein
like numerals depict like parts.
[0005] FIGS. 1A-1B illustrate a method of forming an integrated
circuit (IC) including at least one germanium (Ge)-rich n-MOS
transistor employing one or more dopant diffusion barriers,
specifically, to help prevent source/drain (S/D) dopant from
diffusing into surrounding shallow trench isolation (STI) material,
in accordance with some embodiments of the present disclosure.
[0006] FIGS. 2A-2N illustrate example IC structures that are formed
when carrying out the method of FIGS. 1A-1B, in accordance with
some embodiments
[0007] FIG. 3 illustrates an example cross-sectional view along the
plane A-A in FIG. 2M, in accordance with some embodiments.
[0008] FIG. 4 illustrates a computing system implemented with
integrated circuit structures and/or transistor devices formed
using the techniques disclosed herein, in accordance with some
embodiments of the present disclosure.
[0009] These and other features of the present embodiments will be
understood better by reading the following detailed description,
taken together with the figures herein described. In the drawings,
each identical or nearly identical component that is illustrated in
various figures may be represented by a like numeral. For purposes
of clarity, not every component may be labeled in every drawing.
Furthermore, as will be appreciated, the figures are not
necessarily drawn to scale or intended to limit the described
embodiments to the specific configurations shown. For instance,
while some figures generally indicate straight lines, right angles,
and smooth surfaces, an actual implementation of the disclosed
techniques may have less than perfect straight lines and right
angles, and some features may have surface topography or otherwise
be non-smooth, given real-world limitations of fabrication
processes. Further still, some of the features in the drawings may
include a patterned and/or shaded fill, which is merely provided to
assist in visually differentiating the different features. In
short, the figures are provided merely to show example
structures
[0010] Although the following Detailed Description will proceed
with reference being made to illustrative embodiments, many
alternatives, modifications, and variations thereof will be
apparent in light of this disclosure.
DETAILED DESCRIPTION
[0011] Integrated circuit transistor structures are disclosed that
reduce n-type dopant diffusion, such as phosphorous or arsenic,
from the source and drain regions into adjacent shallow trench
isolation (STI) regions during fabrication of n-MOS devices having
a germanium-rich channel (e.g., germanium concentration of 75
atomic % or more, up to 100 atomic %). In an example embodiment,
the structure includes an intervening diffusion barrier deposited
between the n-MOS transistor and the STI region to provide dopant
diffusion reduction. In some embodiments, the diffusion barrier
includes silicon dioxide with carbon concentrations between 5 and
50% by atomic percentage. In other embodiments, the diffusion
barrier includes at least one of silicon nitride, hafnium oxide,
and aluminum oxide. In some embodiments, the diffusion barrier is
deposited using chemical vapor deposition (CVD), atomic layer
deposition (ALD), or physical vapor deposition (PVD) techniques to
achieve a diffusion barrier thickness in the range of 1 to 5
nanometers. Numerous configurations and process flows will be
apparent in light of this disclosure.
General Overview
[0012] The fabrication of Ge-rich n-MOS transistors is generally
not practical due to the difficulty of maintaining a relatively
high level of n-type dopant in the source/drain regions of the
transistor. This is largely due to the physical properties of Ge,
wherein typical n-type dopants, such as phosphorous and arsenic,
readily diffuse from the Ge-rich source/drain regions under the
high temperature conditions associated with semiconductor
fabrication processes. For instance, Ge-rich n-MOS devices are
susceptible to spilling of the n-type dopant from the S/D regions
into the isolation trench material that separates and insulates
adjacent transistors. This spilling is particularly problematic
under the high temperature conditions associated with the
semiconductor fabrication process. The resulting transistor device
can exhibit poor S/D contact resistance due to the high energy
barrier at the metal-semiconductor interface, which cannot be
overcome by tunneling due to the low dopant levels resulting from
dopant diffusion out of the Ge material. Such high S/D contact
resistance can cause significant performance degradation. These
issues, resulting from dopant diffusion, are further exacerbated as
transistor devices are scaled down to include smaller critical
dimensions, for example using sub-30 nm technology, and beyond.
[0013] Thus, and in accordance with numerous embodiments of the
present disclosure, techniques are provided for forming Ge-rich
n-MOS transistors including one or more dopant diffusion barriers
configured to separate source/drain fin structures from shallow
trench isolation (STI) regions, as will be described in greater
detail below. As can be understood based on this disclosure, the
introduction of one or more dopant diffusion barriers helps to
inhibit the undesired diffusion of dopant (e.g., P, or As) into the
adjacent insulator or STI regions. The dopant diffusion barrier is
configured as an insulator with good surface charge passivation
properties and improved diffusion resistance properties. In some
embodiments, the diffusion barrier (e.g., the layer of insulation
material distinct from the STI region) may include silicon dioxide
(SiO.sub.2) with carbon concentrations between 5 and 50% by atomic
percentage, silicon nitride, hafnium oxide, or aluminum oxide,
although other compositions are possible.
[0014] Note that, as used herein, "Ge-rich" includes a
Ge-containing body that includes over 50% Ge by atomic percentage,
where the Ge or Si.sub.1-xGe.sub.x (x>0.5) may be doped with any
suitable material(s) and/or alloyed with other group IV elements
(e.g., carbon and/or tin up to 2% by atomic percentage). For
instance, in some embodiments, the Ge-rich material may be n-type
doped, such as Ge:As, Ge:P, SiGe:P (with over 50% Ge by atomic
percentage), or SiGe:As (with over 50% Ge by atomic percentage), to
provide some examples. Further, in some embodiments, the Ge-rich
material may include alloying of carbon and/or tin, such as Ge:C,
GeSn, SiGe:C, SiGeSn, GeSn:C, SiGeSn:C. Also note, that in some
embodiments, Ge-rich may include a different threshold
concentration (by atomic percentage) of Ge, such as at least 55,
60, 65, 70, 75, 80, 85, 90, or 95%, for example. For instance, in
some applications, embodiments where a Ge-rich channel region of a
transistor includes at least 80% Ge by atomic percentage may be
desired, or even a pure Ge channel, such as to achieve a desired
charge carrier mobility, for example. Further note that the
inclusion of Ge-rich material in a given feature as described
herein does not preclude the inclusion of materials other than Ge.
For instance, in some embodiments, a Ge-rich channel region may
include a multilayer structure that includes at least one Ge-rich
layer and at least one non-Ge-rich layer. However, in other
embodiments, a Ge-rich feature has Ge-rich material be throughout
essentially the entirety of that feature. Moreover, a Ge-rich
channel region may include grading of the concentration of Ge
throughout at least a portion of the channel region, such that
there may be one or more portions of that channel region that
include less than 50% Ge concentration by atomic percentage, and
may even include no Ge content at all.
[0015] Also, as used herein, "group IV semiconductor material" (or
"group IV material" or generally, "IV") includes at least one group
IV element (e.g., silicon, germanium, carbon, tin), such as silicon
(Si), germanium (Ge), silicon germanium (SiGe), and so forth. Note
that alloys of group IV elements are not to be confused with
compounds of those elements. Therefore, when carbon is alloyed with
any of the other group IV elements, the resulting alloy will be
expressed herein as "X:C", where "X" is the group IV element or
alloy and ":C" indicates alloying with carbon. For instance,
silicon alloyed with carbon may be referred to herein as Si:C
(thereby preventing confusion with silicon carbide (SiC)), silicon
germanium alloyed with carbon may be referred to herein as SiGe:C,
germanium alloyed with carbon may be referred to herein as Ge:C
(thereby preventing confusion with germanium carbide (GeC)), and so
forth. Also note that the molecular ratio or the atomic percentage
of the elements included in a group IV alloy can be adjusted as
desired. Further note that the use of "X:Z" herein indicates a
doping relationship where "X" is an element or alloy doped by "Z",
such as arsenic-doped silicon germanium being represented by
SiGe:As, or phosphorous-doped silicon germanium alloyed with carbon
being represented by SiGe:C:P, to provide some examples. Generally,
when referring to group IV semiconductor material as described
herein (e.g., Si, SiGe, Ge, SiSn, SiGeSn, GeSn, Si:C, SiGe:C, Ge:C,
SiSn:C, SiGeSn:C, GeSn:C), that group IV semiconductor material has
a monocrystalline (or single-crystal) structure, unless otherwise
stated, such as, for example, where polycrystalline silicon (or
poly-Si) may be utilized, as stated herein.
[0016] In some embodiments, the techniques can be used to benefit a
multitude of transistor devices. For instance, in some embodiments,
the techniques may be used to benefit one or more n-channel
transistor devices (where the charge carriers are electrons) such
as n-channel MOSFET (n-MOS) devices. In some embodiments, the
techniques described herein can be used to benefit complementary
transistor circuits, such as CMOS circuits, where the techniques
can be used to benefit one or more of the included n-channel
transistors (e.g., n-MOS devices) making up a given CMOS circuit.
Further still, in some embodiments, the techniques described herein
can be used to benefit transistors including a multitude of
transistor configurations, such as planar and non-planar
configurations, where the non-planar configurations may include
finned or FinFET configurations (e.g., dual-gate or tri-gate),
gate-all-around (GAA) configurations (e.g., nanowire or
nanoribbon), or some combination thereof, to provide a few
examples. Other example transistor devices that can benefit from
the techniques described herein include few to single electron
quantum transistor devices, for example.
[0017] As will be further appreciated, the Ge-rich n-MOS
transistors including one or more dopant diffusion barriers
configured to separate source/drain fin structures from STI regions
provided herein may also be intermixed on the same substrate with
other transistor devices having channel regions devoid of any
germanium, such as transistors having silicon channel regions,
gallium arsenide channel regions, indium arsenide channel regions,
gallium indium arsenide channel regions, or some combination of
compositionally diverse channel regions. Further note that some
channel regions may be native to the substrate (i.e., fins formed
from the substrate), while other channel regions may be epitaxially
provided on the substrate.
[0018] Note that, as used herein, the expression "X includes at
least one of A and B" refers to an X that may include, for example,
just A only, just B only, or both A and B. To this end, an X that
includes at least one of A and B is not to be understood as an X
that requires each of A and B, unless expressly so stated. For
instance, the expression "X includes A and B" refers to an X that
expressly includes both A and B. Moreover, this is true for any
number of items greater than two, where "at least one of" those
items is included in X. For example, as used herein, the expression
"X includes at least one of A, B, and C" refers to an X that may
include just A only, just B only, just C only, only A and B (and
not C), only A and C (and not B), only B and C (and not A), or each
of A, B, and C. This is true even if any of A, B, or C happens to
include multiple types or variations. To this end, an X that
includes at least one of A, B, and C is not to be understood as an
X that requires each of A, B, and C, unless expressly so stated.
For instance, the expression "X includes A, B, and C" refers to an
X that expressly includes each of A, B, and C. Likewise, the
expression "X included in at least one of A and B refers to an X
that may be included, for example, in just A only, in just B only,
or in both A and B. The above discussion with respect to "X
includes at least one of A and B" equally applies here, as will be
appreciated.
[0019] Use of the techniques and structures provided herein may be
detectable using tools such as: electron microscopy including
scanning/transmission electron microscopy (SEM/TEM), scanning
transmission electron microscopy (STEM), nano-beam electron
diffraction (NBD or NBED), and reflection electron microscopy
(REM); composition mapping; x-ray crystallography or diffraction
(XRD); energy-dispersive x-ray spectroscopy (EDS); secondary ion
mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom
probe imaging or tomography; local electrode atom probe (LEAP)
techniques; 3D tomography; or high resolution physical or chemical
analysis, to name a few suitable example analytical tools. In
particular, in some embodiments, such tools may indicate an
integrated circuit (IC) including at least one Ge-rich n-MOS
transistor that includes one or more dopant diffusion barriers as
described herein. For instance, in some such embodiments, the
techniques may be detected by observing (e.g., via SEM/TEM) that
SiO.sub.2 with carbon is present in a dopant diffusion barrier
separating the S/D region from the STI region. In some embodiments,
the techniques and structures described herein may be detected
based on the benefits derived therefrom, such as by observing a
Ge-rich n-MOS source/drain fin structure that does not exhibit
reduced levels of dopant (e.g., P or As) resulting from diffusion
into adjacent STI regions, as a result of the employment of one or
more dopant diffusion barriers as described herein (e.g., as
compared to Ge-rich n-MOS transistors that do not employ the
techniques described herein). Thus, in some embodiments, the
techniques described herein may enable forming enhanced performance
Ge-rich transistor devices with sub-30 nm technology and beyond,
which can also be detected and measured. Numerous configurations
and variations will be apparent in light of this disclosure.
Methodology and Architecture
[0020] FIGS. 1 (1A and 1B) illustrate method 100 of forming an
integrated circuit (IC) including at least one Ge-rich n-MOS
transistor employing one or more dopant diffusion barriers,
specifically, to help prevent or otherwise inhibit S/D dopant from
diffusing into the insulator material of an adjacent isolation
region or so-called STI region, in accordance with some embodiments
of the present disclosure. FIGS. 2A-N illustrate example IC
structures that are formed when carrying out method 100 of FIG. 1,
in accordance with some embodiments. The structures of FIGS. 2A-N
are primarily depicted and described herein in the context of
forming finned or FinFET transistor configurations (e.g., tri-gate
transistor configurations), for ease of illustration. However, in
some embodiments, the techniques can be used to form transistors of
any suitable geometry or configuration, as can be understood based
on this disclosure. Also note that the techniques and structures
are primarily depicted and described in the context of forming
metal-oxide-semiconductor field-effect transistors (MOSFETs).
However, the present disclosure is not intended to be so limited
unless stated otherwise. Further note that method 100 includes a
primary path that illustrates a gate last transistor fabrication
process flow that can be employed in accordance with some
embodiments. However, in other embodiments, a gate first process
flow may be employed instead, as will be described herein (and
which is illustrated with the alternative gate first flow 100'
indicator in FIG. 1). Numerous variations and configurations will
be apparent in light of this disclosure.
[0021] Method 100 of FIG. 1 (referring now to FIG. 1A) includes
patterning 102 hardmask on a substrate, such as patterning hardmask
210a on substrate 200 of FIG. 2A to form the example structure 210b
of FIG. 2B, in accordance with some embodiments. In some
embodiments, hardmask 210a may be deposited or otherwise formed on
substrate 200 using any suitable techniques as will be apparent in
light of this disclosure. For example, hardmask 210a may be blanket
deposited or otherwise grown on substrate 200 using chemical vapor
deposition (CVD), atomic layer deposition (ALD), physical vapor
deposition (PVD), spin-on processing, and/or any other suitable
process to form hardmask 210a on substrate 200. In some instances,
the top surface of substrate 200 on which hardmask 210a is to be
deposited may be treated (e.g., via chemical treatment, thermal
treatment, etc.) prior to deposition of the hardmask 210a material.
After being blanket formed on substrate 200, hardmask 210a may then
be patterned using any suitable techniques, such as one or more
lithography and etch processes, for example, to produce structure
210b. Hardmask 210a may include any suitable material, such as
oxide material, nitride material, and/or any other suitable masking
material, for example. Specific oxide and nitride materials may
include silicon oxide, titanium oxide, hafnium oxide, aluminum
oxide, silicon nitride, and titanium nitride, just to name a few
examples. In some cases, the material of hardmask 210a may be
selected based on the material of substrate 200, for example.
[0022] Substrate 200, in some embodiments, may be: a bulk substrate
including group IV semiconductor material (e.g., Si, Ge, SiGe),
group III-V semiconductor material (e.g., GaAs, GaAsSb, GaAsIn),
and/or any other suitable material(s) as will be apparent in light
of this disclosure; an X on insulator (XOI) structure where X is
one of the aforementioned materials (e.g., group IV and/or group
III-V semiconductor material) and the insulator material is an
oxide material or dielectric material or some other electrically
insulating material, such that the XOI structure includes the
electrically insulating material layer between two semiconductor
layers; or some other suitable multilayer structure where the top
layer includes one of the aforementioned semiconductor materials
(e.g., group IV and/or group III-V semiconductor material). The use
of "group IV semiconductor material" (or "group IV material" or
generally, "IV") herein includes at least one group IV element
(e.g., silicon, germanium, carbon, tin), such as silicon (Si),
germanium (Ge), silicon germanium (SiGe), and so forth. The use of
"group III-V semiconductor material" (or "group III-V material" or
generally, "III-V") herein includes at least one group III element
(e.g., aluminum, gallium, indium) and at least one group V element
(e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as
gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium
aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium
antimonide (GaSb), indium phosphide (InP), and so forth. Note that
group III may also be known as the boron group or IUPAC group 13,
group IV may also be known as the carbon group or IUPAC group 14,
and group V may also be known as the nitrogen family or IUPAC group
15, for example. In some embodiments, substrate 200 may include
Ge-rich material to be used in the channel region of one or more
transistors.
[0023] In some embodiments, substrate 200 may be doped with any
suitable n-type and/or p-type dopant. For instance, in the case, of
a Si substrate, the Si may be p-type doped using a suitable
acceptor (e.g., boron) or n-type doped using a suitable donor
(e.g., phosphorous, arsenic), to provide some example cases.
However, in some embodiments, substrate 200 may be
undoped/intrinsic or relatively minimally doped (such as including
a dopant concentration of less than 1E16 atoms per cubic cm), for
example. In some embodiments, substrate 200 may include a surface
crystalline orientation described by a Miller index of (100),
(110), or (111), or its equivalents, as will be apparent in light
of this disclosure. Although substrate 200, in this example
embodiment, is shown as having a thickness (dimension in the Y-axis
direction) similar to other layers shown in subsequent structures
for ease of illustration, in some instances, substrate 200 may be
much thicker than the other layers, such as having a thickness in
the range of 50 to 950 microns, for example, or any other suitable
thickness as will be apparent in light of this disclosure. In some
embodiments, substrate 200 may be used for one or more other IC
devices, such as various diodes (e.g., light-emitting diodes (LEDs)
or laser diodes), various transistors (e.g., MOSFETs or TFETs),
various capacitors (e.g., MOSCAPs), various microelectromechanical
systems (MEMS), various nanoelectromechanical systems (NEMS),
various radio frequency (RF) devices, various sensors, or any other
suitable semiconductor or IC devices, depending on the end use or
target application. Accordingly, in some embodiments, the
structures described herein may be included in a system-on-chip
(SoC) application, as will be apparent in light of this
disclosure.
[0024] Method 100 of FIG. 1 continues with performing 104 a shallow
trench recess (STR) etch to form fins 202 from substrate 200,
thereby forming the resulting example structure shown in FIG. 2C,
in accordance with some embodiments. In some embodiments, the STR
etch 104 used to form trenches 215 and fins 202 may include any
suitable techniques, such as various masking processes and wet
and/or dry etching processes, for example. In some cases, STR etch
104 may be performed in-situ/without air break, while in other
cases, STR etch 104 may be performed ex-situ, for example. Trenches
215 may be formed with varying widths (dimension in the X-axis
direction) and depths (dimension in the Y-axis direction) as can be
understood based on this disclosure. For example, multiple hardmask
patterning 102 and STR etching 104 processes may be performed to
achieve varying depths in the trenches 215 between fins 202. Fins
202 may be formed to have varying widths Fw (dimension in the
X-axis direction) and heights Fh (dimension in the Y-axis
direction). Note that although hardmask structures 210b are still
present in the example structure of FIG. 2C, in some cases, that
need not be the case, as they may have been consumed during the STR
etch, for example. Further note that, while the fins 202 are shown
as relatively rectangular in nature (with straight sides and a flat
top) for ease of depiction, in reality, the fins may include a
tapered profile where the top of the fin is narrower than the base
of the fin (as viewed in a cross-section taken perpendicular to the
fin). Moreover, the very top of the fin may be rounded, rather than
flat. Numerous other real-world geometries will be appreciated.
[0025] In some embodiments, the fin widths Fw (dimension in the
horizontal or X-axis direction) may be in the range of 2-400 nm (or
in a subrange of 2-10, 2-20, 2-50, 2-100, 2-200, 4-10, 4-20, 4-50,
4-100, 4-200, 4-400, 5-20, 10-20, 10-50,10-100, 10-200, 10-400,
50-100, 50-200, 50-400, 100-400 nm, or any other sub-range), for
example, or any other suitable value or range as will be apparent
in light of this disclosure. In some embodiments, the fin heights
Fh (dimension in the vertical or Y-axis direction) may be in the
range of 4-800 nm (or in a subrange of 4-10, 4-20, 4-50, 4-100,
4-200, 4-400, 10-20, 10-50, 10-80, 10-100, 10-200, 10-400, 10-800,
50-100, 50-200, 50-400, 50-800, 100-400, 100-800, 400-800 nm, or
any other sub-range), for example, or any other suitable value or
range as will be apparent in light of this disclosure. In some
embodiments, the fin heights Fh may be at least 10, 25, 35, 50, 75,
100, 125, 150, 175, 200, 300, 400, 500, 600, 700, or 800 nm tall,
or any other desired height as will be apparent in light of this
disclosure. In some embodiments, the height to width ratio of the
fins (Fh:Fw) may be greater than 1, such as greater than 1.5, 2,
2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9, or 10, or greater than any
other suitable threshold ratio, as will be apparent in light of
this disclosure. Note that the trenches 215 and fins 202 are each
shown as having essentially the same sizes and shapes in this
example structure for ease of illustration; however, the present
disclosure is not intended to be so limited. For example, in some
embodiments, the fins 202 may be formed to have varying heights Fh,
varying widths Fw, varying starting points (or varying starting
heights), varying shapes, and/or any other suitable variations as
will be apparent in light of this disclosure. Moreover, trenches
215 may be formed to have varying depths, varying widths, varying
starting points (or varying starting depths), varying shapes,
and/or any other suitable variations as will be apparent in light
of this disclosure. Further note that although four fins 202 are
shown in the example structure of FIG. 2C for ease of illustration,
any number of fins may be formed, such as one, two, three, five,
ten, hundreds, thousands, millions, and so forth, as can be
understood based on this disclosure.
[0026] Method 100 of FIG. 1 continues with depositing 106 a
diffusion barrier 212 to form the example resulting structure of
FIG. 2D, in accordance with some embodiments. Dopant diffusion
barrier 212 is configured to separate source/drain fin structures
202 from shallow trench isolation (STI) regions 220, as will be
described below. As can be understood based on this disclosure, the
introduction of one or more dopant diffusion barriers helps to
inhibit the undesired diffusion of n-type dopant or impurities
(e.g., P, or As) of the S/D regions (that will be subsequently
created) into the adjacent insulator or STI regions. The dopant
diffusion barrier 212 is configured as an insulator with good
surface charge passivation properties and improved diffusion
resistance properties. In some embodiments, the diffusion barrier
212 includes SiO.sub.2 with carbon concentrations between 5 and 50%
by atomic percentage. In some embodiments, the diffusion barrier
212 may also or alternatively include silicon nitride, hafnium
oxide, or aluminum oxide, although other compositions are possible.
In a more general sense, the diffusion barrier 212 can be any
material or composition that inhibits the diffusion of S/D dopant
into the neighboring STI areas, particularly in the context of a
n-type Ge-rich channel device.
[0027] Deposition 106 of diffusion barrier material 212 may include
any suitable deposition techniques, such as those described herein
(e.g., CVD, ALD, PVD), or any other suitable deposition process. In
some embodiments, the thickness of the deposited barrier layer 212
may be, for example, on the order of 2 nm (or in a range of 1-5 nm,
although other suitable ranges will be apparent in light of this
disclosure).
[0028] Method 100 of FIG. 1 continues with depositing 108 shallow
trench isolation (STI) material 220 to form the example resulting
structure of FIG. 2E, in accordance with some embodiments.
Deposition 108 of STI material 220 may include any suitable
deposition techniques, such as those described herein (e.g., CVD,
ALD, PVD), or any other suitable deposition process. In some
embodiments, STI material 220 (which may be referred to as an STI
layer or STI structure) may include any suitable electrically
insulating material, such as one or more dielectric, oxide (e.g.,
silicon dioxide), and/or nitride (e.g., silicon nitride) materials.
In some embodiments, the material of STI layer 220 may be selected
based on the material of substrate 200. For instance, in the case
of a Si substrate, the STI material may be selected to be silicon
dioxide or silicon nitride, to provide some examples. Method 100 of
FIG. 1 further continues with planarizing/polishing 110 the
structure to form the example resulting structure of FIG. 2F, in
accordance with some embodiments. The planarizing and/or polishing
process(es) performed after forming STI material 220 may include
any suitable techniques, such as chemical-mechanical
planarization/polishing (CMP) processes, for example. Note that the
hardmask 210b is removed by this planarization, in this example
embodiment. In other embodiments, the hardmask 210b may remain.
[0029] Method 100 of FIG. 1 continues with recessing 112 the native
fin material 202. In embodiments where the fins 202 are to be
removed and replaced with replacement semiconductor material (e.g.,
to be used in the channel region of one or more transistor
devices), the structure of FIG. 2F enables such processing. For
example, continuing from the structure of FIG. 2F to the structure
of FIG. 2G, fins 202 may be recessed or removed using selective
etch processing (e.g., for a given etchant, the semiconductor
material of fins 202 is removed selective to the insulator material
of STI layer 220) to form fin-shaped trenches 209 between STI
material 220 in which replacement semiconductor material can be
deposited/grown (e.g., using any suitable techniques, such as CVD,
metal-organic CVD (MOCVD), ALD, molecular beam epitaxy (MBE), PVD).
The depth of the etch can vary from one embodiment to the next. In
the embodiment shown, a portion of the native fin is left so as to
provide a pedestal or fin stub 207 on which the replacement fin
material can be deposited. In other embodiments, the native fin can
be completely removed, so as to be flush with the top surface of
substrate 200 to provide no pedestal or fin stub, or even below the
top surface of substrate 200 so as to provide an inverted pedestal
or fin stub.
[0030] Method 100 of FIG. 1 continues with deposition 114 of
replacement semiconductor fin material. For instance, FIG. 2H
illustrates recess and replace processing to form a replacement
material fin 230, in accordance with some embodiments. Replacement
fin 230 (and generally, any replacement fin formed) may include any
suitable semiconductor material (e.g., group IV and/or III-V
semiconductor material), but at least some of the fins will be
Ge-rich fins to be used for n-type transistor devices. For
instance, replacement fins including SiGe or Ge may be formed by
removing native Si fins during such processing and replacing them
with the SiGe or Ge material, to provide some examples. In
addition, replacement fin 230 may include any suitable n-type or
p-type dopant, or be undoped or lightly-doped. In some embodiments,
replacement material fins, such as replacement fin 230 of FIG. 2H
may be formed using alternative processing. For instance, in some
embodiments, replacement material fins may be formed by
blanket-growing the replacement material on the substrate (e.g.,
using epitaxial deposition processing) and then patterning the
replacement material into replacement material fins, to provide an
example alternative. Note that replacement fin 230 is illustrated
with patterning/shading to merely assist with visually identifying
that feature. In any such cases, the resulting structure can be
planarized to provide a relatively flat top surface, as generally
shown in FIG. 2H.
[0031] Method 100 of FIG. 1 continues with recessing 116 of the STI
material 220 between fins, as shown in FIG. 2I, to cause at least a
portion 231 of fins 230 to exude from the STI plane, thereby
forming the resulting example structure shown in FIG. 2I, in
accordance with some embodiments. Recessing 116 may be performed
using any suitable techniques, such as using one or more wet and/or
dry etch processes that allow the STI material 220 to be
selectively recessed relative to the material of fin 230, and/or
any other suitable processing as will be apparent in light of this
disclosure. As can be understood based on this disclosure, exposed
portions 231 of fins 230 may be used to provide the channel region
of one or more transistors, such that fin portions 231 (the
portions of fins 230 above the top plane of STI layer 220 after
recess 116 has been performed) may be referred to as channel
portions herein, for example. More specifically, the fin portion
231 under the gate structure to be subsequently formed is generally
referred to as the channel portion, with the source and drain
regions to be formed to either side of the channel portion, such
that the channel is between the source and drain regions. Moreover,
the portions of fins 230 below the top plane of STI layer 220 are
indicated as portions 232, where such portions may be referred to
as sub-channel portions, for example.
[0032] As shown in FIG. 2I, the portions 231 of fins 230 exuding
above the top plane of STI layer 220 have a fin height indicated as
Fh, which may be in the range of 4-800 nm (e.g., in the subrange of
4-10, 4-20, 4-50, 4-100, 4-200, 4-400, 10-20, 10-50, 10-80, 10-100,
10-200, 10-400, 10-800, 50-100, 50-200, 50-400, 50-800, 100-400,
100-800, 400-800 nm, or some other sub-range), for example, or any
other suitable value or range, as will be apparent in light of this
disclosure. In some specific embodiments, the fin heights Fh may be
at least 10, 25, 35, 50, 75, 100, 125, 150, 175, 200, 300, 400,
500, 600, 700, or 800 nm tall. Also note that in embodiments
employing planar transistor configurations, recess process 116 need
not be performed, as the transistor may be formed using the top
surface of semiconductor body 230 as shown in FIG. 2H, for
example.
[0033] Note that all of the fins are shown as being replaced in the
example embodiment of FIG. 2I; however, the present disclosure is
not intended to be so limited. In some embodiments, as illustrated
in FIG. 2J, only a subset may be replaced (e.g., such that some
replacement fins 230 are available for subsequent processing and
some native fins 202 remain for subsequent processing). FIG. 2J'
illustrates this in a perspective view.
[0034] Further, in some embodiments, the recess and replace process
may be performed as many times as desired to form as many subsets
of replacement fins as desired by masking off the areas not to be
processes for each replacement fin subset processing. This is
illustrated, for example, in FIG. 2K where two different sets of
replacement fins 230 and 240 are shown. In some such embodiments, a
first subset of replacement fins may be formed for n-channel
transistors (e.g., where the first replacement material is selected
to increase electron mobility) and a second subset of replacement
fins may be formed for p-channel transistors (e.g., where the
second replacement material is selected to increase hole mobility).
So, for instance, some of the native fins 202 are removed and
replaced with a first material 230 (e.g., Ge-rich material) and
others of the native fins 202 are removed and replaced with a
second material 240 (e.g., III-V material). FIG. 2K' illustrates
this in a perspective view. Further still, in some embodiments, a
multilayer replacement fin may be formed to enable the subsequent
formation of nanowires or nanoribbons in the channel region of one
or more transistors, where some of the layers in the multilayer
replacement fin are sacrificial and intended to be removed via
selective etching (e.g., during replacement gate processing).
Numerous such fin replacement schemes can be used, as will be
apparent.
[0035] Method 100 of FIG. 1 (referring now to FIG. 1B) continues
with optionally forming 118 a dummy gate stack to form the example
resulting structure of FIG. 2L, in accordance with some
embodiments. Recall that method 100 is primarily described herein
in the context of a gate last transistor fabrication process flow,
where the processing includes forming a dummy gate stack,
performing the S/D processing, and then forming the final gate
stack after the S/D regions have been processed. However, in other
embodiments, the techniques may be performed using a gate first
process flow. In such an example case, process 118 (forming a dummy
gate stack) would not be performed, and thus, process 118 may be
optional in some embodiments (such as those employing the gate
first process flow). This is reflected with the alternative
location for performing 122 final gate stack processing, which is
shown as the optional gate first flow 100' in FIG. 1, where
performing 122 the final gate stack processing would instead occur
at the location of box 118 in embodiments employing a gate first
process flow, for example. However, the description of method 100
will continue using a gate last process flow, to allow for such a
flow (which generally includes additional processing) to be
adequately described.
[0036] Continuing with forming 118 a dummy gate stack, such a dummy
gate stack (where employed) may include dummy gate dielectric 242
and dummy gate electrode 244, thereby forming the example resulting
structure of FIG. 2L, in this example embodiment. In this example
embodiment, dummy gate dielectric 242 (e.g., dummy oxide material)
and dummy gate electrode 244 (e.g., dummy poly-silicon material)
may be used for a replacement gate process. Note that gate spacers
250, on either side of the dummy gate stack were also formed, and
such gate spacers 250 can be used to help determine the channel
length and/or to help with replacement gate processes, for example.
As can be understood based on this disclosure, the dummy gate stack
(and gate spacers 250) can help define the channel region and
source/drain (S/D) regions of each transistor device, where the
channel region is below the dummy gate stack (as it will be located
below the final gate stack), and the S/D regions are on either side
of and adjacent to the channel region. Note that because the IC
structures are being described in the context of forming finned
transistors, the final gate stack will also be adjacent to either
side of the fin, as the gate stack will reside along the top and
opposing sidewalls of the finned channel regions, in embodiments
employing a finned (e.g., FinFET) configuration.
[0037] Formation of the dummy gate stack may include depositing the
dummy gate dielectric material 242 and dummy gate electrode
material 244, patterning the dummy gate stack, depositing gate
spacer material 250, and performing a spacer etch to form the
structure shown in FIG. 2L, for example. Gate spacers 250 may
include any suitable material, such as any suitable electrical
insulator, dielectric, oxide (e.g., silicon oxide), and/or nitride
(e.g., silicon nitride) material, as will be apparent in light of
this disclosure. Note that in some embodiments, as previously
described, the techniques described herein need not include forming
a dummy gate stack, such that a final gate stack may be formed in
the first instance. Regardless, the end structure will include a
final gate stack, as will be apparent in light of this disclosure.
Also note that in some embodiments, a hardmask may be formed over
the dummy gate stack (which may or may not also be formed over gate
spacers 250) to protect the dummy gate stack during subsequent
processing, for example. The previous relevant description of
hardmask 210 is equally applicable to such a hardmask feature,
where employed.
[0038] Method 100 of FIG. 1 continues with performing 120 the
source/drain (S/D) region processing to form the example resulting
structure of FIG. 2L', in accordance with some embodiments. The S/D
region processing 120 may include an etch and replace process,
where portions of the replacement fins 230 are removed in the S/D
regions by way of a selective etch (or any other suitable etch
scheme) followed by epitaxial deposition of the desired S/D
material thereby forming the bulk S/D regions 261, yielding the
example structure of FIG. 2L', in this example embodiment. In some
embodiments, S/D regions 261 can be formed using any suitable
techniques, such as one or more of the deposition processes
described herein (e.g., CVD, ALD, PVD, MBE), and/or any other
suitable processes as will be apparent in light of this disclosure.
In some such embodiments, S/D regions 261 may be formed using a
selective deposition process, e.g., such that the material of the
features only or significantly only grows (or only grows in a
monocrystalline structure) from the exposed semiconductor material,
as can be understood based on this disclosure. In other
embodiments, the S/D regions 261 are implantation doped portions of
the fins (202, 230, 240).
[0039] Note that the S/D regions 261 are referred to herein as such
for ease of description, but each S/D region may be either a source
region or a drain region, such that the corresponding S/D region
(on the other side of the channel region, and thus, on the other
side of the dummy gate stack) is the other of the source region and
drain region, thereby forming a source and drain region pair. For
instance, as shown in FIG. 2L', there are four channel regions and
four corresponding S/D region 261 pairs.
[0040] In some embodiments, the S/D region 261 may include any
suitable semiconductor material as will be apparent in light of
this disclosure, such as monocrystalline group IV semiconductor
material. For instance, a given S/D region may include at least one
of Si, Ge, Sn, and C. In some embodiments, a given S/D region may
or may not include n-type and/or p-type dopant (such as in one of
the schemes described herein). Where present, the dopant may be
included in a concentration in the range of 1E17 to 5E22 atoms per
cubic cm or greater, for example. In some embodiments, a given S/D
region may include grading (e.g., increasing and/or decreasing) of
the concentration of one or more materials within the feature, such
as the grading of a semiconductor material component concentration
and/or the grading of the dopant concentration, for example. For
instance, in some such embodiments, the dopant concentration
included in a given S/D region may be graded such that it is lower
near the corresponding channel region and higher near the
corresponding S/D contact, which may be achieved using any suitable
processing, such as tuning the amount of dopant in the reactant
flow (e.g., during an in-situ doping scheme), to provide an
example. In some embodiments, a given S/D 261 region may include a
multilayer structure that includes at least two compositionally
different material layers. For instance, in the case of a Fermi
Field FET (FFFET) device, the source region may include a
multilayer structure that includes a p-type doped region and n-type
doped region, in accordance with some embodiments. In some
embodiments, a given S/D region 261 may be raised such that it
extends higher than a corresponding channel region (e.g., in the
vertical or Y-axis direction).
[0041] In some embodiments, S/D region 261 may have different
shapes and configurations, depending on the forming processes used,
as will be apparent in light of this disclosure. For instance, in
the example structure of FIG. 2L' the S/D regions include
three-dimensional diamond shapes, with two top surfaces that are
faceted (e.g., with {111} faceting) as shown. Other example
structures may be formed, in accordance with some embodiments,
including a rounded (or curved) and unfaceted top, and the rounded
or curved S/D region may extend past the underlying sub-fin portion
in the X-axis direction. As can be understood based on this
disclosure, S/D regions including any shape (such as the diamond
shape of S/D region 261, or a rounded shape) can benefit from the
techniques described herein.
[0042] In some embodiments, one of the S/D regions in a
corresponding S/D region pair (such as region 261 on one side of
the dummy gate stack) may be processed separately than the other
S/D region in that pair (such as region 261 on the opposite side of
the dummy gate stack), such that a corresponding S/D pair may
include different material, dopant type, dopant concentration,
sizes, shapes, and/or any other suitable difference as can be
understood based on this disclosure. For instance, in the case of a
TFET device, one of the S/D regions may include n-type doped
semiconductor material and the other of the S/D regions may include
p-type doped semiconductor material, to provide an example case,
such that the n-type S/D region may be processed separately from
the p-type S/D region. The separate processing may be achieved
using any suitable techniques, such as masking off S/D regions not
to be processed to allow processing of other S/D regions, and then
masking off the other S/D regions to allow processing of the
originally masked off S/D regions, for example. In some
embodiments, a given S/D region may include the same or a similar
material composition (e.g., within 1% different) as the
corresponding/adjacent channel region (such as both including the
same Ge-rich material). However, in other embodiments, a given S/D
region may include a different material composition (e.g., at least
1, 2, 3, 4, 5, or 10% different) relative to the
corresponding/adjacent channel region, for example.
[0043] Method 100 of FIG. 1 continues with performing 122 the final
gate stack processing to form the example resulting structure of
FIG. 2M, in accordance with some embodiments. As shown in FIG. 2M,
the processing in this example embodiment included depositing
interlayer dielectric (ILD) layer 270 on the structure of FIG. 2L',
followed by planarization and/or polishing (e.g., CMP) to reveal
the dummy gate stack. Note that ILD layer 270 may include a
multilayer structure, even though it is illustrated as a single
layer. Further note that in some cases, ILD layer 270 and STI
material 220 may not include a distinct interface as shown in FIG.
2M, particularly where, e.g., the ILD layer 270 and STI material
220 include the same dielectric material (e.g., where both include
silicon dioxide). In general, the ILD layer 270 may include any
desired electrical insulator, dielectric, oxide (e.g., silicon
oxide), and/or nitride (e.g., silicon nitride) material, as will be
apparent in light of this disclosure.
[0044] The gate stack processing, in this example embodiment,
continues with removing the dummy gate stack (including dummy gate
244 and dummy gate dielectric 242) to allow for the final gate
stack to be formed. Recall that in some embodiments, the formation
of the final gate stack, which includes gate dielectric 282 and
gate electrode 284, may be performed using a gate first flow. In
such embodiments, the final gate stack processing may have been
alternatively performed at box 118, instead of forming a dummy gate
stack. However, in this example embodiment, the final gate stack is
formed using a gate last flow (also called a replacement gate or
replacement metal gate (RMG) process). Regardless of whether gate
first or gate last processing is employed, the final gate stack can
include gate dielectric 282 and gate electrode 284 as shown in FIG.
2M and described herein.
[0045] Note that when the dummy gate is removed, the channel region
of fins 202 (or replacement fins 230, 240), which is the portion of
the fins that were covered by the dummy gate stack, are exposed to
allow for any desired processing of those channel regions. Such
processing of a given channel region may include various different
techniques, such as removing and replacing the channel region with
replacement material, doping the channel region as desired, forming
the channel region into one or more nanowires (or nanoribbons) for
a gate-all-around (GAA) transistor configuration, cladding the
channel region, cleaning/polishing the channel region, and/or any
other suitable processing as will be apparent in light of this
disclosure.
[0046] In some embodiments, a given channel region of a transistor
device may include monocrystalline Ge-rich group IV semiconductor
material, such as monocrystalline Ge or monocrystalline SiGe with
over 50% Ge by atomic percentage, and/or any other suitable
material as will be apparent in light of this disclosure. In
general, a given channel region may include at least one of silicon
(Si) and germanium (Ge), to provide some examples. In some
embodiments, the channel region may be lightly doped (e.g., with
any suitable n-type and/or p-type dopant) or intrinsic/undoped (or
nominally undoped, with a dopant concentration less than 1E16 atoms
per cubic cm), depending on the particular configuration. In some
embodiments, a given channel region may include grading (e.g.,
increasing and/or decreasing) of the concentration of one or more
materials within the feature, such as the grading of a
semiconductor material component concentration and/or the grading
of the dopant concentration, for example. In some embodiments, a
given channel region may include a multilayer structure that
includes at least two compositionally different material layers. As
can be understood based on this disclosure, the channel region is
at least below the gate stack, in this example embodiment. For
instance, in the case of a finned transistor configuration, the
channel region may be below and between the gate stack, as the
stack is formed on a top and opposing sides of a semiconductor body
or fin. However, if the transistor device were inverted and bonded
to what will be the end substrate, then the channel region may be
above the gate. Therefore, in general, the gate structure and
channel region may include a proximate relationship, where the gate
structure is near the channel region such that it can exert control
over the channel region in an electrical manner, in accordance with
some embodiments. Further, in the case of a nanowire (or nanoribbon
or GAA) transistor configuration, the gate stack may completely
surround each nanowire/nanoribbon in the channel region (or at
least substantially surround each nanowire, such as surrounding at
least 70, 80, or 90% of each nanowire). Further still, in the case
of a planar transistor configuration, the gate stack may simply be
above the channel region.
[0047] Note that the S/D regions 261 are adjacent to either side of
a corresponding channel region, such as can be seen in FIG. 2M, for
example. Also note that the configuration/geometry of a transistor
formed using the techniques described herein may primarily be
described based on the shape of the respective channel region of
that transistor. For instance, a nanowire (or nanoribbon or GAA)
transistor may be referred to as such because it includes one or
more nanowires (or nanoribbons) in the channel region of that
transistor and because the gate stack (including the gate) wraps
around (or at least substantially wraps around) each nanowire (or
nanoribbon). However, the transistor type (e.g., MOSFET, TFET,
FFFET, or other suitable type) may be described based on the doping
and/or operating scheme of the source, channel, and drain regions,
and thus those respective regions may be used to determine the type
or classification of a given transistor, for example. For instance,
MOSFET and TFET transistors may structurally be very similar (or
the same), but they include different doping schemes (e.g.,
source-drain doping schemes for MOSFET of p-p or n-n versus p-n or
n-p for TFET).
[0048] Continuing with performing 122 final gate stack processing,
after the dummy gate has been removed and any desired channel
region processing has been performed, the final gate stack can then
be formed, in accordance with some embodiments. In this example
embodiment, the final gate stack includes gate dielectric 282 and
gate electrode 284, as shown in FIG. 2M. The gate dielectric 282
may include any suitable dielectric (such as silicon dioxide,
and/or a high-k dielectric material), as will be apparent in light
of this disclosure. Examples of high-k dielectric materials
include, for instance, hafnium oxide, hafnium silicon oxide,
lanthanum oxide, lanthanum aluminum oxide, zirconium oxide,
zirconium silicon oxide, tantalum oxide, titanium oxide, barium
strontium titanium oxide, barium titanium oxide, strontium titanium
oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide,
and lead zinc niobate, to provide some examples. In some
embodiments, the gate dielectric 282 may include one or more
silicates (e.g., titanium silicate, tungsten silicate, niobium
silicate, and silicates of other transition metals). In some
embodiments, an annealing process may be carried out on the gate
dielectric 282 to improve its quality when high-k dielectric
material is used. The gate electrode 284 may include a wide range
of materials, such as various suitable metals or metal alloys, such
as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta),
copper (Cu), and carbides and nitrides thereof, for example. In
some embodiments, gate dielectric 282 and/or gate electrode 284 may
include a multilayer structure of two or more material layers, for
example. For instance, in one embodiment, the gate dielectric
includes a first layer of silicon dioxide on the channel region,
and a second layer of hafnium oxide on the first layer. That gate
electrode may include, for instance, a metal plug along with one or
more workfunction layers, resistance-reducing layers, and/or
barrier layers. In some embodiments, gate dielectric 282 and/or
gate electrode 284 may include grading (e.g., increasing and/or
decreasing) the content/concentration of one or more materials in
at least a portion of the feature(s). Note that although gate
dielectric 282 is only shown below gate electrode 284 in the
example embodiment of FIG. 2M, in other embodiments, the gate
dielectric 282 may also be present on one or both sides of gate
electrode 284, such that the gate dielectric 282 is u-shaped (in a
cross-sectional profile) may also be between gate electrode 284 and
one or both of gate spacers 250, for example. Numerous different
gate stack configurations will be apparent in light of this
disclosure.
[0049] Method 100 of FIG. 1 continues with performing 124 S/D
contact processing to form the example resulting structure of FIG.
2M, in accordance with some embodiments. S/D contact processing
124, in this example embodiment, first includes forming S/D contact
trenches 290 above the S/D regions 261, as shown in FIG. 2M. In
some such embodiments, the contact trenches 290 may be formed using
any suitable techniques, such as performing one or more wet and/or
dry etch processes to remove portions of ILD layer 270 as shown,
and/or any other suitable processing as will be apparent in light
of this disclosure. Such etch processing may be referred to as the
S/D contact trench etch processing, or simply, contact trench etch
processing. Further, in some such embodiments, the ILD may first be
patterned such that areas that are not to be removed via the
contact trench etch processing are masked off, for example. In some
embodiments, one or more etch stop layers may have been formed on
S/D regions 261 prior to performing the contact trench etch
processing, to help with the controllability of the processing
(e.g., to help stop the etching to help prevent the etching from
consuming material of the S/D regions 261 in an undesired manner).
In some such embodiments, the etch stop layer(s) may include
insulator material that is dissimilar from the ILD 270 material
(e.g., to provide relative etch selectivity) and/or material that
is resilient to the contact trench etch, such as a carbon-based
etch stop layer (e.g., with carbon concentration in the range of
1-80%).
[0050] Continuing from the example structure of FIG. 2M contact
processing 124 includes forming S/D contacts 291 above respective
S/D regions 261, in accordance with some embodiments. In the
example structure of FIG. 2M, it can be understood that S/D
contacts 291 are electrically connected to S/D regions 261, and in
some cases, they may also be in physical contact with those S/D
regions 261. In some embodiments, S/D contacts 291 may be formed
using any suitable techniques, such as depositing metal or metal
alloy (or other suitable electrically conductive material) in
contact trenches 290. In some embodiments, S/D contact 291
formation may include silicidation, germanidation, and/or annealing
processes, for example, where such processing may be performed to
form an intervening contact layer before forming the bulk contact
metal structure, for instance. In some embodiments, S/D contacts
291 may include aluminum or tungsten, although any suitable
conductive metal or alloy can be used, such as silver,
nickel-platinum, or nickel-aluminum, for example. Generally, in
some embodiments, one or more of the S/D contacts 291 may include a
resistance reducing metal and a contact plug metal, or just a
contact plug, for instance. Example contact resistance reducing
metals include, for instance, nickel, aluminum, titanium, cobalt,
nickel-platinum, or nickel aluminum, and/or other such resistance
reducing metals or alloys. Example contact plug metals include, for
instance, aluminum, copper, nickel, platinum, titanium, or
tungsten, or alloys thereof, although any suitably conductive
contact metal or alloy may be used. In some embodiments, S/D
contacts 291 may employ low work-function metal material(s) and/or
high work-function metal material(s), depending on the particular
configuration. In some embodiments, additional layers may be
present in the S/D contact regions, such as adhesion layers (e.g.,
titanium nitride) and/or liner or barrier layers (e.g., tantalum
nitride), if so desired.
[0051] FIG. 2N illustrates another view in 3 dimensions (x,y,z) of
the example structure of FIG. 2L', according to an embodiment.
Shown in this figure are the substrate 200, the diffusion barrier
212 separating the source/drain fin structures 232, 261 from the
STI regions 220. Also shown in the background is gate spacer 250.
Both p-MOS 261a and n-MOS 261b replacement S/D material are shown
after, for example, epitaxial S/D processing. Additionally, S/D
isolation walls 295 are shown in this example embodiment.
[0052] FIG. 3 illustrates an example cross-sectional view along the
plane A-A in FIG. 2M, in accordance with some embodiments. The
cross-sectional view of FIG. 3 is provided to assist in
illustrating different features of the structure of FIG. 2M.
Therefore, the relevant description with respect to each similarly
numbered feature is equally applicable to FIG. 3. However, note
that the dimensions of the features shown in FIG. 3 may differ
relative to the features in FIG. 2M, for ease of illustration. Also
note that some variations occur between the structures, such as the
shape of gate spacers 250 and the shape of finned channel region
230, for example. Further note that channel region 230 shown in
FIG. 3 is not native to substrate 200; however, in other
embodiments, the channel region (and thus, the material of that
channel region) may be native to substrate 200. Further still, note
that the particular S/D configuration employed in the structure of
FIG. 3 is the same S/D configuration from FIG. 2M. To facilitate
cross referencing between FIG. 2M and FIG. 3, the vertical extent
(along the Y-axis) of the STI 220 is shown, although the STI is not
present in the A-A plane, but rather at other locations along the
X-axis, as shown in FIG. 2M.
[0053] In some embodiments, the length of gate electrode 284 (e.g.,
the dimension between spacers 250 in the Z-axis direction), which
is indicated as Lg in FIG. 3, may be any suitable length as will be
apparent in light of this disclosure. For instance, in some
embodiments, the gate length may be in the range of 3-100 nm (e.g.,
3-10, 3-20, 3-30, 3-50, 5-10, 5-20, 5-30, 5-50, 5-100, 10-20,
10-30, 10-50, 10-100, 20-30, 20-50, 20-100, or 50-100 nm) or
greater, for example. In some embodiments, the gate length may be
less than a given threshold, such as less than 100, 50, 45, 40, 35,
30, 25, 20, 15, 10, 8, or 5 nm, or less than some other suitable
threshold as will be apparent in light of this disclosure. In some
embodiments, the techniques enable maintaining a desired device
performance when scaling to such low thresholds, such as sub-50,
sub-40, sub-30, or sub-20 nm thresholds and beyond, as can be
understood based on this disclosure. For instance, the techniques
as variously described herein can reduce short channel effects,
thereby increasing the effective channel length (dimension between
the S/D regions in the Z-axis direction). Further, the techniques
described herein may allow the gate length and the effective
channel length to be the same or approximately the same, in
accordance with some embodiments. For instance, in some such
embodiments, being approximately the same with respect to the
effective channel length and the gate length may include that the
effective channel length is within 1-10 nm (e.g., within 1, 2, 3,
4, 5, 6, 7, 8, 9, or 10 nm) or within 1-10% (e.g., within 1, 2, 3,
4, 5, 6, 7, 8, 9, or 10%) different (e.g., shorter) than the gate
length. Thus, the gate length may approximate the effective channel
length, in some such embodiments, especially where the dopant
diffusion barrier techniques described herein essentially prevent
dopant from diffusing into the channel region.
[0054] Method 100 of FIG. 1 continues with completing 126
integrated circuit (IC) processing as desired, in accordance with
some embodiments. Such additional processing to complete the IC may
include back-end or back-end-of-line (BEOL) processing to form one
or more metallization layers and/or to interconnect the transistor
devices formed during front-end or front-end-of-line (FEOL)
processing, for example. Any other suitable processing may be
performed, as will be apparent in light of this disclosure. Note
that the processes 102-126 of method 100 are shown in a particular
order for ease of description. However, one or more of the
processes 102-126 may be performed in a different order or may not
be performed at all. For example, box 118 is an optional process
that need not be performed in embodiments employing a gate first
process flow. Recall that the techniques may be used to form a
multitude of different transistor types and configurations.
Although the techniques are primarily depicted and described herein
in the context of employing one or more dopant diffusion barriers
to separate heavily-doped source/drain structures from shallow
trench isolation (STI) regions of a given n-MOS transistor having a
Ge-rich channel region, the present disclosure is not intended to
be so limited, as the techniques may be used to benefit only one
side of a given channel region, and not the other, in some
embodiments. Numerous variations and configurations will be
apparent in light of the present disclosure.
Example System
[0055] FIG. 4 illustrates a computing system 1000 implemented with
integrated circuit structures and/or transistor devices formed
using the techniques disclosed herein, in accordance with some
embodiments of the present disclosure. As can be seen, the
computing system 1000 houses a motherboard 1002. The motherboard
1002 may include a number of components, including, but not limited
to, a processor 1004 and at least one communication chip 1006, each
of which can be physically and electrically coupled to the
motherboard 1002, or otherwise integrated therein. As will be
appreciated, the motherboard 1002 may be, for example, any printed
circuit board, whether a main board, a daughterboard mounted on a
main board, or the only board of system 1000, etc.
[0056] Depending on its applications, computing system 1000 may
include one or more other components that may or may not be
physically and electrically coupled to the motherboard 1002. These
other components may include, but are not limited to, volatile
memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics
processor, a digital signal processor, a crypto processor, a
chipset, an antenna, a display, a touchscreen display, a
touchscreen controller, a battery, an audio codec, a video codec, a
power amplifier, a global positioning system (GPS) device, a
compass, an accelerometer, a gyroscope, a speaker, a camera, and a
mass storage device (such as hard disk drive, compact disk (CD),
digital versatile disk (DVD), and so forth). Any of the components
included in computing system 1000 may include one or more
integrated circuit structures or devices formed using the disclosed
techniques in accordance with an example embodiment. In some
embodiments, multiple functions can be integrated into one or more
chips (e.g., for instance, note that the communication chip 1006
can be part of or otherwise integrated into the processor
1004).
[0057] The communication chip 1006 enables wireless communications
for the transfer of data to and from the computing system 1000. The
term "wireless" and its derivatives may be used to describe
circuits, devices, systems, methods, techniques, communications
channels, etc., that may communicate data through the use of
modulated electromagnetic radiation through a non-solid medium. The
term does not imply that the associated devices do not contain any
wires, although in some embodiments they might not. The
communication chip 1006 may implement any of a number of wireless
standards or protocols, including, but not limited to, Wi-Fi (IEEE
802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term
evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS,
CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any
other wireless protocols that are designated as 3G, 4G, 5G, and
beyond. The computing system 1000 may include a plurality of
communication chips 1006. For instance, a first communication chip
1006 may be dedicated to shorter range wireless communications such
as Wi-Fi and Bluetooth and a second communication chip 1006 may be
dedicated to longer range wireless communications such as GPS,
EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
[0058] The processor 1004 of the computing system 1000 includes an
integrated circuit die packaged within the processor 1004. In some
embodiments, the integrated circuit die of the processor includes
onboard circuitry that is implemented with one or more integrated
circuit structures or devices formed using the disclosed
techniques, as variously described herein. The term "processor" may
refer to any device or portion of a device that processes, for
instance, electronic data from registers and/or memory to transform
that electronic data into other electronic data that may be stored
in registers and/or memory.
[0059] The communication chip 1006 also may include an integrated
circuit die packaged within the communication chip 1006. In
accordance with some such example embodiments, the integrated
circuit die of the communication chip includes one or more
integrated circuit structures or devices formed using the disclosed
techniques as variously described herein. As will be appreciated in
light of this disclosure, note that multi-standard wireless
capability may be integrated directly into the processor 1004
(e.g., where functionality of any chips 1006 is integrated into
processor 1004, rather than having separate communication chips).
Further note that processor 1004 may be a chip set having such
wireless capability. In short, any number of processor 1004 and/or
communication chips 1006 can be used. Likewise, any one chip or
chip set can have multiple functions integrated therein.
[0060] In various implementations, the computing system 1000 may be
a laptop, a netbook, a notebook, a smartphone, a tablet, a personal
digital assistant (PDA), an ultra-mobile PC, a mobile phone, a
desktop computer, a server, a printer, a scanner, a monitor, a
set-top box, an entertainment control unit, a digital camera, a
portable music player, a digital video recorder, or any other
electronic device or system that processes data or employs one or
more integrated circuit structures or devices formed using the
disclosed techniques, as variously described herein. Note that
reference to a computing system is intended to include computing
devices, apparatuses, and other structures configured for computing
or processing information.
Further Example Embodiments
[0061] The following examples pertain to further embodiments, from
which numerous permutations and configurations will be
apparent.
[0062] Example 1 is an integrated circuit (IC) comprising: a
semiconductor body including at least 75% germanium by atomic
percentage; a gate structure on the semiconductor body, the gate
structure including a gate dielectric and a gate electrode; a
source region and a drain region both adjacent to the gate
structure such that the gate structure is between the source and
drain regions, at least one of the source region and the drain
region including n-type impurity; a shallow trench isolation (STI)
region adjacent the at least one of the source region and the drain
region; and a layer of insulation material between the at least one
of the source region and the drain region and the STI region,
wherein the layer of insulation material is distinct from the STI
region.
[0063] Example 2 includes the subject matter of Example 1, wherein
the semiconductor body further includes at least one of silicon,
indium, gallium, arsenic, antimony, and nitrogen.
[0064] Example 3 includes the subject matter of Examples 1 or 2,
wherein the germanium concentration of the semiconductor body is 98
atomic percent or more.
[0065] Example 4 includes the subject matter of any of Examples
1-3, wherein the semiconductor body further includes up to 2% tin
by atomic percentage.
[0066] Example 5 includes the subject matter of any of Examples
1-4, wherein in addition to the n-type impurity, the source region
and drain region are compositionally distinct from the
semiconductor body, the source region and drain region including at
least one of silicon and germanium.
[0067] Example 6 includes the subject matter of any of Examples
1-5, wherein in addition to the n-type impurity, the source region
and drain region are compositionally different from the
semiconductor body, the source region and drain region further
including at least one of silicon, indium, gallium, arsenic,
antimony, and nitrogen.
[0068] Example 7 includes the subject matter of any of Examples
1-6, wherein the source region and drain region further include up
to 2% tin by atomic percentage.
[0069] Example 8 includes the subject matter of any of Examples
1-7, wherein the layer of insulation material includes silicon
dioxide with carbon concentrations between 5 and 50% by atomic
percentage.
[0070] Example 9 includes the subject matter of any of Examples
1-8, wherein the layer of insulation material includes silicon
nitride.
[0071] Example 10 includes the subject matter of any of Examples
1-9, wherein the layer of insulation material includes hafnium
oxide.
[0072] Example 11 includes the subject matter of any of Examples
1-10, wherein the layer of insulation material includes aluminum
oxide.
[0073] Example 12 includes the subject matter of any of Examples
1-11, wherein the n-type impurity is phosphorous or arsenic.
[0074] Example 13 includes the subject matter of any of Examples
1-12, wherein the thickness of the layer of insulation material is
in the range of 1 nanometer to 5 nanometers, the thickness being
the distance between the STI region and the at least one of the
source region and the drain region.
[0075] Example 14 includes the subject matter of any of Examples
1-13, wherein the layer of insulation material is further between
the STI region and the substrate.
[0076] Example 15 includes the subject matter of any of Examples
1-14, wherein the layer of insulation material includes a chemical
composition that provides surface charge passivation and diffusion
resistance properties.
[0077] Example 16 includes the subject matter of any of Examples
1-15, wherein the semiconductor body is on a fin stub, and the
layer of insulation material is on opposing sidewalls of the fin
stub as well as opposing sidewalls of the semiconductor body.
[0078] Example 17 includes the subject matter of any of Examples
1-16, wherein the at least one of the source region and the drain
region is on the fin stub, and the layer of insulation material is
on opposing sidewalls of the fin stub as well as opposing sidewalls
of the at least one of the source region and the drain region.
[0079] Example 18 includes the subject matter of any of Examples
1-17, wherein the fin stub is part of an underlying semiconductor
substrate.
[0080] Example 19 includes the subject matter of any of Examples
1-18, wherein the substrate is silicon and the semiconductor body
includes at least one of germanium, gallium, arsenic, indium,
antimony, and nitrogen.
[0081] Example 20 includes the subject matter of any of Examples
1-19, wherein the at least one of the source region and the drain
region extends above an uppermost surface of the layer of
insulation material.
[0082] Example 21 includes the subject matter of any of Examples
1-20, further comprising interlayer dielectric (ILD) material on an
upper portion of the at least one of the source region and the
drain region.
[0083] Example 22 includes the subject matter of any of Examples
1-21, further comprising a first contact structure in the ILD
material and on the source region, and a second contact structure
in the ILD material and on the drain region.
[0084] Example 23 includes the subject matter of any of Examples
1-22, wherein ILD material is on the uppermost surface of the layer
of insulation material and the STI region.
[0085] Example 24 includes the subject matter of any of Examples
1-23, wherein the semiconductor body is a fin.
[0086] Example 25 includes the subject matter of any of Examples
1-24, wherein the semiconductor body includes one or more
nanowires.
[0087] Example 26 includes the subject matter of any of Examples
1-25, wherein the semiconductor body includes one or more
nanoribbons.
[0088] Example 27 includes the subject matter of any of Examples
1-26, wherein at least one of the gate dielectric and the gate
electrode is on an uppermost surface of the layer of insulation
material.
[0089] Example 28 includes the subject matter of any of Examples
1-27, wherein the gate structure further includes a first gate
spacer between the source region and the gate electrode, and a
second gate spacer between the drain region and the gate
electrode.
[0090] Example 29 includes the subject matter of any of Examples
1-28, wherein at least one of the first gate spacer and the second
gate spacer is on an uppermost surface of the layer of insulation
material.
[0091] Example 30 is a computing system comprising the IC of any of
Examples 1-29.
[0092] Example 31 is a method of forming an integrated circuit
(IC), the method comprising: forming a semiconductor body including
at least 75% germanium by atomic percentage; forming a gate
structure on the semiconductor body, the gate structure including a
gate dielectric and a gate electrode; forming a source region and a
drain region both adjacent to the gate structure such that the gate
structure is between the source and drain regions, at least one of
the source region and the drain region including n-type impurity;
forming a shallow trench isolation (STI) region adjacent the at
least one of the source region and the drain region; and forming a
layer of insulation material between the at least one of the source
region and the drain region and the STI region, wherein the layer
of insulation material is distinct from the STI region.
[0093] Example 32 includes the subject matter of Example 31,
wherein the semiconductor body further includes at least one of
silicon, indium, gallium, arsenic, antimony, and nitrogen.
[0094] Example 33 includes the subject matter of Examples 31 or 32,
wherein the germanium concentration of the semiconductor body is 98
atomic percent or more.
[0095] Example 34 includes the subject matter of any of Examples
31-33, wherein the semiconductor body further includes up to 2% tin
by atomic percentage.
[0096] Example 35 includes the subject matter of any of Examples
31-34, wherein in addition to the n-type impurity, the source
region and drain region are compositionally distinct from the
semiconductor body, the source region and drain region including at
least one of silicon and germanium.
[0097] Example 36 includes the subject matter of any of Examples
31-35, wherein in addition to the n-type impurity, the source
region and drain region are compositionally different from the
semiconductor body, the source region and drain region further
including at least one of silicon, indium, gallium, arsenic,
antimony, and nitrogen.
[0098] Example 37 includes the subject matter of any of Examples
31-36, wherein the source region and drain region further include
up to 2% tin by atomic percentage.
[0099] Example 38 includes the subject matter of any of Examples
31-37, wherein the layer of insulation material includes silicon
dioxide with carbon concentrations between 5 and 50% by atomic
percentage.
[0100] Example 39 includes the subject matter of any of Examples
31-38, wherein the layer of insulation material includes silicon
nitride.
[0101] Example 40 includes the subject matter of any of Examples
31-39, wherein the layer of insulation material includes hafnium
oxide.
[0102] Example 41 includes the subject matter of any of Examples
31-40, wherein the layer of insulation material includes aluminum
oxide.
[0103] Example 42 includes the subject matter of any of Examples
31-41, wherein the n-type impurity is phosphorous or arsenic.
[0104] Example 43 includes the subject matter of any of Examples
31-42, wherein the thickness of the layer of insulation material is
in the range of 1 nanometer to 5 nanometers, the thickness being
the distance between the STI region and the at least one of the
source region and the drain region.
[0105] Example 44 includes the subject matter of any of Examples
31-43, wherein the layer of insulation material is further between
the STI region and the substrate.
[0106] Example 45 includes the subject matter of any of Examples
31-44, wherein the layer of insulation material includes a chemical
composition that provides surface charge passivation and diffusion
resistance properties.
[0107] Example 46 includes the subject matter of any of Examples
31-45, wherein the semiconductor body is on a fin stub, and the
layer of insulation material is on opposing sidewalls of the fin
stub as well as opposing sidewalls of the semiconductor body.
[0108] Example 47 includes the subject matter of any of Examples
31-46, wherein the at least one of the source region and the drain
region is on the fin stub, and the layer of insulation material is
on opposing sidewalls of the fin stub as well as opposing sidewalls
of the at least one of the source region and the drain region.
[0109] Example 48 includes the subject matter of any of Examples
31-47, wherein the fin stub is part of an underlying semiconductor
substrate.
[0110] Example 49 includes the subject matter of any of Examples
31-48, wherein the substrate is silicon and the semiconductor body
includes at least one of germanium, gallium, arsenic, indium,
antimony, and nitrogen.
[0111] Example 50 includes the subject matter of any of Examples
31-49, wherein the at least one of the source region and the drain
region extends above an uppermost surface of the layer of
insulation material.
[0112] Example 51 includes the subject matter of any of Examples
31-50, further comprising interlayer dielectric (ILD) material on
an upper portion of the at least one of the source region and the
drain region.
[0113] Example 52 includes the subject matter of any of Examples
31-51, further comprising a first contact structure in the ILD
material and on the source region, and a second contact structure
in the ILD material and on the drain region.
[0114] Example 53 includes the subject matter of any of Examples
31-52, wherein ILD material is on the uppermost surface of the
layer of insulation material and the STI region.
[0115] Example 54 includes the subject matter of any of Examples
31-53, wherein the semiconductor body is a fin.
[0116] Example 55 includes the subject matter of any of Examples
31-54, wherein the semiconductor body includes one or more
nanowires.
[0117] Example 56 includes the subject matter of any of Examples
31-55, wherein the semiconductor body includes one or more
nanoribbons.
[0118] Example 57 includes the subject matter of any of Examples
31-56, wherein at least one of the gate dielectric and the gate
electrode is on an uppermost surface of the layer of insulation
material.
[0119] Example 58 includes the subject matter of any of Examples
31-57, wherein the gate structure further includes a first gate
spacer between the source region and the gate electrode, and a
second gate spacer between the drain region and the gate
electrode.
[0120] Example 59 includes the subject matter of any of Examples
31-58, wherein at least one of the first gate spacer and the second
gate spacer is on an uppermost surface of the layer of insulation
material.
[0121] Example 60 includes the subject matter of any of Examples
31-59, further comprising depositing the layer of insulation
material using one of chemical vapor deposition (CVD), atomic layer
deposition (ALD), or physical vapor deposition (PVD)
techniques.
[0122] The terms and expressions which have been employed herein
are used as terms of description and not of limitation, and there
is no intention, in the use of such terms and expressions, of
excluding any equivalents of the features shown and described (or
portions thereof), and it is recognized that various modifications
are possible within the scope of the claims. Accordingly, the
claims are intended to cover all such equivalents. Various
features, aspects, and embodiments have been described herein. The
features, aspects, and embodiments are susceptible to combination
with one another as well as to variation and modification, as will
be appreciated in light of this disclosure. The present disclosure
should, therefore, be considered to encompass such combinations,
variations, and modifications. It is intended that the scope of the
present disclosure be limited not be this detailed description, but
rather by the claims appended hereto. Future filed applications
claiming priority to this application may claim the disclosed
subject matter in a different manner, and may generally include any
set of one or more elements as variously disclosed or otherwise
demonstrated herein.
* * * * *