U.S. patent application number 14/164555 was filed with the patent office on 2014-07-24 for adhesion layer and multiphase ultra-low k dielectric material.
This patent application is currently assigned to International Business Machines Corporation. The applicant listed for this patent is International Business Machines Corporation. Invention is credited to ALFRED GRILL, THOMAS JASPER HAIGH, KELLY MALONE, SON VAN NGUYEN, VISHNUBHAI VITTHALBHAI PATEL, HOSADURGA SHOBHA.
Application Number | 20140203336 14/164555 |
Document ID | / |
Family ID | 47712025 |
Filed Date | 2014-07-24 |
United States Patent
Application |
20140203336 |
Kind Code |
A1 |
GRILL; ALFRED ; et
al. |
July 24, 2014 |
ADHESION LAYER AND MULTIPHASE ULTRA-LOW k DIELECTRIC MATERIAL
Abstract
A dielectric material incorporating a graded carbon adhesion
layer whereby the content of C increases with layer thickness and a
multiphase ultra low k dielectric comprising a porous SiCOH
dielectric material having a k less than 2.7 and a modulus of
elasticity greater than 7 GPa is described. A semiconductor
integrated circuit incorporating the above dielectric material in
interconnect wiring is described and a semiconductor integrated
circuit incorporating the above multiphase ultra low k dielectric
in a gate stack spacer of a FET is described.
Inventors: |
GRILL; ALFRED; (WHITE
PLAINS, NY) ; HAIGH; THOMAS JASPER; (CLAVERACK,
NY) ; MALONE; KELLY; (NEWBURGH, NY) ; NGUYEN;
SON VAN; (SCHENECTADY, NY) ; PATEL; VISHNUBHAI
VITTHALBHAI; (YORKTOWN HEIGHTS, NY) ; SHOBHA;
HOSADURGA; (NISKAYUNA, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
47712025 |
Appl. No.: |
14/164555 |
Filed: |
January 27, 2014 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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13214157 |
Aug 19, 2011 |
8637412 |
|
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14164555 |
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Current U.S.
Class: |
257/288 ;
257/734; 428/448 |
Current CPC
Class: |
H01L 21/02274 20130101;
H01L 21/76829 20130101; C08J 9/26 20130101; H01L 2924/0002
20130101; H01L 21/02304 20130101; H01L 21/02126 20130101; H01L
21/02348 20130101; H01L 2924/00 20130101; H01L 21/76801 20130101;
C08J 2201/042 20130101; C08J 2383/04 20130101; H01L 29/515
20130101; H01L 21/02203 20130101; H01L 21/76832 20130101; H01L
21/02351 20130101; H01L 23/5329 20130101; H01L 21/76825 20130101;
H01L 29/511 20130101; H01L 21/02216 20130101; H01L 21/02337
20130101; H01L 2924/0002 20130101 |
Class at
Publication: |
257/288 ;
257/734; 428/448 |
International
Class: |
H01L 29/51 20060101
H01L029/51; H01L 23/532 20060101 H01L023/532 |
Claims
1-25. (canceled)
26. A dielectric material having a first graded dielectric layer of
silicon oxide and organo-silicon where a content of C increases
with thickness and a second porous SiCOH layer having a
tri-dimensional random covalently bond network of Si--O, Si--C,
Si--CH.sub.2--Si, C--O, Si--H, and C--H bonds, said second porous
SiCOH layer having a dielectric constant k lower than 2.7 and a
modulus of elasticity greater than 7 GPa.
27. The dielectric material of claim 26 wherein said content C in
said first graded dielectric layer increases with thickness to
above 30 percent.
28. The dielectric material of claim 26 wherein said content C in
said first graded dielectric layer increases with thickness from 0
percent to above 30 percent.
29. The dielectric material of claim 26 wherein said first graded
dielectric layer thickness is in the range from 3 nm to 7 nm.
30. The dielectric material of claim 26 wherein said first graded
dielectric layer is formed on a substrate, said substrate selected
from the group consisting of a semiconductor, an insulator, a metal
and combinations thereof.
31. The dielectric material of claim 26 wherein said second porous
SiCOH dielectric layer has a dielectric constant k lower than 2.5
and a modulus of elasticity greater than 6 GPa.
32. The dielectric material of claim 26 wherein said second porous
SiCOH dielectric layer has a porosity greater than 13.8
percent.
33. The dielectric material of claim 26 further comprising
Si--(CH.sub.2).sub.n--Si bonds.
34. A semiconductor integrated circuit comprising an interconnect
wiring having a dielectric material having a first graded
dielectric layer of silicon oxide and organo-silicon where a
content of C increases with thickness and a second porous SiCOH
layer having a tri-dimensional random covalently bond network
having a dielectric constant k lower than 2.7 and a modulus of
elasticity greater than 7 GPa.
35. The semiconductor integrated circuit of claim 34 wherein said
content C in said first graded dielectric layer increases with
thickness to above 30 percent.
36. The semiconductor integrated circuit of claim 34 wherein said
content C in said first graded dielectric layer increases with
thickness from 0 percent to above 30 percent.
37. The semiconductor integrated circuit of claim 34 wherein said
first graded dielectric layer thickness is in the range from 3 nm
to 7 nm.
38. The semiconductor integrated circuit of claim 34 wherein said
first graded dielectric layer is formed on a substrate, said
substrate selected from the group consisting of a semiconductor, an
insulator, a metal and combinations thereof.
39. The semiconductor integrated circuit of claim 34 wherein said
second porous SiCOH dielectric layer has a dielectric constant k
lower than 2.5 and a modulus of elasticity greater than 6 GPa.
40. The semiconductor integrated circuit of claim 34 wherein said
second porous SiCOH dielectric layer has a porosity greater than
13.8 percent.
41. A semiconductor integrated circuit comprising a FET having a
gate stack spacer including a first porous SiCOH dielectric
material having a tri-dimensional random covalently bond network
having a dielectric constant k lower than 2.7 and a modulus of
elasticity greater than 7 GPa.
42. The semiconductor integrated circuit of claim 41 wherein said
first porous SiCOH dielectric material has a dielectric constant k
lower than 2.5 and a modulus of elasticity greater than 6 GPa.
43. The semiconductor integrated circuit of claim 41 further
including a second dielectric material having a first graded
dielectric layer of silicon oxide and organo-silicon where a
content of C increases with thickness.
44. The semiconductor integrated circuit of claim 41 wherein said
second dielectric material is positioned between a third material
and said first material to provide adhesion.
Description
BACKGROUND
[0001] The present invention relates to a process to form
multiphase ultra low k dielectric material and more particularly to
a plasma enhanced chemical vapor deposition (PECVD) process to form
porous SiCOH and to a dielectric material having a k lower than 2.7
and a modulus of elasticity greater than 7 GPa.
BRIEF SUMMARY OF THE INVENTION
[0002] In accordance with the present invention, a method for
forming an ultra low k dielectric layer comprising selecting a
plasma enhanced chemical vapor deposition chamber; placing a
substrate in the chamber; introducing an organo-silicon precursor
including an organic porogen into the chamber; heating the
substrate to a temperature in the range from 200.degree. C. to
350.degree. C.; controlling the amount of an oxidant gas in the
chamber; forming a deposited layer by applying a high frequency
radio frequency power in the chamber to initiate a plasma and
polymerization of the organo-silicon precursor and retain at least
a fraction of the organic porogen in the deposited layer; after a
period of time terminating the plasma in the chamber; and applying
to the deposited layer an energy post treatment selected from the
group consisting of thermal anneal, ultra violet (UV) radiation,
and electron beam irradiation to drive out the organic porogen and
increase the porosity in the deposited layer to at least five
percent.
[0003] The invention further provides a porous SiCOH dielectric
material having a tri-dimensional random covalently bond network of
Si--O, Si--C, Si--CH.sub.2--Si, C--O, Si--H and C--H bonds, a
dielectric constant k lower than 2.7 and a modulus of elasticity
greater than 7 GPa.
[0004] The invention further provides a semiconductor integrated
circuit comprising in its interconnect wiring having a porous SiCOH
dielectric material having a tri-dimensional random covalently bond
network having a dielectric constant k lower than 2.7 and a modulus
of elasticity greater than 7 GPa.
[0005] The invention further provides a semiconductor integrated
circuit comprising a FET having a gate stack spacer including a
porous SiCOH dielectric material having a tri-dimensional random
covalently bond network having a dielectric constant k lower than
2.7 and a modulus of elasticity greater than 7 GPa.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0006] These and other features, objects, and advantages of the
present invention will become apparent upon consideration of the
following detailed description of the invention when read in
conjunction with the drawing in which:
[0007] FIG. 1 is a cross-section view of one embodiment of the
invention showing an adhesion layer and a dielectric layer.
[0008] FIG. 2 is a cross-section diagram illustrating the structure
of FIG. 1.
[0009] FIG. 3 is a graph of Fourier Transform Infrared (FTIR)
spectrum obtained from an as-deposited multiphase porous SiCOH film
in which the marked absorbance peak at 1358 cm.sup.-1 of
Si--CH.sub.2--Si bonds is noted.
[0010] FIG. 4 is a graph of FTIR spectrum obtained from the same
film referred to in FIG. 3 after the as-deposited film is subjected
to an energy post treatment with ultra violet (UV) radiation in
which the marked absorbance peak at 1359 cm.sup.-1 of
Si--CH.sub.2--Si bonds is noted
[0011] FIG. 5 is a graph of FTIR spectrum obtained from a
multiphase porous SiCOH film having an energy post treatment with
ultra violet (UV) radiation in which the marked increase in
absorbance peak intensity at 1357 cm.sup.--1 of Si--CH.sub.2--Si
bonds is noted.
[0012] FIGS. 6-8 show enlarged portions of FIG. 5 with changes in
the scale of the abscissa and the ordinate.
[0013] FIG. 9 is a graph of the absolute breakdown field as a
function of percent occurrence of an embodiment of the
invention.
[0014] FIG. 10 is a graph of the current leakage as a function of
the electric field of an embodiment of the invention.
[0015] FIG. 11 is a cross-section diagram of another embodiment of
the invention showing a dielectric layer incorporated in several
interconnect levels in a semiconductor chip.
[0016] FIG. 12 is a cross-section diagram of yet another embodiment
of the invention showing a dielectric spacer adjacent each side of
a gate stack of a field effect transistor.
DETAILED DESCRIPTION
[0017] Referring now to the drawing, FIG. 1 shows a cross-section
view of a first embodiment of the invention showing a silicon
substrate 12, a graded dielectric layer 16 and a dielectric layer
18. Graded dielectric layer 16 is formed on upper surface 13 of
silicon substrate 12. Upper surface 13 of silicon substrate 12 may
contain 0.78 nm of native oxide and will be considered to be part
of silicon substrate 12. Dielectric layer 18 is formed on upper
surface 17 of graded dielectric layer 16. Graded dielectric layer
16 may have a thickness of 4.71 nm at the location shown by arrow
22. Graded dielectric layer 16 may have a thickness in the range
from 3 to 7 nm or less. Dielectric layer 18 may have a thickness in
the range from 1 nm to 400 nm.
[0018] FIG. 2 is a cross-section diagram illustrating the structure
of FIG. 1. Graded dielectric layer 16 functions as an adhesion
layer on silicon substrate 12. Silicon substrate 12 may be replaced
with a semiconductor, insulator, metal or combinations thereof.
Graded dielectric layer 16 may be formed in a plasma enhanced
chemical vacuum deposition (PECVD) chamber by initially introducing
a silicon oxide precursor alone followed by concurrently
introducing an organo-silicon precursor while reducing the flow of
silicon oxide precursor over time to zero. Graded dielectric layer
16 has a carbon content starting at zero and which increases with
depth. The carbon content of graded dielectric layer 16 may be
above 30 percent to a high of 37.7 percent as-deposited. The carbon
content maximum of graded dielectric layer 16 may be reduced to
31.3 percent during an energy post treatment.
[0019] Dielectric layer 18 may be formed in a PECVD chamber by
placing a substrate in the chamber and introducing an
organo-silicon precursor including an organic porogen into the
chamber. The organo-silicon precursor introduced may be a single
organo-silicon precursor. An organo-silicon precursor may be
selected from the group consisting of octamethylcyclotetrasiloxane
(OMCTS) and 1,3,5,7-tetraoctamethylcyclotetrasiloxane (TMCTS),
diethoxymethylsilane (DEMS), diethyldimethoxysilane (DMDMOS,
diethyldimethoxysilane (DEDMOS), other cyclic and non-cyclic
silanes, and other cyclic and non-cyclic siloxanes. The pressure in
the chamber is controlled to be in the range from 5 to 9 Torr. and
preferably about 7 Torr. Substrate 12 may be heated to a
temperature in the range from 200.degree. C. to 350.degree. C. and
preferably heating only in the range from 200.degree. C. to
250.degree. C. The flow of an oxidant gas into the chamber is
controlled and may be reduced to zero after graded dielectric layer
16 is formed and prior to forming dielectric layer 18. The oxidant
gas may be selected from the group consisting of O.sub.2, H.sub.2O,
CH.sub.3OH, and C.sub.4H.sub.10O. Other gas that may be introduced
into the chamber may be inert Ar, a reactive oxygenated gas and an
oxygenated hydrocarbon gas. Dielectric layer 18 may have a
tri-dimensional random covalently bond network of Si--O, Si--C,
Si--CH.sub.2--Si, C--O, Si--H and C--H bonds, a dielectric constant
k lower than 2.7 and a modulus of elasticity greater than 7 GPa or
a dielectric constant k lower than 2.6 and a modulus of elasticity
greater than 6 GPa. The modulus of elasticity in dielectric layer
18 is uniform in all directions or isotropic.
[0020] Dielectric layer 18 may be formed by applying high frequency
radio frequency power in the PECVD chamber just above the plasma
initiation power level. The high frequency power may be at or
greater than 400 kHz and the radio frequency power may be at or
greater than 13.56 MHz. The power just above the plasma initiation
power level is typically a power increase above plasma initiation
in the range from 75 to 800 watts for a 300 mm radius substrate in
a Plasma CVD chamber and preferable in the range from 150 to 450
watts for a 300 mm radius substrate in a Plasma CVD chamber to
maintain a stable plasma at minimum power. By setting the high
frequency radio frequency power just above plasma initiation, an
increase in polymerization occurs and an increase in retention of
an organic porogen in the deposited dielectric layer occurs.
Further, minimum plasma dissociation of an organic functional group
occurs in the plasma and cross-linking of large molecules occur to
form a deposited dielectric layer with a high degree of porosity in
the range from 5 to 16.5 percent after an energy post
treatment.
[0021] The growth of dielectric layer 18 is stopped or terminated
by lowering the high frequency radio frequency power in the PECVD
chamber until the plasma terminates. The as-deposited dielectric
layer 18 may have a dielectric constant in the range from 2.63 to
2.65, a porosity in the range from 5.5 to 8.5 percent, a pore
diameter in the range from 1 to 1.2 nm, a modulus of elasticity in
the range from 1.18 to 6.3 GPa, a hardness in the range from 0.28
to 0.59, a carbon content in the range from 37.7 to 32.5 atomic
percent, an oxygen content in the range from 29.6 to 32.4 atomic
percent, a silicon content in the range from 32.8 to 34.9 atomic
percent, a stress in the range from 19 to 40 MPa and a ratio of
stress/modulus of elasticity in the range from 16.1 to 15.5. The
organo-silicon precursor for the dielectric layer measured to
obtain the above data was octamethylcyclotetrasiloxane (OMCTS) with
the optional addition of an oxygen oxidant source (i.e.
O.sub.2/N.sub.2O). The measurements were made from dielectric
layers made at substrate temperatures of 250.degree. C.,
280.degree. C., 300.degree. C. and 350.degree. C.
[0022] The as-deposited dielectric layer 18 may be subjected to an
energy post treatment of ultra violet radiation for a time period
of 300 sec at a dielectric layer temperature above 200.degree. C.
to increase Si--CH.sub.2--Si cross linking bonds in dielectric
layer 18. Dielectric layer 18 typically has two adjacent
Si--CH.sub.3 + Si--CH.sub.3 chemical bonds in the deposited
dielectric layer which change to Si--CH.sub.2--Si bonds to increase
the modulus of elasticity and hardness of dielectric layer 18 and
outgas of volatile CH.sub.4 to create additional pores in deposited
dielectric layer 18. The energy post treatment thermal anneal may
include heating the as-deposited dielectric layer 18 to a
temperature in the range from 200.degree. C. to 430.degree. C. in
an ambient of forming gas (H.sub.2 and N.sub.2) for a period of
time greater than 40 minutes.
[0023] The as-deposited dielectric layer 18 characteristics for the
dielectric layer described above change after an energy post
treatment of ultra violet radiation for a time period of 300 sec at
a temperature above 200.degree. C. The wavelength of UV may be a
narrow spectrum or a broad spectrum. Certain wavelengths of UV
enhance specific reactions. Dielectric layer 18 after the energy
post treatment has a dielectric constant in the range from 2.39 to
2.60, a porosity in the range from 13.8 to 16.6 percent, a pore
diameter in the range from 0.8 to 1.0 nm, a modulus of elasticity
in the range from 4.92 to 13.83 GPa, a hardness in the range from
1.27 to 1.75, a carbon content in the range from 31.3 to 32.3
atomic percent, an oxygen content in the range from 33.7 to 34.4
atomic percent, a silicon content in the range from 34.4 to 35.2
atomic percent, a stress in the range from 73 to 110 MPa and a
ratio of stress/modulus of elasticity in the range from 6.8 to
16.9.
[0024] Other energy post treatment besides UV radiation may be
thermal anneal and electron beam (EB) irradiation. Thermal anneal
treatment is especially applicable where dielectric layer 18 is
vertical such as if used as a gate stack sidewall spacer on a field
effect transistor or if portions of the layer are vertical and
other portions are horizontal. UV radiation and EB irradiation may
provide an uneven exposure to a vertical dielectric layer. Energy
post treatment functions to drive out the organic porogen and to
increase the porosity in the deposited dielectric layer 18.
Dielectric layer 18 may have a dielectric constant lower than 2.7
and a modulus of elasticity greater than 7 GPa or greater than 8
GPa or a dielectric constant lower than 2.5 and a modulus of
elasticity greater than 6 GPa.
[0025] FIG. 3 is a graph of Fourier Transform Infrared (FTIR)
spectrum shown by curve 33 obtained from an as-deposited dielectric
layer 18 where the organo-silicon precursor was
octamethylcyclotetrasiloxane (OMCTS). In FIG. 3 the ordinate
represents Absorbance and the abscissa represents Wavenumbers
(cm.sup.-1). The spectrum displays a strong Si--O absorption band
34 at 975-1200 cm.sup.-1 with an absorbance of 0.274, a
Si--CH.sub.3 absorption peak 36 at 1271 cm.sup.-1 with an
absorbance of 0.093, a Si--H absorption band 38 at 2146-2230
cm.sup.--1 with an absorbance of 0.02, and small C--H absorption
peaks 40, 41 and 42 at 2875-2990 cm.sup.--1 with a respective
absorbance of 0.008, 0.012 and 0.037. The marked absorbance peak 37
at 1358 cm.sup.-1 of Si--CH.sub.2--Si is shown with an absorbance
of 0.005.
[0026] FIG. 4 is a graph of Fourier Transform Infrared (FTIR)
spectrum shown by curve 53 obtained from the as-deposited
dielectric layer 18 measured in FIG. 3 after energy post treatment.
In FIG. 4 the ordinate represents Absorbance and the abscissa
represents Wavenumbers (cm.sup.-1). The spectrum displays a strong
Si--O absorption band 54 at 975-1200 cm.sup.-1 with an absorbance
of 0.249, a Si--CH.sub.3 absorption peak 56 at 1271 cm.sup.-1 with
an absorbance of 0.06, a Si--H absorption band 58 at 2146-2230
cm.sup.-1 with an absorbance of 0.008, and small C-H absorption
peaks 60, 61 and 62 at 2875-2990 cm.sup.-1 with a respective
absorbance of 0.006, 0.008 and 0.02.
[0027] The marked absorption peak 57 at 1359 cm.sup.-1 of
Si--CH.sub.2--Si is shown with an absorbance of 0.0075.
[0028] In FIG. 4, S--O absorption band 54 at 975-1200 cm.sup.-1 is
90.9 percent of absorption band 34 in FIG. 3. Si--CH.sub.3
absorption peak 56 at 1271 cm.sup.-1is 64.5 percent of absorption
peak 36 in FIG. 3. Si--H absorption band 58 at 2146-2230
cm.sup.-1is 40 percent of absorption band 38 in FIG. 3. C--H
absorption peaks 60', 61 and 62 at 2875-2990 cm.sup.-1 are 75
percent, 66.6 percent and 54.1 percent respectively of absorption
peaks 40, 41 and 42 in FIG. 3. The Si--H.sub.2--Si absorption band
57 at 1359 cm.sup.-1in FIG. 4 is 150 percent of the absorption band
37 at 1358 cm.sup.-1in FIG. 3.
[0029] FIG. 5 is a graph of FTIR spectrum obtained from an
as-deposited dielectric layer 18 shown by curve 60 and from
dielectric layer 18 after being cured by undergoing an energy post
treatment with ultra violet radiation shown by curve 64. In FIG. 5
the ordinate represents Absorbance and the abscissa represents
Wavenumbers (cm.sup.-1). Dielectric layer 18 was formed from an
organo-silicon precursor OMCTS deposited at 250.degree. C.
[0030] In FIG. 5, curves 60 and 64 have overlapping absorbance
peaks but the amplitudes at particular peaks are different. In FIG.
5, wavenumber 800 shows an absorbance peak which corresponds to
Si--Me.sub.2 Wavenumber 844 shows an absorbance peak which
corresponds to O--Si--H. Wavenumber 1263 shows an absorbance peak
which corresponds to Si--Me.sub.2 Wavenumber 1357 shows an
absorbance peak which corresponds to Si--CH.sub.2--Si. The marked
increase of the absorption peak at wavenumber 1357 of
Si--CH.sub.2--Si after energy post treatment with UV radiation is
shown. Wavenumber 1410 shows an absorbance peak which corresponds
to Si--Me.sub.x Wavenumber 2143 shows an absorbance peak which
corresponds to Si--H.sub.. Wavenumber 2963 shows an absorbance peak
which corresponds to CH.sub.3. Wavenumber 3730 shows an absorbance
peak which corresponds to O--H.
[0031] FIGS. 6-8 show enlarged portions of FIG. 5 with changes in
the scale of the abscissa and the ordinate. FIGS. 6-8 show the
amplitude of absorbance peaks of curves 60 and 64 at the same
wavenumber. In FIG. 6, wavenumber 2963 corresponding to CH.sub.3
shows curve 60 has an amplitude of 0.0236 and curve 64 has an
amplitude of 0.0135 which is a reduction of 57.2 percent. In FIG.
7, wavenumber 800 corresponding to Si--Me.sub.2 shows curve 60 has
an amplitude of 0.082 and curve 64 has an amplitude of 0.057 which
is a reduction of 69.5 percent. In FIG. 7, wavenumber 1263
corresponding to Si--Me.sub.2 shows curve 60 has an amplitude of
0.06 and curve 64 has an amplitude of 0.035 which is a reduction of
58.3 percent. In FIG. 8, wavenumber 1357 corresponding to
Si--CH.sub.2--Si shows curve 60 has an amplitude of 0.001 and curve
64 has an amplitude of 0.0024 which is an increase of 240 percent.
This indicates an increase of 240 percent in Si--CH.sub.2--Si after
energy post treatment UV radiation. It should also be noted that
the low vibrational intensity of Si--CH.sub.2--Si is due to the
strong bonding of CH.sub.2 to two Si atoms. Also in FIG. 8,
wavenumber 1410 corresponding to Si--Me.sub.x shows curve 60 has an
amplitude of 0.0375 and curve 64 has an amplitude of 0.0025 which
is a reduction of 58.3 percent. The increase in Si--CH.sub.2--Si
after energy post treatment is shown in FIG. 8 by an increase in
wavenumber 1357 peak absorbance amplitude of 240 percent. The 240
percent increase, improves the modulus of elasticity and hardness
of dielectric layer 18. Energy post treatment with ultra violet
radiation results in removal or reduction of CH.sub.3 as shown in
FIG. 6 and results in removal or reduction of Si--Me.sub.2 as shown
in FIG. 7 from dielectric layer 18.
[0032] FIG. 9 is a graph showing curves 74 and 76 of the absolute
breakdown field as a function of percent occurrence of dielectric
layer 18. Dielectric layer 18 was made with OMCTS as the
organo-silicon precursor. In FIG. 9, the ordinate represents
Percent Occurrence and the abscissa represents Absolute Breakdown
Field (MV/cm). Curve 74 was measured from an as-deposited
dielectric layer 18 with the lowest breakdown electric field being
at about 7.75 MV/cm. Curve 76 was measured from a dielectric layer
18 after energy post treatment with UV radiation.
[0033] FIG. 10 is a graph showing curves 84 and 86 of the Current
Leakage as a function of Electric Field of dielectric layer 18.
Dielectric layer 18 was made with OMCTS as the organo-silicon
precursor. In FIG. 10, the ordinate represents Current J
(Amps/cm.sup.2) and the abscissa represents Electric Field (MV/cm).
Curve 84 was measured at 150.degree. C. from an as-deposited
dielectric layer 18. Curve 86 was measured at 150.degree. C. from a
dielectric layer 18 after energy post treatment with UV
radiation.
[0034] FIG. 11 is a cross section diagram of another embodiment of
the invention showing a back end of the line (BEOL) structure for
making interconnections on a semiconductor chip to devices such as
FET's. Semiconductor substrate 92 may be a silicon containing
substrate containing devices (not shown) and vias (not shown). A
first interconnect level with metal wiring 94 and 95 is formed in
dielectric layer 98 over upper surface 93 of substrate 92 using a
damascene process. A dielectric cap layer 99 is formed over the
upper surface 102 of metal wiring 94 and 95 and upper surface 103
of dielectric layer 98.
[0035] A second interconnect level comprises graded dielectric
layer 106, vias 108 and 110, dielectric layer 112, metal wiring 114
and 115 and dielectric cap layer 118. Graded dielectric layer 106
functions to provide adhesion to upper surface 104 of dielectric
cap layer 99. Dielectric cap layer 99 functions to provide a
diffusion barrier to metal from the upper surface of metal wiring
94 and 95.
[0036] A third interconnect level comprises graded dielectric layer
126, via 128, dielectric layer 132 and metal wiring 134 and 135.
Graded dielectric layer 126 functions to provide adhesion to upper
surface 124 of dielectric cap layer 118.
[0037] FIG. 12 is a cross section diagram of another embodiment of
the invention showing field effect transistor 140 on
silicon-on-insulator (SOI) substrate 142. Silicon-on-insulator 142
comprises insulating layer 144 and silicon containing layer 146.
Shallow trench isolation regions 148 and 150 electrically isolate
silicon region 152 in which FET 140 is formed. Silicon region 152
has source region 156 and drain region 158. Gate dielectric 160 is
formed on the upper surface of silicon region 152 in the area
between source region 156 and drain region 158. Gate electrode 164
is formed over gate dielectric 160 which may be a semiconductor or
metal. A metal gate electrode 166 is formed over gate electrode
164. Sidewall spacers 168 and 170 are formed on the sidewalls of
gate electrode 166 and gate electrode 164. Sidewall spacers 168 and
170 may use dielectric layer 18 disclosed above. A dielectric layer
176 is formed over upper surface 159, sidewall spacers 168 and 170,
and gate electrode 166. Vias 178 and 180 formed through dielectric
layer 176 to source region 156 and drain region 158 provide
electrical contact.
[0038] In FIGS. 2-12, like references are used for functions or
apparatus corresponding to the functions or apparatus of a lower
numbered figure.
[0039] While there has been described and illustrated a method for
forming an ultra low k dielectric layer and a dielectric with k
below 2.7 and a modulus of elasticity greater than 7 GPa, it will
be apparent to those skilled in the art that modifications and
variations are possible without deviating from the broad scope of
the invention which shall be limited solely by the scope of the
claims appended hereto.
* * * * *