U.S. patent application number 13/944825 was filed with the patent office on 2013-11-14 for semiconductor device and method of forming interposer with opening to contain semiconductor die.
The applicant listed for this patent is STATS ChipPAC, Ltd.. Invention is credited to HeeJo Chi, Jun Mo Koo, Yaojian Lin, Reza A. Pagaila.
Application Number | 20130299982 13/944825 |
Document ID | / |
Family ID | 43755915 |
Filed Date | 2013-11-14 |
United States Patent
Application |
20130299982 |
Kind Code |
A1 |
Pagaila; Reza A. ; et
al. |
November 14, 2013 |
Semiconductor Device and Method of Forming Interposer with Opening
to Contain Semiconductor Die
Abstract
A semiconductor device has an interposer mounted over a carrier.
The interposer includes TSV formed either prior to or after
mounting to the carrier. An opening is formed in the interposer.
The interposer can have two-level stepped portions with a first
vertical conduction path through a first stepped portion and second
vertical conduction path through a second stepped portion. A first
and second semiconductor die are mounted over the interposer. The
second die is disposed within the opening of the interposer. A
discrete semiconductor component can be mounted over the
interposer. A conductive via can be formed through the second die
or encapsulant. An encapsulant is deposited over the first and
second die and interposer. A portion of the interposer can be
removed to that the encapsulant forms around a side of the
semiconductor device. An interconnect structure is formed over the
interposer and second die.
Inventors: |
Pagaila; Reza A.;
(Tangerang, ID) ; Lin; Yaojian; (Singapore,
SG) ; Koo; Jun Mo; (Singapore, SG) ; Chi;
HeeJo; (Kyoungki-do, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
STATS ChipPAC, Ltd. |
Singapore |
|
SG |
|
|
Family ID: |
43755915 |
Appl. No.: |
13/944825 |
Filed: |
July 17, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12714190 |
Feb 26, 2010 |
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13944825 |
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|
12565380 |
Sep 23, 2009 |
8143097 |
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12714190 |
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Current U.S.
Class: |
257/738 ;
257/773; 438/124 |
Current CPC
Class: |
H01L 2224/812 20130101;
H01L 2924/01047 20130101; H01L 2924/181 20130101; H01L 2924/3025
20130101; H01L 21/56 20130101; H01L 2924/09701 20130101; H01L
2224/32145 20130101; H01L 2924/01073 20130101; H01L 21/568
20130101; H01L 2924/01005 20130101; H01L 2924/15151 20130101; H01L
2924/15331 20130101; H01L 2224/16146 20130101; H01L 2924/13091
20130101; H01L 24/29 20130101; H01L 2224/48091 20130101; H01L
2924/0002 20130101; H01L 2924/15311 20130101; H01L 25/105 20130101;
H01L 2224/81001 20130101; H01L 2924/1306 20130101; H01L 2224/48091
20130101; H01L 24/48 20130101; H01L 2924/00014 20130101; H01L
2924/01029 20130101; H01L 2924/19041 20130101; H01L 2924/19105
20130101; H01L 2224/73265 20130101; H01L 24/81 20130101; H01L
2224/97 20130101; H01L 2924/00014 20130101; H01L 2924/14 20130101;
H01L 24/94 20130101; H01L 2224/45015 20130101; H01L 2224/48157
20130101; H01L 2224/4816 20130101; H01L 2225/06517 20130101; H01L
2924/01004 20130101; H01L 2224/81801 20130101; H01L 2924/0103
20130101; H01L 23/49816 20130101; H01L 25/0657 20130101; H01L 25/16
20130101; H01L 2224/16225 20130101; H01L 2924/00014 20130101; H01L
2924/1306 20130101; H01L 24/32 20130101; H01L 2924/14 20130101;
H01L 2924/30105 20130101; H01L 24/16 20130101; H01L 21/6835
20130101; H01L 2224/73259 20130101; H01L 2924/01074 20130101; H01L
2924/01322 20130101; H01L 2924/157 20130101; H01L 2224/48158
20130101; H01L 24/92 20130101; H01L 2924/15174 20130101; H01L
2221/68345 20130101; H01L 2924/01006 20130101; H01L 2924/014
20130101; H01L 2924/01078 20130101; H01L 2224/05552 20130101; H01L
23/3128 20130101; H01L 2224/83 20130101; H01L 23/552 20130101; H01L
24/97 20130101; H01L 2924/01082 20130101; H01L 2224/04105 20130101;
H01L 2224/0401 20130101; H01L 24/83 20130101; H01L 2224/0557
20130101; H01L 2224/16225 20130101; H01L 2924/01079 20130101; H01L
23/13 20130101; H01L 2224/73253 20130101; H01L 2924/0105 20130101;
H01L 2924/12044 20130101; H01L 2224/16145 20130101; H01L 2224/73203
20130101; H01L 2225/06541 20130101; H01L 2924/01049 20130101; H01L
2924/12042 20130101; H01L 2924/1532 20130101; H01L 2924/18161
20130101; H01L 2924/3511 20130101; H01L 2924/13091 20130101; H01L
2224/73265 20130101; H01L 2224/05552 20130101; H01L 2924/15311
20130101; H01L 2224/45099 20130101; H01L 2924/00012 20130101; H01L
2924/00 20130101; H01L 2924/00 20130101; H01L 2224/05552 20130101;
H01L 2924/00 20130101; H01L 2924/207 20130101; H01L 2224/45015
20130101; H01L 2924/00014 20130101; H01L 2225/06548 20130101; H01L
2224/12105 20130101; H01L 2924/0002 20130101; H01L 2924/12041
20130101; H01L 2224/97 20130101; H01L 2224/16227 20130101; H01L
2225/06589 20130101; H01L 2924/00014 20130101; H01L 2924/181
20130101; H01L 23/49827 20130101; H01L 2225/06513 20130101; H01L
2924/01019 20130101; H01L 2224/97 20130101; H01L 2224/73267
20130101; H01L 2924/01013 20130101; H01L 2924/12042 20130101; H01L
2924/207 20130101 |
Class at
Publication: |
257/738 ;
438/124; 257/773 |
International
Class: |
H01L 23/498 20060101
H01L023/498; H01L 21/56 20060101 H01L021/56 |
Claims
1. A method of making a semiconductor device, comprising: providing
a carrier; forming an interface layer over the carrier; disposing a
first substrate over the carrier; disposing a second substrate over
the carrier; disposing a first semiconductor die over the first and
second substrates electrically connected to the first and second
substrates; depositing an encapsulant over the first semiconductor
die and over the first and second substrates; and removing the
carrier and interface layer.
2. The method of claim 1, further including forming a plurality of
bumps over the first and second substrates.
3. The method of claim 1, wherein disposing the first and second
substrates includes simultaneously disposing the first and second
substrates over the carrier.
4. The method of claim 1, further including forming an electrical
connection between the first and second substrates.
5. The method of claim 1, further including forming an interconnect
structure over a surface of the first substrate opposite the first
semiconductor die.
6. The method of claim 1, further including disposing a second
semiconductor die over the first substrate.
7. A method of making a semiconductor device, comprising: providing
a first substrate; disposing a second substrate adjacent to the
first substrate; disposing a first semiconductor die over the first
substrate electrically connected to the first substrate; and
depositing an encapsulant over the first semiconductor die and over
the first and second substrates.
8. The method of claim 7, further including forming a bump between
the first semiconductor die and first substrate.
9. The method of claim 7, further including disposing a passive
component over the first or second substrate.
10. The method of claim 7, further including forming an
interconnect structure over a surface of the first substrate
opposite the first semiconductor die.
11. The method of claim 7, further including forming an electrical
connection between the first and second substrates.
12. The method of claim 7, further including forming a bump over a
surface of the first substrate opposite the first semiconductor
die.
13. The method of claim 7, further including disposing a second
semiconductor die over the first semiconductor die.
14. A semiconductor device, comprising: a first substrate; a second
substrate; a first semiconductor die disposed over the first and
second substrates; and an encapsulant deposited over the first
semiconductor die and over the first and second substrates.
15. The semiconductor device of claim 14, further including a bump
formed between the first semiconductor die and the second
substrate.
16. The semiconductor device of claim 14, wherein the first
substrate includes a laminate interposer.
17. The semiconductor device of claim 14, wherein the first
substrate includes a coefficient of thermal expansion (CTE) similar
to a CTE of the semiconductor die.
18. The semiconductor device of claim 14, wherein the first
semiconductor die includes a ball grid array.
19. The semiconductor device of claim 14, further including a
second semiconductor die disposed over the first substrate.
20. A semiconductor device, comprising: a first substrate; a second
substrate; and a first semiconductor die disposed over the first
and second substrates and electrically connected to the first and
second substrates.
21. The semiconductor device of claim 20, further including a
second semiconductor die disposed over the first substrate.
22. The semiconductor device of claim 20, wherein the first
substrate includes a laminate interposer.
23. The semiconductor device of claim 20, wherein the second
substrate includes an insulating layer and a conductive layer.
24. The semiconductor device of claim 20, wherein the first
substrate includes a coefficient of thermal expansion (CTE) similar
to a CTE of the semiconductor die.
25. The semiconductor device of claim 20, further including a
passive component disposed over the first substrate.
Description
CLAIM TO DOMESTIC PRIORITY
[0001] The present application is a continuation of U.S. patent
application Ser. No. 12/714,190, filed Feb. 26, 2010, which is a
continuation-in-part of U.S. patent application Ser. No.
12/565,380, filed Sep. 23, 2009, now U.S. Pat. No. 8,143,097, which
application is incorporated herein by reference.
FIELD OF THE INVENTION
[0002] The present invention relates in general to semiconductor
devices and, more particularly, to a semiconductor device and
method of forming an interposer with an open cavity to contain a
semiconductor die in a wafer level chip scale package.
BACKGROUND OF THE INVENTION
[0003] Semiconductor devices are commonly found in modern
electronic products. Semiconductor devices vary in the number and
density of electrical components. Discrete semiconductor devices
generally contain one type of electrical component, e.g., light
emitting diode (LED), small signal transistor, resistor, capacitor,
inductor, and power metal oxide semiconductor field effect
transistor (MOSFET). Integrated semiconductor devices typically
contain hundreds to millions of electrical components. Examples of
integrated semiconductor devices include microcontrollers,
microprocessors, charged-coupled devices (CCDs), solar cells, and
digital micro-mirror devices (DMDs).
[0004] Semiconductor devices perform a wide range of functions such
as high-speed calculations, transmitting and receiving
electromagnetic signals, controlling electronic devices,
transforming sunlight to electricity, and creating visual
projections for television displays. Semiconductor devices are
found in the fields of entertainment, communications, power
conversion, networks, computers, and consumer products.
Semiconductor devices are also found in military applications,
aviation, automotive, industrial controllers, and office
equipment.
[0005] Semiconductor devices exploit the electrical properties of
semiconductor materials. The atomic structure of semiconductor
material allows its electrical conductivity to be manipulated by
the application of an electric field or base current or through the
process of doping. Doping introduces impurities into the
semiconductor material to manipulate and control the conductivity
of the semiconductor device.
[0006] A semiconductor device contains active and passive
electrical structures. Active structures, including bipolar and
field effect transistors, control the flow of electrical current.
By varying levels of doping and application of an electric field or
base current, the transistor either promotes or restricts the flow
of electrical current. Passive structures, including resistors,
capacitors, and inductors, create a relationship between voltage
and current necessary to perform a variety of electrical functions.
The passive and active structures are electrically connected to
form circuits, which enable the semiconductor device to perform
high-speed calculations and other useful functions.
[0007] Semiconductor devices are generally manufactured using two
complex manufacturing processes, i.e., front-end manufacturing, and
back-end manufacturing, each involving potentially hundreds of
steps. Front-end manufacturing involves the formation of a
plurality of die on the surface of a semiconductor wafer. Each die
is typically identical and contains circuits formed by electrically
connecting active and passive components. Back-end manufacturing
involves singulating individual die from the finished wafer and
packaging the die to provide structural support and environmental
isolation.
[0008] One goal of semiconductor manufacturing is to produce
smaller semiconductor devices. Smaller devices typically consume
less power, have higher performance, and can be produced more
efficiently. In addition, smaller semiconductor devices have a
smaller footprint, which is desirable for smaller end products. A
smaller die size may be achieved by improvements in the front-end
process resulting in die with smaller, higher density active and
passive components. Back-end processes may result in semiconductor
device packages with a smaller footprint by improvements in
electrical interconnection and packaging materials.
[0009] Wafer level chip scale module packages (WLCSMP) and fan-out
wafer level chip scale packages (FO-WLCSP) typically contain
stacked semiconductor die over and between an organic substrate or
interposer for higher device integration. Examples of the WLCSMPs
with upper and lower stacked semiconductor die can be found in U.S.
Pat. Nos. 6,921,968, 5,977,640, and 6,906,415. The lower
semiconductor die is thinner than the organic substrate and thus
contained within the encapsulant. Accordingly, it is difficult to
properly dissipate heat from the lower semiconductor. The fixed
organic substrate requires care when handling to avoid damage to
the thin semiconductor die. In addition, warpage is a recurring
issue due to mismatches in the coefficient of thermal expansion
(CTE) between the upper and lower semiconductor die and organic
substrate.
[0010] In FO-WLCSP, the bumps on the upper semiconductor die are
typically large in diameter with a corresponding high pitch. The
large pitch of upper die bumps limits the ability to mount a
fine-pitch die with high input/output (I/O) count. In addition, the
bump collapse for large balls is difficult to control, particularly
when mounted on adhesive tape or carrier. The bump collapse
increases chances of electrical shorting to adjacent conductive
structures during reflow. The lower semiconductor die is prone to
shifting during encapsulation due to inadequate adhesion between
die and carrier.
SUMMARY OF THE INVENTION
[0011] A need exists for a thinner WLCSP to accommodate a
fine-pitch die with high I/O count. Accordingly, in one embodiment,
the present invention is a method of making a semiconductor device
comprising the steps of providing a carrier, forming an interface
layer over the carrier, disposing a first substrate over the
carrier, disposing a second substrate over the carrier, disposing a
first semiconductor die over the first and second substrates
electrically connected to the first and second substrates,
depositing an encapsulant over the first semiconductor die and over
the first and second substrates, and removing the carrier and
interface layer.
[0012] In another embodiment, the present invention is a method of
making a semiconductor device comprising the steps of providing a
first substrate, disposing a second substrate adjacent to the first
substrate, disposing a first semiconductor die over the first
substrate electrically connected to the first substrate, and
depositing an encapsulant over the first semiconductor die and over
the first and second substrates.
[0013] In another embodiment, the present invention is a
semiconductor device comprising a first substrate and a second
substrate. A first semiconductor die is disposed over the first and
second substrates. An encapsulant is deposited over the first
semiconductor die and over the first and second substrates.
[0014] In another embodiment, the present invention is a
semiconductor device comprising a first substrate and a second
substrate. A first semiconductor die is disposed over the first and
second substrates and electrically connected to the first and
second substrates.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 illustrates a PCB with different types of packages
mounted to its surface;
[0016] FIGS. 2a-2c illustrate further detail of the representative
semiconductor packages mounted to the PCB;
[0017] FIGS. 3a-3i illustrate a process of forming a WLCSMP having
an open cavity for containing a semiconductor die and
interconnected through a TSV interposer;
[0018] FIG. 4 illustrates the WLCSMP with an open cavity containing
the semiconductor die and interconnected through the TSV
interposer;
[0019] FIG. 5 illustrates the TSV interposer with a polymer
insulating layer;
[0020] FIG. 6 illustrates the WLCSMP with a heat spreader and TIM
layer formed over the upper semiconductor die;
[0021] FIG. 7 illustrates the WLCSMP with an EMI and RFI shielding
layer formed over the upper semiconductor die;
[0022] FIG. 8 illustrates the WLCSMP with conductive pillars formed
through the encapsulant;
[0023] FIG. 9 illustrates the WLCSMP with conductive pillars formed
through the encapsulant and conductive layer formed over the
encapsulant;
[0024] FIG. 10 illustrates the WLCSMP with conductive pillars
formed through the encapsulant and interconnect structure formed
over the upper semiconductor die;
[0025] FIG. 11 illustrates the WLCSMP with TSV formed through the
upper semiconductor die and interconnect structure formed over the
upper semiconductor die;
[0026] FIG. 12 illustrates the WLCSMP with TSV formed through the
lower semiconductor die and interconnect structure formed over the
lower semiconductor die;
[0027] FIGS. 13a-13g illustrate a process of forming an interposer
with an opening for containing a semiconductor die;
[0028] FIG. 14 illustrates the FO-WLCSP with interposer having an
opening for containing the semiconductor die;
[0029] FIG. 15 illustrates conductive TSV formed in the lower
semiconductor die;
[0030] FIG. 16 illustrates conductive pillars formed in the
encapsulant around the upper semiconductor die;
[0031] FIG. 17 illustrates the WLCSMP with an EMI and RFI shielding
layer formed over the upper semiconductor die;
[0032] FIG. 18 illustrates a truncated interposer with encapsulant
formed on the sides of the FO-WLCSP;
[0033] FIG. 19 illustrates discrete semiconductor components formed
over the interposer;
[0034] FIG. 20 illustrates two-level stepped interposer with
openings for containing two semiconductor die;
[0035] FIG. 21 illustrates an upper interposer stacked over a lower
interposer with openings for containing two semiconductor die;
and
[0036] FIG. 22 illustrates two-level stepped interposer with
openings for stacking three semiconductor die.
DETAILED DESCRIPTION OF THE DRAWINGS
[0037] The present invention is described in one or more
embodiments in the following description with reference to the
figures, in which like numerals represent the same or similar
elements. While the invention is described in terms of the best
mode for achieving the invention's objectives, it will be
appreciated by those skilled in the art that it is intended to
cover alternatives, modifications, and equivalents as may be
included within the spirit and scope of the invention as defined by
the appended claims and their equivalents as supported by the
following disclosure and drawings.
[0038] Semiconductor devices are generally manufactured using two
complex manufacturing processes: front-end manufacturing and
back-end manufacturing. Front-end manufacturing involves the
formation of a plurality of die on the surface of a semiconductor
wafer. Each die on the wafer contains active and passive electrical
components, which are electrically connected to form functional
electrical circuits. Active electrical components, such as
transistors and diodes, have the ability to control the flow of
electrical current. Passive electrical components, such as
capacitors, inductors, resistors, and transformers, create a
relationship between voltage and current necessary to perform
electrical circuit functions.
[0039] Passive and active components are formed over the surface of
the semiconductor wafer by a series of process steps including
doping, deposition, photolithography, etching, and planarization.
Doping introduces impurities into the semiconductor material by
techniques such as ion implantation or thermal diffusion. The
doping process modifies the electrical conductivity of
semiconductor material in active devices, transforming the
semiconductor material into an insulator, conductor, or dynamically
changing the semiconductor material conductivity in response to an
electric field or base current. Transistors contain regions of
varying types and degrees of doping arranged as necessary to enable
the transistor to promote or restrict the flow of electrical
current upon the application of the electric field or base
current.
[0040] Active and passive components are formed by layers of
materials with different electrical properties. The layers can be
formed by a variety of deposition techniques determined in part by
the type of material being deposited. For example, thin film
deposition may involve chemical vapor deposition (CVD), physical
vapor deposition (PVD), electrolytic plating, and electroless
plating processes. Each layer is generally patterned to form
portions of active components, passive components, or electrical
connections between components.
[0041] The layers can be patterned using photolithography, which
involves the deposition of light sensitive material, e.g.,
photoresist, over the layer to be patterned. A pattern is
transferred from a photomask to the photoresist using light. The
portion of the photoresist pattern subjected to light is removed
using a solvent, exposing portions of the underlying layer to be
patterned. The remainder of the photoresist is removed, leaving
behind a patterned layer. Alternatively, some types of materials
are patterned by directly depositing the material into the areas or
voids formed by a previous deposition/etch process using techniques
such as electroless and electrolytic plating.
[0042] Depositing a thin film of material over an existing pattern
can exaggerate the underlying pattern and create a non-uniformly
flat surface. A uniformly flat surface is required to produce
smaller and more densely packed active and passive components.
Planarization can be used to remove material from the surface of
the wafer and produce a uniformly flat surface. Planarization
involves polishing the surface of the wafer with a polishing pad.
An abrasive material and corrosive chemical are added to the
surface of the wafer during polishing. The combined mechanical
action of the abrasive and corrosive action of the chemical removes
any irregular topography, resulting in a uniformly flat
surface.
[0043] Back-end manufacturing refers to cutting or singulating the
finished wafer into the individual die and then packaging the die
for structural support and environmental isolation. To singulate
the die, the wafer is scored and broken along non-functional
regions of the wafer called saw streets or scribes. The wafer is
singulated using a laser cutting tool or saw blade. After
singulation, the individual die are mounted to a package substrate
that includes pins or contact pads for interconnection with other
system components. Contact pads formed over the semiconductor die
are then connected to contact pads within the package. The
electrical connections can be made with solder bumps, stud bumps,
conductive paste, or wirebonds. An encapsulant or other molding
material is deposited over the package to provide physical support
and electrical isolation. The finished package is then inserted
into an electrical system and the functionality of the
semiconductor device is made available to the other system
components.
[0044] FIG. 1 illustrates electronic device 50 having a chip
carrier substrate or printed circuit board (PCB) 52 with a
plurality of semiconductor packages mounted on its surface.
Electronic device 50 may have one type of semiconductor package, or
multiple types of semiconductor packages, depending on the
application. The different types of semiconductor packages are
shown in FIG. 1 for purposes of illustration.
[0045] Electronic device 50 may be a stand-alone system that uses
the semiconductor packages to perform one or more electrical
functions. Alternatively, electronic device 50 may be a
subcomponent of a larger system. For example, electronic device 50
may be a graphics card, network interface card, or other signal
processing card that can be inserted into a computer. The
semiconductor package can include microprocessors, memories,
application specific integrated circuits (ASIC), logic circuits,
analog circuits, RF circuits, discrete devices, or other
semiconductor die or electrical components.
[0046] In FIG. 1, PCB 52 provides a general substrate for
structural support and electrical interconnect of the semiconductor
packages mounted on the PCB. Conductive signal traces 54 are formed
over a surface or within layers of PCB 52 using evaporation,
electrolytic plating, electroless plating, screen printing, or
other suitable metal deposition process. Signal traces 54 provide
for electrical communication between each of the semiconductor
packages, mounted components, and other external system components.
Traces 54 also provide power and ground connections to each of the
semiconductor packages.
[0047] In some embodiments, a semiconductor device has two
packaging levels. First level packaging is a technique for
mechanically and electrically attaching the semiconductor die to an
intermediate carrier. Second level packaging involves mechanically
and electrically attaching the intermediate carrier to the PCB. In
other embodiments, a semiconductor device may only have the first
level packaging where the die is mechanically and electrically
mounted directly to the PCB.
[0048] For the purpose of illustration, several types of first
level packaging, including wire bond package 56 and flip chip 58,
are shown on PCB 52. Additionally, several types of second level
packaging, including ball grid array (BGA) 60, bump chip carrier
(BCC) 62, dual in-line package (DIP) 64, land grid array (LGA) 66,
multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70,
and quad flat package 72, are shown mounted on PCB 52. Depending
upon the system requirements, any combination of semiconductor
packages, configured with any combination of first and second level
packaging styles, as well as other electronic components, can be
connected to PCB 52. In some embodiments, electronic device 50
includes a single attached semiconductor package, while other
embodiments call for multiple interconnected packages. By combining
one or more semiconductor packages over a single substrate,
manufacturers can incorporate pre-made components into electronic
devices and systems. Because the semiconductor packages include
sophisticated functionality, electronic devices can be manufactured
using cheaper components and a streamlined manufacturing process.
The resulting devices are less likely to fail and less expensive to
manufacture resulting in a lower cost for consumers.
[0049] FIGS. 2a-2c show exemplary semiconductor packages. FIG. 2a
illustrates further detail of DIP 64 mounted on PCB 52.
Semiconductor die 74 includes an active region containing analog or
digital circuits implemented as active devices, passive devices,
conductive layers, and dielectric layers formed within the die and
are electrically interconnected according to the electrical design
of the die. For example, the circuit may include one or more
transistors, diodes, inductors, capacitors, resistors, and other
circuit elements formed within the active region of semiconductor
die 74. Contact pads 76 are one or more layers of conductive
material, such as aluminum (Al), copper (Cu), tin (Sn), nickel
(Ni), gold (Au), or silver (Ag), and are electrically connected to
the circuit elements formed within semiconductor die 74. During
assembly of DIP 64, semiconductor die 74 is mounted to an
intermediate carrier 78 using a gold-silicon eutectic layer or
adhesive material such as thermal epoxy or epoxy resin. The package
body includes an insulative packaging material such as polymer or
ceramic. Conductor leads 80 and wire bonds 82 provide electrical
interconnect between semiconductor die 74 and PCB 52. Encapsulant
84 is deposited over the package for environmental protection by
preventing moisture and particles from entering the package and
contaminating die 74 or wire bonds 82.
[0050] FIG. 2b illustrates further detail of BCC 62 mounted on PCB
52. Semiconductor die 88 is mounted over carrier 90 using an
underfill or epoxy-resin adhesive material 92. Wire bonds 94
provide first level packaging interconnect between contact pads 96
and 98. Molding compound or encapsulant 100 is deposited over
semiconductor die 88 and wire bonds 94 to provide physical support
and electrical isolation for the device. Contact pads 102 are
formed over a surface of PCB 52 using a suitable metal deposition
process such as electrolytic plating or electroless plating to
prevent oxidation. Contact pads 102 are electrically connected to
one or more conductive signal traces 54 in PCB 52. Bumps 104 are
formed between contact pads 98 of BCC 62 and contact pads 102 of
PCB 52.
[0051] In FIG. 2c, semiconductor die 58 is mounted face down to
intermediate carrier 106 with a flip chip style first level
packaging. Active region 108 of semiconductor die 58 contains
analog or digital circuits implemented as active devices, passive
devices, conductive layers, and dielectric layers formed according
to the electrical design of the die. For example, the circuit may
include one or more transistors, diodes, inductors, capacitors,
resistors, and other circuit elements within active region 108.
Semiconductor die 58 is electrically and mechanically connected to
carrier 106 through bumps 110.
[0052] BGA 60 is electrically and mechanically connected to PCB 52
with a BGA style second level packaging using bumps 112.
Semiconductor die 58 is electrically connected to conductive signal
traces 54 in PCB 52 through bumps 110, signal lines 114, and bumps
112. A molding compound or encapsulant 116 is deposited over
semiconductor die 58 and carrier 106 to provide physical support
and electrical isolation for the device. The flip chip
semiconductor device provides a short electrical conduction path
from the active devices on semiconductor die 58 to conduction
tracks on PCB 52 in order to reduce signal propagation distance,
lower capacitance, and improve overall circuit performance. In
another embodiment, the semiconductor die 58 can be mechanically
and electrically connected directly to PCB 52 using flip chip style
first level packaging without intermediate carrier 106.
[0053] FIGS. 3a-3i illustrate, in relation to FIGS. 1 and 2a-2c, a
process of forming a WLCSMP having an open cavity for containing a
semiconductor die and interconnected through TSV interposer. FIG.
3a shows a semiconductor wafer 118 containing a base substrate
material, such as silicon, germanium, gallium arsenide, indium
phosphide, or silicon carbide, for structural support. A plurality
of vias is formed from surface 123 partially through semiconductor
wafer 118 using laser drilling, mechanical drilling, or etching
process, such as deep reactive ion etching (DRIE) or potassium
hydroxide (KOH) etch. An optional insulating layer can be formed
around the vias as a liner. After depositing the insulation layer
inside the vias, the vias are filled with Al, Cu, Sn, Ni, Au, Ag,
titanium (Ti), W, poly-silicon, or other suitable electrically
conductive material using PVD, CVD, electrolytic plating,
electroless plating, or other suitable metal deposition process to
form conductive through silicon vias (TSV) 122.
[0054] A circuit layer 124 is formed over surface 123 of
semiconductor wafer 118. Circuit layer 124 contains an electrically
conductive layer 125 separated by insulating layer 126. The
insulating layer 126 can be one or more layers of silicon dioxide
(SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON),
tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), photoresist, or
other material having similar insulating and structural properties.
The insulating layer 126 is formed using PVD, CVD, printing, spin
coating, spray coating, sintering or thermal oxidation. A portion
of insulating layer 126 is removed by an etching process.
Conductive layer 125 is formed in the removed portions of
insulating layer 126 using patterning with PVD, CVD, sputtering,
electrolytic plating, electroless plating, or other suitable metal
deposition process. Conductive layer 125 can be one or more layers
of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically
conductive material. One portion of conductive layer 125 is
electrically connected to TSV 122. Other portions of conductive
layer 125 can be electrically common or electrically isolated
depending on the design and function of the semiconductor device.
One or more integrated passive devices (IPD), such as inductors,
capacitors, and resistors, can be formed in circuit layer 124 for
RF signal processing.
[0055] A trench or cavity 128 is formed from surface 123 partially
through semiconductor wafer 118 with sufficient width and depth to
contain a semiconductor die. Trench 128 can be formed with saw
blade, laser drilling, mechanical drilling, DRIE, or KOH etch. In
one embodiment, trench 128 has a width greater than an x/y axis
length of the semiconductor die and depth greater than a thickness
of the semiconductor die. An optional trench 130 is formed from
surface 123 partially through semiconductor wafer 118 for dicing
saw space. Trench 130 allows the sides of semiconductor wafer 118
(later referred to as TSV interposer) to be covered by encapsulant
after singulation.
[0056] A substrate or carrier 120 contains temporary or sacrificial
base material such as silicon, polymer, polymer composite, metal,
ceramic, glass, glass epoxy, beryllium oxide, or other suitable
low-cost, rigid material for structural support. An interface layer
or tape 121 is applied over carrier 120 as a temporary adhesive
bonding film or etch-stop layer.
[0057] FIG. 3b shows semiconductor wafer 118 mounted to carrier
tape 121 with surface 123 oriented away from the tape. In another
embodiment, TSV 122 can be formed in semiconductor wafer 118 after
to mounting the wafer to carrier 120.
[0058] FIG. 3c shows a semiconductor die or component 132 having an
active surface 133 containing analog or digital circuits
implemented as active devices, passive devices, conductive layers,
and dielectric layers formed within the die and electrically
interconnected according to the electrical design and function of
the die. For example, the circuit may include one or more
transistors, diodes, and other circuit elements formed within
active surface 133 to implement analog circuits or digital
circuits, such as digital signal processor (DSP), ASIC, memory, or
other signal processing circuit. Semiconductor die 132 may also
contain IPD, such as inductors, capacitors, and resistors, for RF
signal processing.
[0059] An electrically conductive bump material is deposited over
active surface 133 using an evaporation, electrolytic plating,
electroless plating, ball drop, or screen printing process. The
bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and
combinations thereof, with an optional flux solution. For example,
the bump material can be eutectic Sn/Pb, high-lead solder, or
lead-free solder. The bump material is reflowed by heating the
material above its melting point to form spherical balls or bumps
136. Bumps 136 represent one type of interconnect structure that
can be formed over active surface 133. The interconnect structure
can also use stud bumps, micro bumps, conductive pillars,
conductive paste, or other electrical interconnect.
[0060] A semiconductor die or component 134 is mounted and
electrically connected to semiconductor die 132 using bumps 136.
Semiconductor die 134 has an active surface 135 containing analog
or digital circuits implemented as active devices, passive devices,
conductive layers, and dielectric layers formed within the die and
electrically interconnected according to the electrical design and
function of the die. For example, the circuit may include one or
more transistors, diodes, and other circuit elements formed within
active surface 135 to implement analog circuits or digital
circuits, such as DSP, ASIC, memory, or other signal processing
circuit. Semiconductor die 134 may also contain IPD, such as
inductors, capacitors, and resistors, for RF signal processing.
[0061] The combined semiconductor die 132-134 are positioned over
semiconductor wafer 118 and aligned to place semiconductor die 134
over trench 128. The combined semiconductor die 132-134 are then
mounted to semiconductor wafer 118 by reflowing bumps 136 to
metallurgically and electrically connect active surface 133 to
conductive layer 125, as shown in FIG. 3d. Semiconductor die 134 is
contained within trench 128 to reduce the package height.
[0062] In FIG. 3e, an encapsulant or molding compound 140 is
deposited over semiconductor wafer 118 and around semiconductor die
132 and 134 using a paste printing, compressive molding, transfer
molding, liquid encapsulant molding, vacuum lamination, spin
coating, or other suitable applicator. Encapsulant 140 can be
polymer composite material, such as epoxy resin with filler, epoxy
acrylate with filler, or polymer with proper filler. Encapsulant
140 is non-conductive and environmentally protects the
semiconductor device from external elements and contaminants.
[0063] In FIG. 3f, a portion of encapsulant 140 is removed by
grinding wheel 142 to expose a back surface 143 of semiconductor
die 132 and reduce the height of the package. In another
embodiment, such as described in FIG. 9, grinding wheel 142 can
leave a portion of encapsulant 140 covering surface 143 of
semiconductor die 132.
[0064] In FIG. 3g, an optional substrate or carrier 144 contains
temporary or sacrificial base material such as silicon, polymer,
polymer composite, metal, ceramic, glass, glass epoxy, beryllium
oxide, or other suitable low-cost, rigid material or bulk
semiconductor material for structural support. An interface layer
or tape 146 is applied over carrier 144 as a temporary adhesive
bonding film or etch-stop layer. The assembly described in FIGS.
3a-3f is inverted and mounted to carrier tape 146. The carrier 120
and tape 121 are removed by chemical etching, mechanical peel-off,
CMP, mechanical grinding, thermal bake, laser scanning, or wet
stripping.
[0065] In FIG. 3h, a portion of surface 147 of semiconductor wafer
118, opposite surface 123, is removed by grinding wheel 142 to
expose TSV 122 and back surface 148 of semiconductor die 134 and
reduce the height of the package. The remaining portion of
semiconductor wafer 118 constitutes interposer 149 having TSV 122
for electrical interconnect.
[0066] In FIG. 3i, an interconnect structure 150 is formed over
surface 151 of interposer 149. The interconnect structure 150
includes an insulating or passivation layer 152 formed over surface
151 as using PVD, CVD, printing, spin coating, spray coating,
sintering or thermal oxidation. The insulating layer 152 can be one
or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other
material having similar insulating and structural properties. A
portion of insulating layer 152 is removed by an etching process to
expose TSV 122.
[0067] An electrically conductive layer 154 is formed over TSV 122
and the removed portion of insulating layer 152 using a patterning
and deposition process such as PVD, CVD, sputtering, electrolytic
plating, and electroless plating. Conductive layer 154 can be one
or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable
electrically conductive material. An optional under bump
metallization (UBM) layer can be formed over conductive layer 154.
One portion of conductive layer 154 is electrically connected to
TSV 122 and circuit layer 124. Other portions of conductive layer
154 can be electrically common or electrically isolated depending
on the design and function of the semiconductor device.
[0068] An electrically conductive bump material is deposited over
build-up interconnect structure 150 and electrically connected to
conductive layer 154 using an evaporation, electrolytic plating,
electroless plating, ball drop, or screen printing process. The
bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and
combinations thereof, with an optional flux solution. For example,
the bump material can be eutectic Sn/Pb, high-lead solder, or
lead-free solder. The bump material is bonded to conductive layer
154 using a suitable attachment or bonding process. In one
embodiment, the bump material is reflowed by heating the material
above its melting point to form spherical balls or bumps 156. In
some applications, bumps 156 are reflowed a second time to improve
electrical contact to conductive layer 154. The bumps can also be
compression bonded to conductive layer 154. Bumps 156 represent one
type of interconnect structure that can be formed over conductive
layer 154. The interconnect structure can also use stud bumps,
micro bumps, conductive pillars, conductive paste, or other
electrical interconnect.
[0069] The carrier 144 and tape 146 are removed by chemical
etching, mechanical peel-off, CMP, mechanical grinding, thermal
bake, laser scanning, or wet stripping. Semiconductor die 132 and
134 are singulated with saw blade or laser cutting device 160 into
individual WLCSMP. FIG. 4 shows WLCSMP 162 after singulation.
Discrete semiconductor components 164, such as resistor, capacitor,
inductor, or active component, are mounted to interposer 149.
Semiconductor die 134 is electrically connected to semiconductor
die 132 through bumps 136. Semiconductor die 132 is electrically
connected through circuit layer 124 and interposer 149 containing
TSV 122 to interconnect structure 150. The WLCSMP 162 has an open
cavity for containing semiconductor die 134 to reduce the height of
the package. The grinding process also reduces the height of WLCSMP
162. In one embodiment, the sides of interposer 149 are covered by
encapsulant 140 due to the extra dicing space provided by trench
130. Alternatively, without trench 130, the sides of interposer 149
can be exposed. The exposed surface 143 of semiconductor die 132
and exposed surface 148 of semiconductor die 134 provide for good
heat dissipation. The similar base material of semiconductor die
132 and 134 and interposer 149, e.g., silicon, provides thermal
stress relief and makes WLCSMP 162 robust against any mismatch in
CTE between the components of the package. Accordingly, WLCSMP 162
has reduced occurrence of warpage.
[0070] In a variation of the above process, after FIG. 3h, an
interconnect structure 170 is formed over surface 151 of interposer
149, as shown in FIG. 5. The interconnect structure 170 includes a
polymer insulating layer 172 formed over surface 151 using spin
coating, film lamination, molding, or other suitable deposition
process. Polymer insulating layer 172 can be one or more layers of
polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO), or other
material having similar insulating and structural properties. A
portion of polymer insulating layer 172 is removed by an etching
process to expose TSV 122.
[0071] An electrically conductive layer 174 is formed over TSV 122
and the removed portion of polymer insulating layer 172 using a
patterning and deposition process such as PVD, CVD, sputtering,
electrolytic plating, and electroless plating. Conductive layer 174
can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other
suitable electrically conductive material. One portion of
conductive layer 174 is electrically connected to TSV 122 and
circuit layer 124. Other portions of conductive layer 174 can be
electrically common or electrically isolated depending on the
design and function of the semiconductor device.
[0072] An electrically conductive bump material is deposited over
build-up interconnect structure 170 and electrically connected to
conductive layer 174 using an evaporation, electrolytic plating,
electroless plating, ball drop, or screen printing process. The
bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and
combinations thereof, with an optional flux solution. For example,
the bump material can be eutectic Sn/Pb, high-lead solder, or
lead-free solder. The bump material is bonded to conductive layer
174 using a suitable attachment or bonding process. In one
embodiment, the bump material is reflowed by heating the material
above its melting point to form spherical balls or bumps 176. In
some applications, bumps 176 are reflowed a second time to improve
electrical contact to conductive layer 174. The bumps can also be
compression bonded to conductive layer 174. Bumps 176 represent one
type of interconnect structure that can be formed over conductive
layer 174. The interconnect structure can also use stud bumps,
micro bumps, conductive pillars, conductive paste, or other
electrical interconnect.
[0073] FIG. 6 shows WLCSMP 178 including the features described in
FIGS. 3a-3i and 4 and metal plate 180 mounted to surface 143 of
semiconductor die 132 and encapsulant 140 with thermally conductive
adhesive. Metal plate 180 can also be formed by electroless or
electroplating process. Metal plate 180 operates as a heat spreader
to dissipate thermal energy from WLCSMP 178. Metal plate 180 can be
Al, Cu, or another material with high thermal conductivity. An
optional die attach adhesive or thermal interface layer (TIM) 182
secures metal plate 180 to semiconductor die 132 and encapsulant
140. Metal plate 180 increases the rigidity of WLCSMP 178.
[0074] FIG. 7 shows WLCSMP 190 including the features described in
FIGS. 3a-3i and 4 and metal plate 192 mounted to surface 143 of
semiconductor die 132 and encapsulant 140 with an adhesive. Metal
plate 192 can also be formed by electroless or electroplating
process. Metal plate 192 operates as an electromagnetic
interference (EMI) or radio frequency interference (RFI) shielding
layer. Metal plate 192 can be Cu, Al, ferrite or carbonyl iron,
stainless steel, nickel silver, low-carbon steel, silicon-iron
steel, foil, epoxy, conductive resin, and other metals and
composites capable of blocking or absorbing EMI, RFI, and other
inter-device interference. The shielding layer can also be a
non-metal material such as carbon-black or aluminum flake to reduce
the effects of EMI and RFI. Metal plate 192 is grounded through
conductive pillars or studs 194, circuit layer 124, TSV 122 in
interposer 149, and interconnect structure 150. Conductive pillars
194 can be Au studs, or Cu pillars, or solder. Metal plate 192 also
operates as a heat spreader to dissipate thermal energy from WLCSMP
190.
[0075] FIG. 8 shows WLCSMP 196 including the features described in
FIGS. 3a-3i and 4 and conductive pillars or studs 198 formed in
encapsulant 140. Conductive pillars 198 can be formed by laser
drilling, mechanical drilling, or DRIE vias in encapsulant 140 and
filling the vias with conductive material, such as Cu, Au, or
solder. Conductive pillars 198 provide additional interconnect
capability for stacking semiconductor packages.
[0076] FIG. 9 shows WLCSMP 200 including the features described in
FIGS. 3a-3i and 4, with the exception that the grinding operation
described in FIG. 3f leaves encapsulant 140 covering surface 143 of
semiconductor die 132. Conductive pillars or studs 202 can be
formed by laser drilling, mechanical drilling, or DRIE vias in
encapsulant 140 and filling the vias with conductive material, such
as Cu, Au, or solder. Conductive layer 204 is formed in encapsulant
140. Conductive pillars 202 and conductive layer 204 provide
additional interconnect capability for fan-in stacking
semiconductor packages.
[0077] FIG. 10 shows WLCSMP 210 including the features described in
FIGS. 3a-3i and 4. In addition, conductive pillars or studs 212 can
be formed by laser drilling, mechanical drilling, or DRIE vias in
encapsulant 140 and filling the vias with conductive material, such
as Cu, Au, or solder. An interconnect structure 214 is formed over
surface 143 of semiconductor die 132 and encapsulant 140. The
interconnect structure 214 includes an insulating or passivation
layer 216 formed using PVD, CVD, printing, spin coating, spray
coating, sintering or thermal oxidation. The insulating layer 216
can be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or
other material having similar insulating and structural properties.
An electrically conductive layer 218 is formed in insulating layer
216 using a patterning and deposition process such as PVD, CVD,
sputtering, electrolytic plating, and electroless plating.
Conductive layer 218 can be one or more layers of Al, Cu, Sn, Ni,
Au, Ag, or other suitable electrically conductive material. One
portion of conductive layer 218 is electrically connected to
conductive pillars 212. Other portions of conductive layer 218 can
be electrically common or electrically isolated depending on the
design and function of the semiconductor device. Conductive pillars
212 and interconnect structure 214 provide additional interconnect
capability for fan-in stacking semiconductor packages.
[0078] FIG. 11 shows WLCSMP 220 including the features described in
FIGS. 3a-3i and 4. In addition, conductive pillars 222 can be
formed by laser drilling, mechanical drilling, or DRIE vias in
semiconductor die 132 and filling the vias with conductive
material, such as Cu or Au. An interconnect structure 224 is formed
over surface 143 of semiconductor die 132. The interconnect
structure 224 includes an insulating or passivation layer 226
formed using PVD, CVD, printing, spin coating, spray coating,
sintering or thermal oxidation. The insulating layer 226 can be one
or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other
material having similar insulating and structural properties. A
portion of insulating layer 226 is removed by an etching process.
An electrically conductive layer 228 is formed in the removed
portion of insulating layer 226 using a patterning and deposition
process such as PVD, CVD, sputtering, electrolytic plating, and
electroless plating. Conductive layer 228 can be one or more layers
of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically
conductive material. Conductive pillars 222 and conductive layer
226 provide additional interconnect capability for stacking
semiconductor packages.
[0079] FIG. 12 shows WLCSMP 230 including the features described in
FIGS. 3a-3i and 4. In addition, conductive pillars 232 can be
formed by laser drilling, mechanical drilling, or DRIE vias in
semiconductor die 134 and filling the vias with conductive
material, such as Cu or Au. The interconnect structure 150 is
extended over surface 148 of semiconductor die 134. Conductive
pillars 232 and interconnect structure 150 over surface 158 of
semiconductor die 134 provide additional interconnect capability
for stacking semiconductor packages.
[0080] FIGS. 13a-13g illustrate, in relation to FIGS. 1 and 2a-2c,
a process of forming an interposer with an opening for containing a
semiconductor die. In FIG. 13a, a wafer-form substrate or carrier
240 contains temporary or sacrificial base material such as
silicon, polymer, polymer composite, metal, ceramic, glass, glass
epoxy, beryllium oxide, or other suitable low-cost, rigid material
for structural support. An interface layer or tape 242 is applied
over carrier 240 as a temporary double-sided adhesive bonding film
or etch-stop layer.
[0081] In FIG. 13b, a die-form laminate interposer 244 is mounted
to interface layer 242 over carrier 240. The interposer 244
includes one or more insulating layers 246 and one or more
conductive layers 248. Conductive layer 248 provides a vertical
conduction path through interposer 244. The openings 250 have
sufficient width and depth to contain a semiconductor die.
[0082] FIG. 13c shows a semiconductor die or component 252 having
an active surface 254 containing analog or digital circuits
implemented as active devices, passive devices, conductive layers,
and dielectric layers formed within the die and electrically
interconnected according to the electrical design and function of
the die. For example, the circuit may include one or more
transistors, diodes, and other circuit elements formed within
active surface 254 to implement analog circuits or digital
circuits, such as DSP, ASIC, memory, or other signal processing
circuit. Semiconductor die 252 may also contain IPD, such as
inductors, capacitors, and resistors, for RF signal processing.
Bumps 256 are formed on contact pads 258 which are electrically
connected to the circuits within active surface 254 of
semiconductor die 252,
[0083] A semiconductor die or component 260 has an active surface
262 containing analog or digital circuits implemented as active
devices, passive devices, conductive layers, and dielectric layers
formed within the die and electrically interconnected according to
the electrical design and function of the die. For example, the
circuit may include one or more transistors, diodes, and other
circuit elements formed within active surface 262 to implement
analog circuits or digital circuits, such as DSP, ASIC, memory, or
other signal processing circuit. Semiconductor die 260 may also
contain IPD, such as inductors, capacitors, and resistors, for RF
signal processing. Contact pads 264 are electrically connected to
the circuits on active surface 262 of semiconductor die 260.
[0084] Semiconductor die 260 is mounted to semiconductor die 252
with die attach adhesive 268. The combined semiconductor die 252
and 260 are positioned over interposer 244 and aligned to place
semiconductor die 260 over opening 250 with contact pads 264
oriented toward carrier 240. The combined semiconductor die 252 and
260 are then mounted to interposer 244 by reflowing,
thermal-compress bonding, or mechanical plugging of bumps 256 to
metallurgically and electrically connect contact pads 258 to
conductive layer 248, as shown in FIG. 13d. Semiconductor die 260
is contained within opening 250 to reduce the package height.
[0085] In another embodiment, semiconductor die 260 is first
mounted in opening 250. Semiconductor die 252 is then mounted to
semiconductor die 260 and interposer 244 with die attach adhesive
268 and bumps 256.
[0086] In FIG. 13e, an encapsulant or molding compound 270 is
deposited over interposer 244 and around semiconductor die 252 and
260 using a paste printing, compressive molding, transfer molding,
liquid encapsulant molding, vacuum lamination, spin coating, or
other suitable applicator. Encapsulant 270 can be polymer composite
material, such as epoxy resin with filler, epoxy acrylate with
filler, or polymer with proper filler. Encapsulant 270 is
non-conductive and environmentally protects the semiconductor
device from external elements and contaminants.
[0087] In FIG. 13f, carrier 240 and interface layer 242 are removed
by chemical etching, mechanical peel-off, CMP, mechanical grinding,
thermal bake, laser scanning, or wet stripping. A build-up
interconnect structure 274 is formed over semiconductor die 260 and
interposer 244. The build-up interconnect structure 274 includes an
insulating or passivation layer 276 formed by PVD, CVD, printing,
spin coating, spray coating, or thermal oxidation. The insulating
layer 276 can be one or more layers of SiO2, Si3N4, SiON, Ta2O5,
Al2O3, polymer dielectric, or other material having similar
insulating and structural properties. An electrically conductive
layer 278 is formed using patterning and PVD, CVD, electrolytic
plating, electroless plating process, or other suitable metal
deposition process. Conductive layer 278 can be one or more layers
of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically
conductive material. Conductive layer 278 is electrically connected
to conductive layer 248 of interposer 244 and contact pads 264 of
semiconductor die 260. Conductive layer 278 operates, in part, as a
redistribution layer (RDL) to extend the electrical connectivity of
interposer 244.
[0088] An electrically conductive bump material is deposited over
build-up interconnect structure 274 and electrically connected to
conductive layer 278 using an evaporation, electrolytic plating,
electroless plating, ball drop, or screen printing process. The
bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and
combinations thereof, with an optional flux solution. For example,
the bump material can be eutectic Sn/Pb, high-lead solder, or
lead-free solder. The bump material is bonded to conductive layer
278 using a suitable attachment or bonding process. In one
embodiment, the bump material is reflowed by heating the material
above its melting point to form spherical balls or bumps 280. In
some applications, bumps 280 are reflowed a second time to improve
electrical contact to conductive layer 278. The bumps can also be
compression bonded to conductive layer 278. Bumps 280 represent one
type of interconnect structure that can be formed over conductive
layer 278. The interconnect structure can also use stud bumps,
micro bumps, conductive pillars, conductive paste, or other
electrical interconnect.
[0089] Semiconductor die 252 and 260 are singulated with saw blade
or laser cutting device 281 into individual FO-WLCSP 282. FIG. 14
shows FO-WLCSP 282 after singulation. Semiconductor die 252 is
electrically connected to semiconductor die 260 through bumps 256,
interposer 244, and conductive layer 278 of build-up interconnect
structure 274. FO-WLCSP 282 has interposer 244 with an open cavity
for containing semiconductor die 260 to reduce the height of the
package. Bumps 256 are relatively small, compared to bumps 280,
which provides finer pitch and higher I/O count for semiconductor
die 252. The smaller bumps 256 also improves control of bump
collapse and reduces electrical shorting to adjacent conductive
structures. The interposer 244 reduces the encapsulant flow
pressure toward semiconductor die 260 to reduce die shifting during
encapsulation.
[0090] FIG. 15 shows FO-WLCSP 290 similar to the features described
in FIGS. 13a-13g and 14 with conductive TSV 292 formed through
semiconductor die 260. A plurality of vias is formed through
semiconductor die 260 over contact pads 264 using laser drilling,
mechanical drilling, or DRIE. The vias are filled with Al, Cu, Sn,
Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically
conductive material using electrolytic plating, electroless plating
process, or other suitable metal deposition process to form
conductive TSVs 292 for vertical interconnectivity. Bumps 294 are
formed between TSVs 292 and contact pads 258 to provide electrical
connection between semiconductor die 252 and semiconductor die
260.
[0091] FIG. 16 shows FO-WLCSP 296 similar to the features described
in FIGS. 13a-13g and 14 with conductive through mold vias (TMV) 298
formed through encapsulant 270. A plurality of vias is formed
through encapsulant 270 over conductive layer 248 using laser
drilling, mechanical drilling, or DRIE. The vias are filled with
Al, Cu, Sn, Ni, Au, Ag, Ti, W, poly-silicon, or other suitable
electrically conductive material using electrolytic plating,
electroless plating process, or other suitable metal deposition
process to form conductive TMVs 298 for vertical interconnectivity.
TMVs 298 are electrically connected to conductive layer 248 of
interposer 244. In another embodiment, conductive pillars, stacked
bumps, or studs are formed in encapsulant 270.
[0092] FIG. 17 shows FO-WLCSP 300 similar to the features described
in FIGS. 13a-13g and 14 with conductive TSV 302 formed through
semiconductor die 252. A plurality of vias is formed through
semiconductor die 252 over contact pads 258 using laser drilling,
mechanical drilling, or DRIE. The vias are filled with Al, Cu, Sn,
Ni, Au, Ag, Ti, W, poly-silicon, or other suitable electrically
conductive material using electrolytic plating, electroless plating
process, or other suitable metal deposition process to form
conductive TSVs 302 for vertical interconnectivity.
[0093] A thermal interface material (TIM) 304 is applied over a
back surface of semiconductor die 252, opposite active surface 254.
A heat sink 306 is mounted over TIM 304 and the back surface of
semiconductor die 252. Heat sink 306 can be Al, Cu, or another
material with high thermal conductivity to provide heat dissipation
for semiconductor die 252. TIM 304 can be aluminum oxide, zinc
oxide, boron nitride, or pulverized silver. TIM 304 aids in the
distribution and dissipation of heat generated by semiconductor die
252 and 260.
[0094] FIG. 18 shows FO-WLCSP 308 similar to the features described
in FIGS. 13a-13g and 14 with interposer 244 truncated or singulated
to remove opposing end portions of the interposer. An encapsulant
or molding compound 309 is deposited over interposer 244 and around
semiconductor die 252 and 260 using a paste printing, compressive
molding, transfer molding, liquid encapsulant molding, vacuum
lamination, spin coating, or other suitable applicator. Encapsulant
309 can be polymer composite material, such as epoxy resin with
filler, epoxy acrylate with filler, or polymer with proper filler.
Encapsulant 309 is non-conductive and environmentally protects the
semiconductor device from external elements and contaminants.
Encapsulant 309 covers the sides of FO-WLCSP 308 for additional
protection.
[0095] FIG. 19 shows FO-WLCSP 310 similar to the features described
in FIGS. 13a-13g and 14 without semiconductor die 252. Discrete
semiconductor components 312 are mounted and electrically connected
to conductive layer 248 of interposer 244. Discrete semiconductor
components 312 can be active devices, such as transistors and
diodes, or passive devices, such as capacitors, resistors, and
inductors. The interposer 244 prevents shifting of discrete
semiconductor components 312 during encapsulation.
[0096] An encapsulant or molding compound 311 is deposited over
interposer 244 and around semiconductor die 260 and discrete
semiconductor component 312 using a paste printing, compressive
molding, transfer molding, liquid encapsulant molding, vacuum
lamination, spin coating, or other suitable applicator. Encapsulant
311 can be polymer composite material, such as epoxy resin with
filler, epoxy acrylate with filler, or polymer with proper filler.
Encapsulant 311 is non-conductive and environmentally protects the
semiconductor device from external elements and contaminants.
[0097] FIG. 20 shows FO-WLCSP 314 similar to the features described
in FIGS. 13a-13g and 14 with two-level stepped interposer 316
having one or more conductive layers 318 and one or more conductive
layers 320 and one or more insulating layers 322. Conductive layers
318 and 320 provide a vertical conduction path through interposer
316. Conductive layer 318 is electrically connected to conductive
layer 278 of build-up interconnect structure 274. Conductive layer
320 is electrically connected between bumps 256 and conductive
layer 278.
[0098] An electrically conductive layer 324 is formed over
interposer 316 and encapsulant 270 using patterning and PVD, CVD,
electrolytic plating, electroless plating process, or other
suitable metal deposition process. Conductive layer 324 can be one
or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable
electrically conductive material. Conductive layer 324 is
electrically connected to conductive layer 318 of interposer 316
and operates, in part, as an RDL to extend the electrical
connectivity of the interposer to external devices.
[0099] FIG. 21 shows FO-WLCSP 330 similar to the features described
in FIGS. 13a-13g and 14 with second interposer 332 stacked over
interposer 244 by fit-press process to form multiple stepped
interposers. The second interposer 332 has one or more conductive
layers 334 and one or more insulating layers 336. Conductive layer
334 provides a vertical conduction path through interposer 332.
Conductive layer 334 is electrically connected to conductive layer
248 of interposer 244.
[0100] FIG. 22 shows FO-WLCSP 340 similar to the features described
in FIGS. 13a-13g and 14 with two-level stepped interposer 342
having one or more conductive layers 344 and one or more conductive
layers 346 and one or more insulating layers 348. Conductive layers
344 and 346 provide a vertical conduction path through interposer
342. Conductive layer 344 is electrically connected between bumps
256 and conductive layer 278 of build-up interconnect structure
274.
[0101] A semiconductor die or component 350 has an active surface
352 containing analog or digital circuits implemented as active
devices, passive devices, conductive layers, and dielectric layers
formed within the die and electrically interconnected according to
the electrical design and function of the die. For example, the
circuit may include one or more transistors, diodes, and other
circuit elements formed within active surface 352 to implement
analog circuits or digital circuits, such as DSP, ASIC, memory, or
other signal processing circuit. Semiconductor die 350 may also
contain IPD, such as inductors, capacitors, and resistors, for RF
signal processing. Contact pads 354 are electrically connected to
the circuits on active surface 262. Semiconductor die 350 is
mounted and electrically connected to conductive layer 346 of
interposer 342 with bumps 356.
[0102] An encapsulant or molding compound 358 is deposited over
interposer 342 and around semiconductor die 252, 260, and 350 using
a paste printing, compressive molding, transfer molding, liquid
encapsulant molding, vacuum lamination, spin coating, or other
suitable applicator. Encapsulant 358 can be polymer composite
material, such as epoxy resin with filler, epoxy acrylate with
filler, or polymer with proper filler. Encapsulant 358 is
non-conductive and environmentally protects the semiconductor
device from external elements and contaminants.
[0103] Semiconductor die 252 is electrically connected to
semiconductor die 260 through bumps 256, interposer 342, and
conductive layer 278 of build-up interconnect structure 274.
Semiconductor die 350 is electrically connected to semiconductor
die 252 and 260 through bumps 256 and 356, interposer 342, and
conductive layer 278 of build-up interconnect structure 274.
FO-WLCSP 340 has stepped interposer 342 with an open cavity for
containing semiconductor die 252 and 260 to reduce the height of
the package. Bumps 256 and 356 are relatively small, compared to
bumps 280, which provides finer pitch and higher I/O count for
semiconductor die 252 and 260. The smaller bumps 256 and 356 also
improve control of bump collapse and reduce electrical shorting to
adjacent conductive structures. The interposer 342 reduces the
encapsulant flow pressure toward semiconductor die 252 and 260 to
reduce die shifting during encapsulation.
[0104] While one or more embodiments of the present invention have
been illustrated in detail, the skilled artisan will appreciate
that modifications and adaptations to those embodiments may be made
without departing from the scope of the present invention as set
forth in the following claims.
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