U.S. patent application number 13/939146 was filed with the patent office on 2013-11-07 for package-on-package interconnect stiffener.
The applicant listed for this patent is Leonel R. Arana, Sanka Ganesan, John S. Guzek, Yosuke Kanaoka, Robert M. Nickerson, Rajasekaran Swaminathan, Yoshihiro Tomita, Ram S. Viswanath. Invention is credited to Leonel R. Arana, Sanka Ganesan, John S. Guzek, Yosuke Kanaoka, Robert M. Nickerson, Rajasekaran Swaminathan, Yoshihiro Tomita, Ram S. Viswanath.
Application Number | 20130292838 13/939146 |
Document ID | / |
Family ID | 42933723 |
Filed Date | 2013-11-07 |
United States Patent
Application |
20130292838 |
Kind Code |
A1 |
Ganesan; Sanka ; et
al. |
November 7, 2013 |
PACKAGE-ON-PACKAGE INTERCONNECT STIFFENER
Abstract
Embodiments of the invention relate to a package-on-package
(PoP) assembly comprising a top device package and a bottom device
package interconnected by way of an electrically interconnected
planar stiffener. Embodiments of the invention include a first
semiconductor package having a plurality of inter-package contact
pads and a plurality of second level interconnect (SLI) pads; a
second semiconductor package having a plurality of SLI pads on the
bottom side of the package; and a planar stiffener having a first
plurality of planar contact pads on the top side of the stiffener
electrically connected to the SLI pads of the second package, and a
second plurality of planar contact pads electrically connected to
the inter-package contact pads of the first package.
Inventors: |
Ganesan; Sanka; (Chandler,
AZ) ; Kanaoka; Yosuke; (Tsukuba-shi, JP) ;
Viswanath; Ram S.; (Phoenix, AZ) ; Swaminathan;
Rajasekaran; (Tempe, AZ) ; Nickerson; Robert M.;
(Chandler, AZ) ; Arana; Leonel R.; (Phoenix,
AZ) ; Guzek; John S.; (Chandler, AZ) ; Tomita;
Yoshihiro; (Tsukuba-shi, JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Ganesan; Sanka
Kanaoka; Yosuke
Viswanath; Ram S.
Swaminathan; Rajasekaran
Nickerson; Robert M.
Arana; Leonel R.
Guzek; John S.
Tomita; Yoshihiro |
Chandler
Tsukuba-shi
Phoenix
Tempe
Chandler
Phoenix
Chandler
Tsukuba-shi |
AZ
AZ
AZ
AZ
AZ
AZ |
US
JP
US
US
US
US
US
JP |
|
|
Family ID: |
42933723 |
Appl. No.: |
13/939146 |
Filed: |
July 10, 2013 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12384984 |
Apr 10, 2009 |
8513792 |
|
|
13939146 |
|
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|
|
Current U.S.
Class: |
257/773 ;
438/109 |
Current CPC
Class: |
H01L 23/488 20130101;
H01L 2224/32225 20130101; H01L 2924/15311 20130101; H01L 2924/00014
20130101; H01L 2225/107 20130101; H01L 2924/00014 20130101; H01L
23/562 20130101; H01L 2225/1023 20130101; H01L 2924/15311 20130101;
H01L 25/105 20130101; H01L 23/49833 20130101; H01L 23/3128
20130101; H01L 2224/48091 20130101; H01L 2224/73265 20130101; H01L
2924/01078 20130101; H01L 2924/14 20130101; H01L 21/50 20130101;
H01L 2924/01079 20130101; H01L 24/73 20130101; H01L 2924/00012
20130101; H01L 2924/181 20130101; H01L 2224/73265 20130101; H01L
2224/45015 20130101; H01L 2924/00012 20130101; H01L 2224/32225
20130101; H01L 2924/00014 20130101; H01L 2224/32225 20130101; H01L
2924/00 20130101; H01L 2924/207 20130101; H01L 2224/45099 20130101;
H01L 2224/48227 20130101; H01L 24/48 20130101; H01L 2224/48227
20130101; H01L 2224/48227 20130101; H01L 2224/73265 20130101; H01L
2924/181 20130101; H01L 2224/48091 20130101; H01L 2924/3511
20130101; H01L 2924/01046 20130101; H01L 2924/15331 20130101; H01L
2924/00014 20130101 |
Class at
Publication: |
257/773 ;
438/109 |
International
Class: |
H01L 23/488 20060101
H01L023/488; H01L 21/50 20060101 H01L021/50 |
Claims
1. A package-on-package (PoP) assembly, comprising: a first
semiconductor package having a plurality of inter-package contact
pads and a plurality of second level interconnect (SLI) pads; a
second semiconductor package having a plurality of SLI pads on the
bottom side of the package; and a planar stiffener having a first
plurality of planar contact pads on the top side of the stiffener
electrically connected to the SLI pads of the second package, and a
second plurality of planar contact pads electrically connected to
the inter-package contact pads of the first package.
2. The assembly of claim 1, wherein the stiffener includes routing
features accommodating various circuitry designs of the second
package.
3. The assembly of claim 2, wherein the substrate includes a
coefficient of thermal expansion (CTE) approximately between 15 and
25 ppm, and a flexural modulus approximately between 15 and 30
GPa.
4. The assembly of claim 1, wherein the layout of the second
plurality of planar contact pads of the stiffener matches the
layout of the inter-package contact pads of the first package.
5. The assembly of claim 1, wherein the stiffener includes a plug
material disposed between the first plurality and the second
plurality of planar contact pads.
6. The assembly of claim 1, wherein the stiffener includes a plug
material disposed in the substrate.
7. A method to form a package-on-package (PoP) assembly,
comprising: providing a first semiconductor package having a
plurality of inter-package contact pads and a plurality of second
level interconnect (SLI) pads; attaching micro balls to the
inter-package contact pads of the first package; connecting a
planar stiffener to the micro balls attached to the first package,
the stiffener having a first plurality of planar contact pads on
the top side of the stiffener to receive a second semiconductor
package, and a second plurality of planar contact pads to connect
the stiffener to the micro balls attached to the first package; and
reflowing the micro balls to form electrical connection between the
stiffener and the first package.
8. The method of claim 7, further comprising attaching a bottom
side of the stiffener to the first package by way of an adhesive of
low glass transition temperature (T.sub.g).
9. The method of claim 7, wherein the stiffener comprises: a
substrate having a through recess adapted to house a die attached
to the first package, and a plurality of through openings through
which the first and second pluralities of contact pads are
disposed; a solder-wettable planar surface finish on the first and
second pluralities of contact pads; and a conductive trace
electrically connecting the first plurality of contact pads to the
corresponding second plurality of contact pads.
10. A semiconductor assembly, comprising: a first semiconductor
package including a first substrate and a first die having a
plurality of inter-package contact pads and a plurality of second
level interconnect (SLI) pads; a planar stiffener having a first
plurality of planar contact pads on the top side of the stiffener
configured to electrically connect the planar stiffener and a
second die, and a second plurality of planar contact pads on the
bottom side of the stiffener electrically connected to the
inter-package contact pads of the first package and a wire bond in
contact with the second die and electrically coupled to the first
semiconductor package through the planar stiffener; wherein the
second die and the planar stiffener are stacked on the first
substrate.
11. The semiconductor assembly of claim 10, wherein the planar
stiffener is configured to electrically connect a second
semiconductor package including the planar stiffener and the second
die.
12. The semiconductor assembly of claim 10, wherein the second die
is part of a memory package.
13. The semiconductor assembly of claim 10, wherein the second die
is part of a cache unit.
14. The semiconductor assembly of claim 10, wherein the second die
is part of a device package suited for connection with the type of
device of the first semiconductor package.
15. The semiconductor assembly of claim 10, wherein the first die
is part of a semiconductor logic package.
16. The semiconductor assembly of claim 10, wherein the first die
is part of a semiconductor logic package, and wherein the second
die is part of a memory package.
17. The semiconductor assembly of claim 10, wherein the first die
is part of a semiconductor logic package, and wherein the second
die is part of a cache unit.
18. The semiconductor assembly of claim 10, wherein the first die
is part of a semiconductor logic package, and wherein the second
die is part of a device package suited for connection with the type
of device of the first semiconductor package.
19. The semiconductor assembly of claim 10, wherein the wire bond
is electrically coupled to the planar stiffener by direct contact
to a second substrate upon which the second die is disposed.
20. The semiconductor assembly of claim 10, wherein the first
semiconductor package is attachable to a motherboard via the second
level interconnect pads.
21. A semiconductor assembly, comprising: a first semiconductor
package including a first substrate and a first die having a
plurality of inter-package contact pads and a plurality of second
level interconnect (SLI) pads; a stiffener having a first plurality
of planar contact pads on the top side of the stiffener configured
to electrically connect the planar stiffener and a second die, and
a second plurality of planar contact pads on the bottom side of the
stiffener electrically connected to the inter-package contact pads
of the first package and a wire bond in contact with the second die
and electrically coupled to the first semiconductor package through
the stiffener; wherein the second die and the stiffener are stacked
on the first substrate; wherein the stiffener is configured to
electrically connect a second semiconductor package including the
stiffener and the second die; and wherein the second die is part of
a memory package.
22. The semiconductor assembly of claim 21, wherein the wire bond
is electrically coupled to the stiffener by direct contact to a
second substrate upon which the second die is disposed.
23. A semiconductor assembly, comprising: a first semiconductor
package including a first substrate and a first die having a
plurality of inter-package contact pads and a plurality of second
level interconnect (SLI) pads; a stiffener having a first plurality
of planar contact pads on the top side of the stiffener configured
to electrically connect the planar stiffener and a second die, and
a second plurality of planar contact pads on the bottom side of the
stiffener electrically connected to the inter-package contact pads
of the first package; a wire bond in contact with the second die
and electrically coupled to the first semiconductor package through
the stiffener; wherein the second die and the stiffener are stacked
on the first substrate; wherein the stiffener is configured to
electrically connect a second semiconductor package; and wherein
the second die is part of a memory package; and wherein the first
semiconductor package and the stiffener are electrically coupled
through a micro ball.
24. The semiconductor assembly of claim 23, wherein the first die
is part of a semiconductor logic package.
25. The semiconductor assembly of claim 23, wherein the first die
is part of a semiconductor logic package, and wherein the second
die is part of a memory package.
26. The semiconductor assembly of claim 23, wherein the first die
is part of a semiconductor logic package, and wherein the second
die is part of a cache unit.
27. The semiconductor assembly of claim 23, wherein the first die
is part of a semiconductor logic package, and wherein the second
die is part of a device package suited for connection with the type
of device of the first semiconductor package.
28. The semiconductor assembly of claim 23, wherein the wire bond
is electrically coupled to the stiffener by direct contact to a
second substrate upon which the second die is disposed.
29. A semiconductor assembly, comprising: a first semiconductor
package including a first die and a first substrate having a
plurality of inter-package contact pads and a plurality of second
level interconnect (SLI) pads; a planar stiffener having a first
plurality of planar contact pads on the top side of the stiffener
configured to electrically connect to a second semiconductor
package, and a second plurality of planar contact pads on the
bottom side of the stiffener electrically connected to the
inter-package contact pads of the first package; and a wire bond
that that is wire-bonded to a die in the second semiconductor
package.
30. The semiconductor assembly of claim 29, wherein the second die
is part of a memory package.
31. The semiconductor assembly of claim 29, wherein the second die
is part of a cache unit.
32. The semiconductor assembly of claim 29, wherein the second die
is part of a device package suited for connection with the type of
device of the first package.
33. The semiconductor assembly of claim 29, wherein the first die
is part of a semiconductor logic package.
34. The semiconductor assembly of claim 29, wherein the first die
is part of a semiconductor logic package, and wherein the second
die is part of a memory package.
35. The semiconductor assembly of claim 29, wherein the first die
is part of a semiconductor logic package, and wherein the second
die is part of a cache unit.
36. The semiconductor assembly of claim 29, wherein the first die
is part of a semiconductor logic package, and wherein the second
die is part of a device package suited for connection with the type
of device of the first package.
37. A semiconductor assembly, comprising: a first semiconductor
package including a first substrate and a first die having a
plurality of inter-package contact pads and a plurality of second
level interconnect (SLI) pads; a planar stiffener having a first
plurality of planar contact pads on the top side of the stiffener
configured to electrically connect a second semiconductor package
including the planar stiffener and a second die, and a second
plurality of planar contact pads on the bottom side of the
stiffener electrically connected to the inter-package contact pads
of the first package; and a wire bond in contact with the second
die and electrically coupled to the first semiconductor package
through the planar stiffener; wherein the second die and the planar
stiffener are stacked on the first substrate.
38. The semiconductor assembly of claim 37, wherein the second die
is part of a memory package.
39. The semiconductor assembly of claim 37, wherein the second die
is part of a cache unit.
40. The semiconductor assembly of claim 37, wherein the second die
is part of a device package suited for connection with the type of
device of the first package.
41. The semiconductor assembly of claim 37, wherein the first die
is part of a semiconductor logic package.
42. The semiconductor assembly of claim 37, wherein the first die
is part of a semiconductor logic package, and wherein the second
die is part of a memory package.
43. The semiconductor assembly of claim 37, wherein the first die
is part of a semiconductor logic package, and wherein the second
die is part of a cache unit.
44. The semiconductor assembly of claim 37, wherein the first die
is part of a semiconductor logic package, and wherein the second
die is part of a device package suited for connection with the type
of device of the first package.
Description
[0001] This is a Continuation application of Ser. No. 12/384,984
filed Apr. 10, 2009, which is presently pending.
FIELD
[0002] Embodiments of the invention relate to semiconductor
packaging technology. More particularly, embodiments of the
invention relate to a package-on-package interconnect
stiffener.
BACKGROUND
[0003] Mobile devices such as mobile phones, mobile internet
devices (MIDs) and laptops, are designed with smaller form factor
and slimmer profile for improved aesthetic and functional appeals.
The size of and real estate occupied by semiconductor packages in
the devices need to be scaled down accordingly. Package-on-package
(PoP) packaging technology is employed to stack a semiconductor
package on top of another semiconductor package to remove the x and
y dimensions constraints in the layout of semiconductor packages on
a motherboard.
[0004] PoP technology presents various problems, particularly with
respect to the original equipment manufacturer (OEM) process. One
of the problems is the limitation of cold surface to cold surface
solder reflow process. FIG. 1 is a cross-sectional view of a known
package-on-package (PoP) assembly. Bottom device package 150 may be
a core chip such as a microprocessor unit and includes die 170,
substrate 160, inter-package contact pads 155 on the top side of
bottom package 150, micro balls 180 attached to inter-package
contact pads 155, and second level interconnect pads 190 attachable
to a motherboard (not shown). Top device package 100 is stacked
onto bottom package 150 to form an electrical connection
therebetween. Top device package 100 may be a peripheral chip such
as a memory or cache unit, and may include die 120 interconnected
to substrate 110 via wire bond 130 and encapsulated by molding 125.
The bottom side of top device package 100 includes micro balls 140
reflowed and electrically connected to micro balls 180 on the top
side of bottom device package 150. During the OEM process, accurate
placement and reflow of top device package 100 on bottom device
package 150 are typically limited and difficult to control due to
the curved surfaces of micro balls 140, 180 and result in poor
stacking yield. Further, the pitch of micro balls 140 of top device
package 100 is limited by the pitch of micro balls 180 of bottom
device package 150. A change in the ball pitch of top device
package 100 necessitates a change in the ball pitch of the bottom
device package 150 and vice versa.
[0005] Another problem typically associated with PoP packaging is
the coefficient of thermal expansion (CTE) mismatch between top
device package 100 and bottom device package 150. The CTE mismatch
is due to the fact that top device package 100 and bottom device
package 150 are made from different materials and undergo different
rates of thermal expansion in an elevated temperature range. The
different rates of expansion and contraction result in warpage of
the PoP assembly. Warpage of the PoP assembly presents process
challenges in the package stacking process step and quality of
joint formation between top device package 100 and bottom device
package 150. Intrinsic stresses accumulated in the solder joints
between the packages may risk quality and reliability failures
during the use of the device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Embodiments of the invention are illustrated by way of
example and not limited in the figures of the accompanying
drawings, in which like references indicate similar elements.
[0007] FIG. 1 is a cross-sectional view of a known
package-on-package (PoP) assembly.
[0008] FIG. 2 is a cross-sectional view of a package-on-package
(PoP) assembly having an interconnect stiffener according to an
embodiment.
[0009] FIG. 3 is an exploded perspective view of a PoP assembly
having an interconnect stiffener according to an embodiment.
[0010] FIG. 4 is an exploded perspective view of a top device
package and a bottom device package having an interconnect
stiffener attached to the top side of the bottom device package
according to an embodiment.
[0011] FIG. 5 is a perspective view of an assembled PoP assembly
having a top device package and a bottom device package attached to
an interconnect stiffener according to an embodiment.
[0012] FIG. 6 is a cross-sectional view of a PoP interconnect
stiffener according to an embodiment.
[0013] FIG. 7 is a cross-sectional view of a PoP interconnect
stiffener according to another embodiment.
[0014] FIG. 8 is a flowchart of a method of fabricating a PoP
assembly having an interconnect stiffener according to an
embodiment.
DETAILED DESCRIPTION
[0015] Embodiments of the invention relate to a package-on-package
(PoP) assembly comprising a top device package and a bottom device
package interconnected by way of an electrically interconnected
planar stiffener. Embodiments include a planar stiffener having
contact pads on the bottom side attached to a bottom device
package, and contact pads on the top side of the stiffener to
receive a top device package. Embodiments of the invention include
a first semiconductor package having a plurality of inter-package
contact pads and a plurality of second level interconnect (SLI)
pads; a second semiconductor package having a plurality of SLI pads
on the bottom side of the package; and a planar stiffener having a
first plurality of planar contact pads on the top side of the
stiffener electrically connected to the SLI pads of the second
package, and a second plurality of planar contact pads electrically
connected to the inter-package contact pads of the first package.
Embodiments of the invention provide reliable electrical
interconnection and warpage control between the top device package
and the bottom device package.
[0016] FIG. 2 is a cross-sectional view of a package-on-package
(PoP) assembly having an interconnect stiffener according to an
embodiment. The PoP assembly is attachable to a motherboard (not
shown) via second level interconnect pads 190 disposed on the
bottom side of bottom device package 150. The PoP assembly includes
bottom device package 150 interconnected to planar interconnect
stiffener 200. Bottom device package 150 may be any semiconductor
package depending on the application. For example, bottom device
package 150 may be a semiconductor logic package, an application
processor, or a memory package with an integrated circuit in die
170. Planar stiffener 200 includes a plurality of planar contact
pads 210 disposed on the top side of stiffener 200. Planar contact
pads 210 are configured to be electrically connected to top device
package 100, for example, by way of micro balls 140. Top device
package 100 may be a memory package or cache unit or any other
device package suited for connection with the type of device of
bottom device package 150. Planar stiffener 200 also includes a
plurality of planar contact pads 240 disposed on the bottom side of
stiffener 200. In the PoP assembly, planar contact pads 240 are
electrically connected to bottom device package 150, for example,
by way of micro balls 180.
[0017] FIG. 3 is an exploded perspective view of a PoP assembly
having an interconnect stiffener according to an embodiment. Planar
interconnect stiffener 200 includes substrate 220 defining a
through recess 330 adapted to house die 170 of bottom device
package 150. Stiffener 200 also includes small through openings
through which planar contact pads 210 and 240 are formed. Planar
contact pads 210 and 240 formed on substrate 220 each includes a
solder-wettable surface finish so that during reflow, the solder
materials of micro balls 140 and 180 can melt, wet and form
permanent conductive connection between stiffener 200 and the top
and bottom packages 100, 150. Various types of solder-wettable
surface finish known in the art such as Electroless
Nickel/Immersion Gold (ENIG), ENIG+Electroless Gold (ENIG+EG) and
Nickel-Palladium-Gold (NiPdAu) are suitable for planar contact pads
210 and 240.
[0018] FIG. 4 is an exploded perspective view of a top device
package and a bottom device package having an interconnect
stiffener attached to the top side of the bottom device package
according to an embodiment. Stiffener 220 is attached to bottom
device package 150 via respective contact pads 155 and 240. Planar
contact pads 240 disposed on the bottom side of stiffener 220 are
connected to inter-package contact pads 155 of bottom device
package 150 by way of conductive micro balls 180. Stiffener 220 may
be attached to bottom device package 150 before attaching top
device package 100 to the top side of stiffener 220. The layout of
planar contact pads 240 on the bottom side of stiffener 220 may
match the layout of inter-package contact pads 155 of bottom device
package 150. However, the layout of planar contact pads 240 on the
bottom side of stiffener 220 is not precluded to be different from
the layout of planar contact pads 210 on the top side of stiffener
220.
[0019] FIG. 5 is a perspective view of an assembled PoP assembly
having a top device package and a bottom device package attached to
an interconnect stiffener according to an embodiment. Top device
package 100 is connected to stiffener 220 via interconnects such as
micro balls 140 disposed on planar contact pads 210 on the top side
of stiffener 220. FIG. 5 shows an embodiment of assembled PoP with
the width and length dimensions of top device package 100
substantially the same with the respective dimensions of stiffener
220. However, stiffener 220 is not precluded to have other
dimensions relative to top device package 100 and bottom device
package 150.
[0020] FIG. 6 is a cross-sectional view of a PoP interconnect
stiffener according to an embodiment. Stiffener 200 includes
substrate 220 to provide structural support and upon which contact
pads 210, 240 are fabricated. Stiffener 200 includes solder resist
layer 620 disposed on the top surface and bottom surface of core
layer 630. For an embodiment, core layer 630 is a cored substrate
fabricated from known polymeric materials such as bismaleimide
triazine (BT), polyimide, and liquid crystalline (LC) polymer.
However, other materials suitable for core layer 630 are not
precluded in other embodiments of the invention. Substrate 220 may
include a coefficient of thermal expansion (CTE) of approximately
between 15 and 25 ppm. Substrate 220 may also include a flexural
modulus of approximately between 15 and 30 GPa. The properties of
stiffener 200 will be designed to provide acceptable end-of-line
warpage of the assembly of top device package 100 and stiffener 200
and/or the reliability of the interconnections between top device
package 100 and stiffener 200.
[0021] Stiffener 200 also includes conductive traces 600 fabricated
in substrate 220 to electrically interconnect planar contact pads
210 on the top side of stiffener 220 with planar contact pads 240
on the bottom side of stiffener 220. FIG. 6 illustrates a
via-in-pad design in which plug material 610 is disposed between
core layer 630 and between planar contact pads 210, 240. Plug
material 610 forms part of the material for substrate 220 to
provide structural rigidity and foundation to contact pads 210 and
240 and is made from known materials such as silica filled epoxy
composite or commercially available solder resist materials.
Stiffener 220 may also include routing features accommodating
various circuitry designs of top device package 100. Hence, the
circuitry laid in substrate 160 of bottom device package 150 needs
not be redesigned every time when top device package 100 of
different circuitry layout is paired with bottom device package
150. Stiffener 200 may include adhesive 640 laminated on solder
resist layer 620 on the bottom side of stiffener 200 to adhere
stiffener 200 to the top surface of bottom device package 150.
Adhesive 640 may be any type of known adhesive having a low glass
transition temperature (T.sub.g), for example between 90 and
180.degree. C., such that adhesive 640 is cured below the typical
solder reflow temperature range of 220-260.degree. C.
[0022] FIG. 7 is a cross-sectional view of a PoP interconnect
stiffener according to another embodiment. FIG. 7 embodies a
via-off-pad design in which core layer 630 extends in planar
contact pads 210 and 240 regions, and plug material 610 is disposed
between solder resist layers 520 and in substrate 220. Other
designs of substrate 220 are not in precluded in other embodiments
of the invention.
[0023] FIG. 8 is a flowchart of a method of fabricating a PoP
assembly having an interconnect stiffener according to an
embodiment. Bottom device package 150 having inter-package contact
pads 155 on the top side of the package and second level
interconnect (SLI) pads 190 on the bottom side of the package is
provided. Bottom device package 150 may be in the form of
individual package or multiple packages connected in a panel form.
In operation 700, micro balls 180 are placed on inter-package
contact pads 155 of bottom device package 150 and reflowed to form
solder interconnection. In operation 710, planar stiffener 200 is
fabricated from core layer 630 material. Stiffener 200 may be
formed in a panel form from which individual stiffener 200 units
may be obtained after singulation. Known process to fabricate
package substrate may be used to form stiffener 200 and the key
process steps may include: drilling through-holes in core layer
630; plating the sidewalls of through-holes; disposing plug
material 610 in the through-holes; forming electrically conductive
planar contact pads 210 and 240; forming a solder-wettable finish
on planar contact pads 210 and 240; and forming recess 330 in
stiffener 200.
[0024] In operation 720 (FIG. 8), planar stiffener 200 is mounted
on the top side of bottom device package 150. Planar contact pads
240 on the bottom side of stiffener 200 are aligned and attached to
micro balls 180 connected to inter-package contact pads 155 of
bottom device package 150. The assembly of stiffener 200 and bottom
device package 150 are reflowed to form permanent interconnection.
After reflow, die 170 is attached to bottom device package 150
attached to stiffener 200. The assembly of bottom device package
150 and stiffener 200 (in panel form) may then be singulated to
yield individual assemblies of bottom device package 150 with
stiffener 200 attached thereto. Top device package 100 may
subsequently be attached to planar contact pads 210 on the top side
of stiffener 200 to form a package-on-package assembly.
[0025] Embodiments of the invention provide a device package
electrically interconnected with an interconnect stiffener upon
which another device package can be mounted and electrically
connected to form a package-on-package assembly. The stiffener in
the package-on-package assembly provides the necessary stiffness to
the assembly for improved warpage control and the platform on which
a top device package can be attached with greater process
control.
[0026] In the foregoing specification, reference has been made to
specific embodiments of the invention. It will, however be evident
that various modifications and changes may be made thereto without
departing from the broader spirit and scope of the invention. The
specification and drawings are, accordingly, to be regarded in an
illustrative rather than restrictive sense.
* * * * *