U.S. patent application number 13/410386 was filed with the patent office on 2012-06-28 for method and device for identifying and implementing flexible logic block logic for easy engineering changes.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Robert D. HERZL, Robert S. HORTON, Kenneth A. LAURICELLA, David W. MILTON, Clarence R. OGILVIE, Paul M. SCHANELY, Nitin SHARMA, Tad J. WILDER, Charles B. WINN.
Application Number | 20120167022 13/410386 |
Document ID | / |
Family ID | 40851802 |
Filed Date | 2012-06-28 |
United States Patent
Application |
20120167022 |
Kind Code |
A1 |
HERZL; Robert D. ; et
al. |
June 28, 2012 |
METHOD AND DEVICE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC
BLOCK LOGIC FOR EASY ENGINEERING CHANGES
Abstract
A chip design methodology and an integrated circuit chip. The
methodology includes identifying engineering changeable logic, and
replacing the identified engineering changeable logic with flexible
logic blocks (FLB).
Inventors: |
HERZL; Robert D.; (South
Burlington, VT) ; HORTON; Robert S.; (Colchester,
VT) ; LAURICELLA; Kenneth A.; (Colchester, VT)
; MILTON; David W.; (Underhill, VT) ; OGILVIE;
Clarence R.; (Huntington, VT) ; SCHANELY; Paul
M.; (Essex Junction, VT) ; SHARMA; Nitin;
(South Burlington, VT) ; WILDER; Tad J.; (South
Hero, VT) ; WINN; Charles B.; (Colchester,
VT) |
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
Armonk
NY
|
Family ID: |
40851802 |
Appl. No.: |
13/410386 |
Filed: |
March 2, 2012 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
12014240 |
Jan 15, 2008 |
8181148 |
|
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13410386 |
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Current U.S.
Class: |
716/103 |
Current CPC
Class: |
G06F 30/30 20200101 |
Class at
Publication: |
716/103 |
International
Class: |
G06F 9/45 20060101
G06F009/45 |
Claims
1. A chip design methodology comprising: identifying engineering
changeable logic; and replacing the identified engineering
changeable logic with flexible logic blocks (FLB).
2. The chip design methodology in accordance with claim 1, wherein
the identifying engineering changeable logic includes tagging logic
related to at least one of: new or asynchronous interfaces; new
functions; an inexperienced designer; late date design changes; low
verification coverage; and bug fixes made to the logic.
3. The chip design methodology in accordance with claim 2, further
comprising: prioritizing the tagged logic; and replacing the tagged
logic with flexible logic blocks according to the prioritizing.
4. The chip design methodology in accordance with claim 1, wherein
the identified engineering changeable logic is replaced with
flexible logic blocks using synthesis directives or synthesis
script of a synthesis tool.
5. The chip design methodology in accordance with claim 1, wherein
the identified engineering changeable logic is replaced with
flexible logic blocks using an FLB library of a post-processing
tool.
6. The chip design methodology in accordance with claim 1, further
comprising: saving a netlist of design logic; and comparing the
saved netlist to a subsequent netlist, wherein at least one of a
new function, a non-equivalent function, a new design, or part of a
fix is identified as engineering changeable logic to be replaced
with flexible logic blocks.
7. The chip design methodology in accordance with claim 1, further
comprising: copying the identified engineering changeable logic to
obtain original identified engineering changeable logic and copy
identified engineering changeable logic, wherein the identified
engineering changeable logic replaced with flexible logic blocks
comprises the copy identified engineering changeable logic; and
selecting at least one of the original identified engineering
changeable logic and the copy identified changeable logic replaced
with flexible logic blocks.
8. The chip design methodology in accordance with claim 7, wherein,
when more flexibility is desired, the method further comprises
converting at least some of the original engineering changeable
logic to flexible logic blocks.
9. An integrated circuit chip, comprising: a device for identifying
engineering changeable logic; and a replacing device for replacing
the identified engineering changeable logic with flexible logic
blocks (FLB).
10. The integrated circuit chip in accordance with claim 9, wherein
the replacing device comprises a synthesizing tool.
11. The integrated circuit chip in accordance with claim 9, wherein
the replacement device comprises a post-processing tool.
12. The integrated circuit chip in accordance with claim 9, wherein
the device for identifying engineering changeable logic comprises a
device to tag logic related to at least one of: new or asynchronous
interfaces; new functions; inexperienced designer; late date design
changes; low verification coverage; and bug fixes made to the
logic.
13. The integrated circuit chip in accordance with claim 9, wherein
the identified engineering changeable logic comprise cones of logic
having a plurality of outputs of which at least one of outputs
requires a change.
14. The integrated circuit chip in accordance with claim 9, further
comprising: a first netlist of design logic; a subsequent netlist;
and a comparison unit for comparing the first netlist to the
subsequent netlist, wherein at least one of a new function, a
non-equivalent function, a new design, or part of a fix is
identified as engineering changeable logic to be replaced with
flexible logic blocks.
15. The integrated circuit chip in accordance with claim 14,
wherein the comparison unit comprises a logical equivalency testing
tool.
16. The integrated circuit chip in accordance with claim 9, wherein
the device for identifying engineering changeable logic comprises a
device to tag logic related to new or asynchronous interfaces.
17. The integrated circuit chip in accordance with claim 9, wherein
the device for identifying engineering changeable logic comprises a
device to tag logic related to new functions.
18. The integrated circuit chip in accordance with claim 9, wherein
the device for identifying engineering changeable logic comprises a
device to tag logic related to late date design changes.
19. The integrated circuit chip in accordance with claim 9, wherein
the device for identifying engineering changeable logic comprises a
device to tag logic related to low verification coverage.
20. The integrated circuit chip in accordance with claim 9, wherein
the device for identifying engineering changeable logic comprises a
device to tag logic related to bug fixes made to the logic.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a divisional application of
co-pending U.S. application Ser. No. 12/014,240, filed on Jan. 15,
2008, the contents of which are incorporated by reference herein in
their entirety.
FIELD OF THE INVENTION
[0002] A method and device for forming an application specific
integrated circuit (ASIC), in particular, in response to
engineering changes.
BACKGROUND OF THE INVENTION
[0003] An application specific integrated circuit (ASIC) is an
integrated circuit designed or customized for a specific use or
task. Generally, a customer or client requests a manufacturer or
ASIC design center to fabricate an ASIC to perform specific logic.
The customer may provide a "netlist," which represents the desired
logic operation for the application, or some other representation
of the logic for performing the desired task to a designer or
engineer. The designer or engineer takes the customer's logic and
synthesizes it into gate logic. This gate logic is then placed and
routed to form a physical design of the chip, which can take, e.g.,
many weeks to months to complete.
[0004] During the placing and routing procedure, it is not unusual
for the customer to request engineering changes for the logic,
e.g., in an effort to improve the ASIC functionality. In this
regard, it can be difficult, after logic synthesis and the initial
physical design process, to change the placed and routed gate
logic. As a result, incorporating the engineering changes into the
ASIC may generally result in a very complicated and lengthy ordeal
for the designer/engineer. Moreover, gate logic cannot generally
simply be replaced, since changing gate logic can result in
different timing characteristics between the gates that must also
be considered in the new gate logic.
[0005] The underlying obstacles to putting in engineering changes
to a chip have for a long time plagued designers. From distilling
down the minimal change in a netlist (when the change was made to
register transfer logic (RTL)) to rewiring gates on an existing
placement the change is always a timely complicated process and
does not lend itself to automation.
[0006] Functional logic blocks (FLBs) can be used in place of
standard cell logic gates in order to enable easy changes to
functional blocks with wire, as discussed in commonly owned U.S.
application Ser. No. 11/838,929 filed Aug. 15, 2007, the disclosure
of which is expressly incorporated by reference herein in its
entirety. The function can be implemented with a separate library
of simple logic, e.g., NAND gates and NOR gates, where the simple
logic blocks are built up from higher complexity block, e.g., AOIs
with inputs tied up and down inside the library block to create the
simpler logic function. This would enable additional logic that can
be easily changed in the existing logic path.
SUMMARY OF THE INVENTION
[0007] According to an aspect of the invention, a chip design
methodology includes identifying engineering changeable logic, and
replacing the identified engineering changeable logic with flexible
logic blocks.
[0008] In accordance with another aspect of the invention, a device
for forming an integrated circuit chip includes a device for
identifying engineering changeable logic, and a replacing device
for replacing the identified engineering changeable logic with
flexible logic blocks.
[0009] According to still another aspect of the invention, a method
for chip design includes receiving a first netlist, receiving a
subsequent netlist composed of engineering logic changes,
identifying the engineering logic changes made since the first
netlist, and replacing at least one of the engineering logic
changes with a flexible logic block.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The present invention is described in the detailed
description which follows, in reference to the noted plurality of
drawings by way of non-limiting examples of exemplary embodiments
of the present invention.
[0011] FIG. 1 illustrates an exemplary physical structure for an
application specific integrated circuit (ASIC) chip according to an
embodiment of the invention;
[0012] FIG. 2 illustrates examples of normal ASIC gates and
suitable replacement flexible logic blocks (FLBs) in accordance
with the invention;
[0013] FIG. 3 illustrates an exemplary flow diagram for performing
an embodiment of the invention;
[0014] FIG. 4 illustrates an exemplary flow diagram for changing
cones of logic to FLBs and/or providing redundant FLBs for
identified cones;
[0015] FIG. 5 illustrates a non-limiting exemplary flow diagram of
operation of the illustration depicted in FIG. 4; and
[0016] FIG. 6 illustrates an exemplary flow diagram of a netlist
comparison method.
DETAILED DESCRIPTION OF THE EMBODIMENTS OF THE INVENTION
[0017] The cost of using FLBs in place of simple logic can be quite
expensive. Accordingly, the invention is directed to a method of
identifying logic to be implemented in flexible logic blocks (FLBs)
and a device for implementing the method in forming a chip, e.g.,
an application specific integrated circuit (ASIC). Further, while
starting logic can be from a variety of sources, e.g., RTL for the
chip, third party vendor provided RTL or netlists, FLBs can be used
with all sources according to the invention.
[0018] FIG. 1 illustrates the physical structure of an application
specific integrated circuit (ASIC) structure according to the
invention. As shown, flexible logic blocks (FLBs) 11 can be
distributed or sprinkled across chip 10 with normal ASIC logic 12,
e.g., in a regular array or predefined pattern. FLBs 11 and normal
(standard) ASIC logic 12 can be interconnected (not shown) on chip
10 in order to perform the desired logic of the ASIC.
Alternatively, regions of the chip 10 can be identified for
utilizing FLBs 11 to be interconnected with normal ASIC logic 12 in
such regions and throughout chip 10 to perform the desired ASIC
functionality.
[0019] FLBs are enhanced logic function gates with at least one
additional function wired to be initially deactivated, e.g.,
through extra tied inputs tied to ground. Thus, regions of the chip
can be identified in order to arrange FLBs 11 across chip 10 or in
the identified region of chip 10 to be interconnected with the
normal ASIC logic and yet allow for easy changes to their function
and operation. Further, to facilitate the late changes to the
design, e.g., after the chip 10 has been placed and routed, these
regions likely to require late changes can be identified in order
to replace the standard logic with FLBs 11 having used and unused
logic gates. Because of the unused or deactivated functions
associated with the FLBs, the use of FLBs 11 allow for engineering
changes to the ASIC logic, even if not made until late in the
design cycle. Moreover, the engineering changes can be effected
through wire only changes, thereby avoiding timing problems
generally associated with replacing and/or adding logic gates to
the chip.
[0020] The use of FLBs 11 and their associated reconnection
techniques to utilize initially unused logic allow changes to be
easily made to FLB function even after the chip is manufactured.
Wiring to and from FLBs 11 can stretch around chip 10 or the
predefined region of chip 10 to enable easy connections to and from
other standard ASIC function placed and wired on chip 10. Further,
for ease of modifying the logic, it may be advantageous to build
much of the original logic function on chip 10 from FLBs 11.
[0021] ASIC chips are generally requested by a customer who
provides a "netlist" representing the desired logic for the
application to be performed. The manufacturer of the chip can
synthesize gate logic from the customer netlist, which can be
formed in, e.g., register transfer logic (RTL). As the cost for
FLBs can be greater than the cost for the simple logic it replaces,
it can be advantageous to identify the logic likely to be subject
to subsequent engineering changes.
[0022] Moreover, FLBs can also be synthesized, placed and routed in
place of normal ASIC gates in areas of the chip identifiable as
engineering changeable, e.g., in which new functions, changed
functions, new hardware, or bug fixes have been made. In this
event, such FLB gates may have some of inputs and outputs wired to
perform the functioning logic of the normal ASIC gate and have
additional inputs, and perhaps even outputs, that are at least
initially appropriately tied off so the FLB functions as the normal
ASIC gate it replaces. With this design, should a change, e.g., an
engineering change, be required or requested by the customer or
designer later in the design cycle, e.g., after placing and
routing, the FLB can replace the standard logic so the function of
the FLB can be easily changed or effected through wire only changes
to the inputs and/or outputs of the FLB.
[0023] After a piece of logic or a specific area of the chip has
been identified, the specific gates of this identified logic (risky
or normal) or area can be isolated and synthesized or formed with
FLBs or combinations of FLBs and normal logic gates. As noted
above, while FLBs can be very complex functions, e.g., programmable
MUX structures, NAND and NOR gates with and/or inverted gates
(AOIs) with appropriately tied off inputs, they can change their
function through a mere change of wiring. Moreover, it may be
advantageous to arrange the tied inputs on metal layers where they
can be accessed and, therefore, easily changed. FIG. 2 illustrates
examples of normal ASIC gates and suitable replacement FLBs that
can be used in place them.
[0024] By way of non-limiting example, FIG. 2 illustrates a normal
or standard logic block and a suitable replacement FLB at least
initially wired to function as the normal logic block it can
replace. According to an aspect of the invention, a standard NAND
gate 21 having inputs A and B can be replaced with an FLB formed of
an AND gate 22 with inputs A and B and an output coupled to an OR
inverted gate 23. Another AND gate 24 has inputs tied to ground and
an output coupled to the OR inverted gate 23. Also, NAND gate 21
can be formed as an AND-OR inverted (AOI) in which AND gate 25 has
inputs A and B and 1'b1 and an output coupled to OR inverted gate
26. The other input to OR inverted gate 26 is tied to ground.
According to another aspect of the invention, a standard AND gate
31 having inputs A and B can be replaced with an FLB formed of an
AND gate 32 with inputs A and B and an output coupled to an OR gate
33. Another AND gate 34 has inputs tied to ground and an output
coupled to the OR gate 33. Also, AND gate 31 can be formed as by
AND gate 35 having inputs A and B and 1. Moreover, standard OR gate
41 having inputs A and B can be replaced with an AND gate 42 with
inputs A and B'1' and an output coupled to an OR gate 43. Another
AND gate 44 has inputs B and B'1' and an output coupled to the OR
gate 43. It is understood that additional and even more complicated
FLBs can be formed for replacing standard logic blocks without
departing from the spirit and scope of the invention. Further,
while FIG. 2 illustrates exemplary basic standard logic block, it
is understood other FLBs can be designed and initially wired for
replacing other standard logic blocks that have not been
illustrated here without departing from the scope and spirit of the
invention.
[0025] As shown in the illustrations of the replacement FLB in FIG.
2, the inputs and outputs of the FLBs are initially wired not only
to perform the functioning logic of the normal ASIC gate it
replaces but also to include additional inputs, and perhaps even
outputs, that are appropriately tied off, e.g., to ground. As
discussed above, this design allows for easy alteration of the
functioning of the FLBs through the wiring of the gates. Should a
change, e.g., an engineering change, be required later in the
design cycle, e.g., after placing and routing, the function of the
FLB or the inputs and/or outputs of the FLB can be easily added to
or changed with wire only changes.
[0026] During design and implementation of a chip, FLBs can be
used, e.g., to fix late-found bugs. Further, logic identifiable as
highly probable for engineering changes or for replacement with
FLBs can be tagged by, e.g., identifying synthesis directives in
the source code (RTL); identifying hierarchy in design (named
block, unit instance name); start and/or endpoint cones of logic;
identifying dataflow and tagging non-dataflow; and tracking changes
using logical equivalency checking between a chip netlist and a
previous version of that netlist. Cones of logic changed are new
function/bug fixes and therefore high-risk engineering change
areas.
[0027] FIG. 3 shows a flow diagram 300 for an FLB RTL substitution
flow according to the invention. The initial RTL logic can be
created from a customer's desired logic for the chip application or
netlist. From the design RTL, the application specifications,
designer's insight, and units and/or subunits of the logic can be
analyzed at step 301. At step 302, a determination is made whether
the logic is at least one of a new or asynchronous interface. If
yes, the logic can be tagged or flagged for implementation as an
FLB at step 303.
[0028] The tag function can be implemented through a synthesis tool
or a post-processing tool. Thus, the logic can be tagged in the
source code (RTL) with a direct synthesis tool to implement logic
with FLBs until instructed otherwise, or the logic can also be
tagged with a synthesis script, e.g., as a table in a post
processing tool to replace logic with FLB books.
[0029] If no, a determination is made at step 304 whether the logic
relates to a new function. In this regard, if the function has not
been used before, it may be prone to error and, therefore,
necessitate subsequent engineering changes. If a new function, the
logic is tagged or flagged for implementation as an FLB at step
305. If not a new function, a determination is made at step 306
whether the designer is inexperienced, because inexperienced
designers may be more likely than experienced designers to have
mistakes in their logic. Therefore, if designed by an inexperienced
designer, the logic can be tagged or flagged for implementation as
an FLB at step 307, otherwise a determination is made at step 308
whether it is a late date for design change. This can be
significant since the logic may not have been tested or not fully
tested. If a late date for design change is identified, the logic
can be tagged or flagged for implementation as an FLB at step 309.
If not, a determination can be made at step 310 if verification
coverage is low, as this can be difficult to test. If verification
coverage is low, the logic can be tagged or flagged for
implementation as an FLB at step 311. Otherwise, a determination is
made at step 312 if bug fixes have been made in this logic. If such
fixes have been made, the logic may be tagged or flagged to be
implemented as an FLB at step 313. Thereafter, the tagged or
flagged FLBs can be ranked according to a priority assignment at
step 314.
[0030] A priority tag related to a relative importance of the
tagged engineering changeable parameter can be utilized to identify
which logic is more desirable to target for FLB implementation.
Priority can be assigned to various methods for identifying where
to use FLBs, e.g., priority may be inversely proportional to
verification coverage, since logic areas with low verification
coverage are more likely to require engineering changes; designer
or verifier experience; interface regions, e.g., asynchronous,
between major blocks, between new functions, etc.; dates and days
of development and verification; history of the logic function,
e.g., range of new function to previously used on other chips; and
feedback from logic bug reports, which can be mapped across the
entire logic. In the process of designing a chip, simulation
typically progresses with the bug fix rate decreasing
exponentially. If a log, kept for all bugs encountered and fixed,
is mapped over the logic, it could be used as an indicator of
entities needing implementation in FLBs and as an indicator of
future bug likelihood.
[0031] The FLB gates can be synthesized where tagged or flagged and
meeting constraints at step 315 or can be synthesized using normal
library at step 316 to post process the FLB gates where tagged or
flagged and meeting constraints. If the amount of logic targeted
for replacement with FLBs exceeds chip area/power/timing
constraints, it may be advantageous to back-off replacement of
changeable logic with FLBs. However, synthesis would use these
priority tags to make appropriate trade-off between
area/power/timing and engineering changeability. Thereafter, the
FLB netlist is optimized at step 317.
[0032] In step 315, the tags/flags can be put on the logic
structures in the form of synthesis directives or synthesis script
in comments in the RTL source code to synthesize the tagged blocks
with FLB gate libraries as the target block, i.e., FLB targeted
logic can be isolated into separate logic files, and synthesized
using minimal blocks like NANDs and NORs. Further, the synthesis
tool can be used to target a source or sink of cones by flop names
identified by the logic designer to target the FLB gate library as
the target library. With regard to cones, the start of a cone can
be a point in the logic where the signal fans out, and the
endpoints of the cone can be an output signal or latch. More
particularly, inputs that can be cause an output to change can
funnel down to a single point or expand from a single point.
[0033] In step 316, tagged blocks can be post-processed as FLB gate
libraries. FLB targeted logic can be synthesized using minimal
logic blocks, such as AOIs or muxes, with additional tied input
lines. Alternatively, a targeted block can be synthesized with an
FLB gate library as the target library, which allows changes in
wire only. Further, the post-processing tool can be used to target
flops/POs/PIs as a source or sink of cones of logic to replace
simple NAND/NOR logic with FLB gates.
[0034] Moreover, according to a further aspect of the invention,
data flow, e.g., adders, multiplexers, etc., can be identified,
whereby non-data flow (control logic) can be targeted for FLB
logic. As control logic is not typically easily identified, the
method according to this aspect of the invention can identify data
flow, e.g., from a netlist, and all unidentified logic can be
considered as changeable logic.
[0035] Further, FIG. 4 illustrates a flow diagram for changing
cones of logic to FLBs and/or providing redundant FLBs for
identified cones of logic. According to an implementation of the
inventive method, cones of logic that may require engineering
changes can be formed of standard cell gates to be replaced by FLB
gates. This may allow logic changes to be made only by changing
wires. Moreover, some engineering changes may require that the
original function of the logic remain intact for some logic cones
while others require the change. Thus, the flow diagram of FIG. 4
can be used when a logic change is needed to fix a bug, but
downstream logic may need the function of the logic to be
unchanged. By way of non-limiting example, cone in element 410 can
be coupled to a cone out element 411 through a parallel arrangement
of a standard ASIC library 412 and a special purpose library 413
connected to a selector 414. Selector 414 can be any known selector
device, e.g., a multiplexer, arranged to select one or both of the
libraries, whereby an FLB can be selected to replace the standard
ASIC logic or an FLB can be selected to be arranged in parallel
with the standard ASIC logic to provide redundant logic between
cone in element 410 and cone out element 411. In an example of the
illustrated embodiment, cone in element 410 can include inputs A
and B and cone out element 411 can include outputs C, D, and E. If
it is determined that to fix a bug in the logic output D needs an
input F (not shown), the selector can select a redundant FLB with
input F, while outputs C and E remain unchanged with inputs A and
B.
[0036] FIG. 5 illustrates a non-limiting exemplary flow diagram of
operation of the illustration depicted in FIG. 4. As shown, the RTL
logic is implemented in step 501. At step 502, the engineering
changeable logic is identified and extracted, e.g., via synthesis
directives or synthesis script. At step 503, the stable or
non-changeable logic is synthesized to gates, while changeable
logic is synthesized to gates at step 504. The changeable logic is
copied at step 505 to produce original changeable RTL logic at step
506 and a copy of the changeable RTL logic at step 507. The copy of
the changeable RTL logic, which is redundant with respect to the
original changeable RTL logic, can be converted into FLB gates at
step 508. At step 509, a determination is made whether more
flexibility is needed in the original changeable RTL logic. If more
flexibility is needed, the original changeable RTL logic can be
converted to FLB gates at step 510, otherwise, no further action on
the original changeable RTL logic is necessary. The gate logic from
steps 503, 508 and 509/510 can be merged, e.g., with a multiplexer
or other selection device, at step 511 into merged logic at step
512.
[0037] According to still another aspect of the invention, a
non-limiting example of a netlist comparison method is depicted in
FIG. 6, in which a post-synthesis replacement of standard cell
logic in the netlist with FLB logic is based on logic cones that
are no longer equivalent to a previous netlist. Thus, FIG. 6
depicts a flow diagram to identify high risk parts of a netlist to
be implemented with FLBs, yet does not require RTL source code, but
can be implemented through netlists provided to the ASIC vendor. At
step 601, a netlist is delivered to the ASIC vendor by the
customer, and a determination is made at step 602 whether the
delivered netlist is the first drop of the netlist. If the first
drop, the netlist is saved as a base level at step 603 and no logic
is targeted for FLBs. As successive netlists are delivered to the
ASIC vendor from the customer, the ASIC vendor can compare the
netlists to identify where the customer is making bug fixes or to
identify new functions. By way of example, a subsequent netlist
release can include most of the customer's design being submitted
for a first analysis of what the chip may look like. Another
subsequent netlist release can include a final output of synthesis
in order to analyze timing and/or performance of the chip. Still
another subsequent netlist release can be the last netlist received
from the customer.
[0038] When the delivered netlist is not the first drop, a logical
equivalency testing (LEQ) tool is run at step 604 between the new
netlist and the saved base level netlist in order to identify new
function, changed functions, bug fixes, etc. At step 605, new cones
for FLB substitution can be targeted, e.g., new function or part of
a fix, and non-equivalent cones for FLB substitution can be
targeted, e.g., new design (which may or may not be proven logic).
A percentage of logic (based on chip constraints, design history,
etc.) can be selected in the targeted cones for FLB substitution at
step 606.
[0039] The circuit as described above is part of the design for an
integrated circuit chip. The chip design is created in a graphical
computer programming language, and stored in a computer storage
medium (such as a disk, tape, physical hard drive, or virtual hard
drive such as in a storage access network). If the designer does
not fabricate chips or the photolithographic masks used to
fabricate chips, the designer transmits the resulting design by
physical means (e.g., by providing a copy of the storage medium
storing the design) or electronically (e.g., through the Internet)
to such entities, directly or indirectly. The stored design is then
converted into the appropriate format (e.g., GDSII) for the
fabrication of photolithographic masks, which typically include
multiple copies of the chip design in question that are to be
formed on a wafer. The photolithographic masks are utilized to
define areas of the wafer (and/or the layers thereon) to be etched
or otherwise processed. Moreover, the process as described above is
used in the fabrication of integrated circuit chips.
[0040] The resulting integrated circuit chips can be distributed by
the fabricator in raw wafer form (that is, as a single wafer that
has multiple unpackaged chips), as a bare die, or in a packaged
form. In the latter case the chip is mounted in a single chip
package (such as a plastic carrier, with leads that are affixed to
a motherboard or other higher level carrier) or in a multichip
package (such as a ceramic carrier that has either or both surface
interconnections or buried interconnections). In any case the chip
is then integrated with other chips, discrete circuit elements,
and/or other signal processing devices as part of either (a) an
intermediate product, such as a motherboard, or (b) an end product.
The end product can be any product that includes integrated circuit
chips, ranging from toys and other low-end applications to advanced
computer products having a display, a keyboard or other input
device, and a central processor.
[0041] While the invention has been described in terms of a
preferred embodiment, those skilled in the art will recognize that
the invention can be practiced with modifications within the spirit
and scope of the appended claims.
* * * * *