Milton; David W.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Milton; David W..The latest application filed is for "chip performance monitoring system and method".

Company Profile

2.41.39

Milton; David W. - Underhill VT US
Milton; David W. - US
Milton; David W. - Middletown OH

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Critical path delay prediction Grant 10,169,500 - Charlebois , et al. J	2019-01-01
Chip performance monitoring system and method Grant 10,006,964 - Charlebois , et al. June 26, 2	2018-06-26
Chip Performance Monitoring System And Method App 20160231379 - Charlebois; Margaret R. ; et al.	2016-08-11
Chip performance monitoring system and method Grant 9,383,766 - Charlebois , et al. July 5, 2	2016-07-05
Method and system of communicating between peer processors in SoC environment Grant 9,367,493 - Devins , et al. June 14, 2	2016-06-14
Flexible performance screen ring oscillator within a scan chain Grant 9,188,643 - Charlebois , et al. November 17, 2	2015-11-17
Performance screen ring oscillator formed from paired scan chains Grant 9,128,151 - Charlebois , et al. September 8, 2	2015-09-08
Performance screen ring oscillator formed from multi-dimensional pairings of scan chains Grant 9,097,765 - Charlebois , et al. August 4, 2	2015-08-04
Chip Performance Monitoring System And Method App 20140195196 - Charlebois; Margaret R. ; et al.	2014-07-10
Ring oscillator Grant 8,754,696 - Charlebois , et al. June 17, 2	2014-06-17
Differential clock signal generator Grant 8,736,340 - Milton May 27, 2	2014-05-27
Flexible Performance Screen Ring Oscillator Within A Scan Chain App 20140132290 - Charlebois; Margaret R. ; et al.	2014-05-15
Ring Oscillator App 20140028365 - Charlebois; Margaret R. ; et al.	2014-01-30
Differential Clock Signal Generator App 20140002167 - Milton; David W.	2014-01-02
Circuit design using design variable function slope sensitivity Grant 8,464,199 - Charlebois , et al. June 11, 2	2013-06-11
Critical Path Delay Prediction App 20130041608 - Charlebois; Margaret R. ; et al.	2013-02-14
Semiconductor layer forming method and structure Grant 8,341,588 - Herzl , et al. December 25, 2	2012-12-25
Method, circuit, and design structure for capturing data across a pseudo-synchronous interface Grant 8,300,752 - Berhanu , et al. October 30, 2	2012-10-30
Method And Device For Identifying And Implementing Flexible Logic Block Logic For Easy Engineering Changes App 20120167022 - HERZL; Robert D. ; et al.	2012-06-28
Method, circuit, and design structure for capturing data across a pseudo-synchronous interface Grant 8,189,723 - Berhanu , et al. May 29, 2	2012-05-29
Method for identifying and implementing flexible logic block logic for easy engineering changes Grant 8,181,148 - Herzl , et al. May 15, 2	2012-05-15
Semiconductor Layer Forming Method And Structure App 20120083913 - Herzl; Robert D. ; et al.	2012-04-05
Optimal bus operation performance in a logic simulation environment Grant 8,140,314 - Devins , et al. March 20, 2	2012-03-20
Structure for identifying and implementing flexible logic block logic for easy engineering changes Grant 8,141,028 - Herzl , et al. March 20, 2	2012-03-20
Minimizing impact of design changes for integrated circuit designs Grant 8,060,845 - Herzl , et al. November 15, 2	2011-11-15
Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method Grant 7,996,807 - Grise , et al. August 9, 2	2011-08-09
Method of switching external models in an automated system-on-chip integrated circuit design verification system Grant 7,917,348 - Devins , et al. March 29, 2	2011-03-29
Circuit and design structure for synchronizing multiple digital signals Grant 7,863,949 - Milton January 4, 2	2011-01-04
Method and system of coherent design verification of inter-cluster interactions Grant 7,849,362 - Devins , et al. December 7, 2	2010-12-07
Circuit And Design Structure For Synchronizing Multiple Digital Signals App 20100194459 - Milton; David W.	2010-08-05
Circuit and design structure for synchronizing multiple digital signals Grant 7,768,325 - Milton August 3, 2	2010-08-03
Method and system for logic verification using mirror interface Grant 7,729,877 - Devins , et al. June 1, 2	2010-06-01
Method and system of design verification Grant 7,711,534 - Devins , et al. May 4, 2	2010-05-04
Method, Circuit, And Design Structure For Capturing Data Across A Pseudo-synchronous Interface App 20100040183 - Berhanu; Malede W. ; et al.	2010-02-18
Method, Circuit, And Design Structure For Capturing Data Across A Pseudo-synchronous Interface App 20100039150 - Berhanu; Malede W. ; et al.	2010-02-18
Method for Minimizing Impact of Design Changes For Integrated Circuit Designs App 20100017773 - Herzl; Robert D. ; et al.	2010-01-21
Circuit and design structure for synchronizing multiple digital signals App 20090267660 - Milton; David W.	2009-10-29
Integrated Test Waveform Generator (twg) And Customer Waveform Generator (cwg), Design Structure And Method App 20090265677 - Grise; Gary D. ; et al.	2009-10-22
Design Structure For Identifying And Implementing Flexible Logic Block Logic For Easy Engineering Changes App 20090183134 - Herzl; Robert D. ; et al.	2009-07-16
Method and Device for Identifying and Implementing Flexible Logic Block Logic for Easy Engineering Changes App 20090183135 - Herzl; Robert D. ; et al.	2009-07-16
Method and apparatus for transmitting data in an integrated circuit Grant 7,536,496 - Harding , et al. May 19, 2	2009-05-19
Method for dynamically changing the frequency of clock signals Grant 7,515,666 - Milton , et al. April 7, 2	2009-04-07
Asic Logic Library Of Flexible Logic Blocks And Method To Enable Engineering Change App 20090045836 - Herzl; Robert D. ; et al.	2009-02-19
Asic Logic Library Of Flexible Logic Blocks And Method To Enable Engineering Change App 20090045839 - HERZL; Robert D. ; et al.	2009-02-19
Optimal bus operation performance in a logic simulation environment App 20080312896 - Devins; Robert J. ; et al.	2008-12-18
Optimal bus operation performance in a logic simulation environment Grant 7,451,070 - Devins , et al. November 11, 2	2008-11-11
Design Structure for Transmitting Data in an Integrated Circuit App 20080276034 - Harding; W. Riyon ; et al.	2008-11-06
Method And System For Logic Verification Using Mirror Interface App 20080222583 - Devins; Robert J. ; et al.	2008-09-11
Method Of Switching External Models In An Automated System-on-chip Integrated Circuit Design Verification System App 20080133206 - Devins; Robert J. ; et al.	2008-06-05
Method of switching external models in an automated system-on-chip integrated circuit design verification system Grant 7,353,156 - Devins , et al. April 1, 2	2008-04-01
Method and system for logic verification using mirror interface Grant 7,353,131 - Devins , et al. April 1, 2	2008-04-01
Method And System For Logic Verification Using Mirror Interface App 20070204246 - Devins; Robert J. ; et al.	2007-08-30
A Method And Apparatus For Transmitting Data In An Integrated Circuit App 20070204094 - Harding; W. Riyon ; et al.	2007-08-30
Method And System Of Coherent Design Verification Of Inter-cluster Interactions App 20070168733 - Devins; Robert J. ; et al.	2007-07-19
Clock control circuit for test that facilitates an at speed structural test Grant 7,240,266 - Farmer , et al. July 3, 2	2007-07-03
METHOD AND SYSTEM OF COMMUNICATING BETWEEN PEER PROCESSORS IN SoC ENVIRONMENT App 20070136559 - Devins; Robert J. ; et al.	2007-06-14
A Method And Apparatus For Transferring Data Between Cores In An Integrated Circuit App 20060262779 - Courchesne; Adam J. ; et al.	2006-11-23
Clock Control Circuit For Test That Facilitates An At Speed Structural Test App 20060248417 - Farmer; Henry R. ; et al.	2006-11-02
System, Method And Program Storage Device For Simulation App 20060229858 - Devins; Robert J. ; et al.	2006-10-12
Clock Control Circuit For Test That Facilitates An At Speed Structural Test App 20060190781 - Farmer; Henry R. ; et al.	2006-08-24
Circuit and method for pipelined insertion Grant 7,065,602 - Horton , et al. June 20, 2	2006-06-20
Method And Apparatus For Initializing Multiple Processors Residing In An Integrated Circuit App 20060047939 - Devins; Robert J. ; et al.	2006-03-02
Method and system for logic verification using mirror interface App 20050144577 - Devins, Robert J. ; et al.	2005-06-30
Method and system for logic verification using mirror interface Grant 6,865,502 - Devins , et al. March 8, 2	2005-03-08
Circuit And Method For Pipelined Insertion App 20050001280 - Horton, Robert S. ; et al.	2005-01-06
Method of switching external models in an automated system-on-chip integrated circuit design verification system App 20030149946 - Devins, Robert J. ; et al.	2003-08-07
System for controlling external models used for verification of system on a chip (SOC) interfaces App 20030145290 - Devins, Robert J. ; et al.	2003-07-31
Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs Grant 6,539,522 - Devins , et al. March 25, 2	2003-03-25
Method of controlling external models in system-on-chip verification Grant 6,487,699 - Devins , et al. November 26, 2	2002-11-26
Method and system for logic verification using mirror interface App 20020147560 - Devins, Robert J. ; et al.	2002-10-10
Method for efficient verification of system-on-chip integrated circuit designs including an embedded processor Grant 6,427,224 - Devins , et al. July 30, 2	2002-07-30
Apparatus for inspecting and hangering shirts Grant 5,046,844 - Milton September 10, 1	1991-09-10

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