U.S. patent application number 11/275091 was filed with the patent office on 2007-06-14 for method and system of communicating between peer processors in soc environment.
Invention is credited to Robert J. Devins, David W. Milton, Pascal A. Nsame.
Application Number | 20070136559 11/275091 |
Document ID | / |
Family ID | 36127019 |
Filed Date | 2007-06-14 |
United States Patent
Application |
20070136559 |
Kind Code |
A1 |
Devins; Robert J. ; et
al. |
June 14, 2007 |
METHOD AND SYSTEM OF COMMUNICATING BETWEEN PEER PROCESSORS IN SoC
ENVIRONMENT
Abstract
A method and system comprises transferring data from a first
processor to at least one pulse generator directly connected to an
interrupt control of at least a second processor. The transferring
of the data bypasses memory. The method further includes reading
the transferred data directly from the at least one pulse generator
by the at least a second processor.
Inventors: |
Devins; Robert J.; (Essex
Junction, VT) ; Milton; David W.; (Underhill, VT)
; Nsame; Pascal A.; (Colchester, VT) |
Correspondence
Address: |
GREENBLUM & BERNSTEIN, P.L.C.
1950 ROLAND CLARK DRIVE
RESTON
VA
20191
US
|
Family ID: |
36127019 |
Appl. No.: |
11/275091 |
Filed: |
December 9, 2005 |
Current U.S.
Class: |
712/2 ; 712/10;
712/24; 712/32 |
Current CPC
Class: |
G06F 15/17 20130101;
G06F 13/24 20130101 |
Class at
Publication: |
712/002 ;
712/010; 712/024; 712/032 |
International
Class: |
G06F 15/00 20060101
G06F015/00; G06F 15/76 20060101 G06F015/76 |
Claims
1. A method comprising: transferring data from a first processor to
at least one pulse generator directly connected to an interrupt
control of at least a second processor, the transferring of the
data bypasses memory; and reading the transferred data directly
from the at least one pulse generator by the at least a second
processor.
2. The method of claim 1, wherein the transferring of the data and
reading of the transferred data is in real-time in a multiprocessor
SoC design.
3. The method of claim 1, wherein the transferring step is provided
in a single clock cycle.
4. The method of claim 1, wherein the reading step is provided in a
single clock cycle.
5. The method of claim 1, further comprising providing write access
directly to the at least one pulse generator.
6. The method of claim 1, wherein the transferring data includes
sending interrupts to the first processor or at least a second
processor through the at least one pulse generator.
7. The method of claim 1, further comprising obtaining
authorization from an arbiter to begin the transferring of
data.
8. The method of claim 1, wherein the reading of the transferred
data is directly from the at least one pulse generator.
9. The method of claim 1, wherein the transferring of the data and
reading of the transferred data is at least (i) processor to
processor data traffic, (ii) processor to enabled interrupt device
data traffic and (iii) processor to non-enable interrupt devices
data.
10. The method of claim 1, further comprising partitioning the at
least one pulse generator such that each partition is dedicated to
at least one of separate functions and separate processors.
11. The method of claim 1, further comprising fabricating an
integrated circuit chip using the method of claim 1.
12. The method of claim 8, further comprising distributing the
integrated circuit chip.
13. A method comprising: obtaining application and ordering
requirements; selecting at least one channel, an arbitration
algorithm and an interrupt type; upon completion of the obtaining
and selecting step, sending a complex message over a bus to a pulse
generator; and reading, by a processor, the complex message
directly from the pulse generator.
14. The method of claim 13, wherein the obtaining the application
requirement is at least one of an application code, data
transmission rates, and amount of time and data type to
transmit.
15. The method of claim 13, wherein the selecting the channel
includes selecting all channels if there is a broadcast message or
one or more channels if there is no broadcast message.
16. The method of claim 15, wherein the selection of the one or
more channels is based on at least a partitioning of the pulse
generator.
17. The method of claim 13, wherein the selecting of the
arbitration algorithm provides priority to the complex message.
18. The method of claim 13, wherein the selecting of the interrupt
type is one of a fast interrupt type, a normal interrupt type or a
non-maskable interrupt type.
19. The method of claim 13, further comprising the pulse generator:
decoding the complex message and the interrupt type; applying the
arbitration algorithm and register ordering requirement;
registering the at least one channel; and upon completion of the
decoding, applying and registering steps, applying the ordering
requirement.
20. The method of claim 19, wherein the reading step is provided
after the steps of claim 19.
21. The method of claim 19, wherein the reading of the transferred
data is in real time.
22. A system, comprising: at least two processors connected to a
bus system; and at least one pulse generator connected to the bus
system and each of the at least two processors, wherein the at
least one pulse generator is a write-only device receiving data
from the at least two processors which has bypassed memory, and the
at least two processors read data directly from the at least one
pulse generator, bypassing the memory.
23. The system of claim 22, wherein the at least one pulse
generator is equal to an amount of the at least two processors.
24. The system of claim 22, wherein the at least one pulse
generator is equal to or less than the number of the at least two
processors and equal to or greater than 1.
25. The system of claim 22, wherein the bus system is an on-chip
bus arbiter or an on-chip crossbar/switch.
26. The system of claim 22, wherein the at least one pulse
generator is connected directly to an interrupt controller of each
of the at least two processors.
27. The system of claim 22, further comprising at least one
interrupt enabled device and one non-interrupt enabled device which
write data directly to the at least one pulse generator.
28. The system of claim 22, wherein the at least one pulse
generator is partitioned for at least one of each of the at least
two processors, functions and a combination thereof.
29. The system of claim 22, wherein the at least one pulse
generator is a single pulse generator connected to the at least two
processors.
30. A system, comprising: peer processors connected to a bus
system; and at least one pulse generator receiving data over the
bus system and connected to an interrupt control of the peer
processors such that data from one of the peer processors is read
directly from the at least one pulse generator by the one of the
peer processors or another of the peer processors.
31. The system of claim 30, wherein the at least one pulse
generator is a write-only device receiving data from the one of the
peer processors.
32. The system of claim 30, wherein the at least one pulse
generator bypasses memory such that the one or the another of the
peer processors read data directly from the at least one pulse
generator, bypassing the memory.
33. The system of claim 30, wherein: the at least one pulse
generator is equal to or less than the number of the peer
processors and equal to or greater than 1; and the at least one
pulse generator is partitioned such that the partition is dedicated
to one or more of the peer processors, functions or a combination
thereof.
34. The system of claim 30, wherein the bus system is an on-chip
bus arbiter or an on-chip crossbar/switch.
35. A computer program product comprising a computer useable medium
including a computer readable program, wherein the computer
readable program when executed on a computer causes the computer
to: provide a signal in one clock cycle to a pulse generator, the
signal having data associated therewith; and a processor reading
the data directly from the pulse generator in one clock cycle and
bypassing memory.
Description
FIELD OF THE INVENTION
[0001] The invention relates to a method and system of
communicating between processors, and more particularly, to a
method and system of communication between multiple processors in a
SoC test and verification environment.
BACKGROUND DESCRIPTION
[0002] Present-day integrated circuit (IC) chips have advanced
significantly in both complexity and sophistication. For example,
in early generation chip designs, a chip might embody relatively
simple electronic logic blocks effected by interconnections between
logic gates; whereas, newer generation chips include designs having
combinations of complex, modularized IC designs often called
"cores", which together constitute an entire SoC. These newer
generation IC designs increase the overall functionality and
performance characteristics of the chip, itself, by, for example,
having the ability to include smaller feature sizes and thus
increasing the amount of circuitry which can be built on a single
chip. But, this comes at a cost: longer design and verification
times which, in turn, translate into added development and
manufacturing costs.
[0003] The verification phase of chip design has moved toward a
software simulation approach to avoid the costs of implementing
designs in hardware to verify the workability of such designs.
However, multiprocessor and multicore designs can lead to very
large simulation models. Even when using modern simulation tools,
simulation load and execution time, as well as build time can
become cost and time prohibitive. This is especially true in
complex design cases with inter-processor clusters since a complete
gate level representation of the design must be constructed and
loaded into the simulation for each processor.
[0004] As the chip design becomes more complex, the verification
tends to require an even more inordinate amount of time and
computing resources, largely due to the modeling and verification
of the interaction of functions associated with the design. This
verification process becomes more complicated for verification of
multi-processor cores, which interact with one another. These
inefficiencies in current verification methodologies exacerbate
time pressures and increase, significantly, the time-to-market, a
key factor for developers and marketers of IC chips in being
competitive in business.
[0005] To effectuate the growing trend towards SoC implementations
of IC using multiprocessor platforms, SoC systems use tightly
coupled software programs and processes running in independent peer
processors. These independent execution units must be able to
communicate with one another in a timely manner. However, in
currently known implementations, communication is through
mailbox/semaphore mechanisms to implement inter-process
communication (IPC) protocols. Such mechanisms tend to be
non-deterministic with respect to message delivery time, and are
often not sufficient for real-time SoC functionality.
[0006] By way of example, and referring to FIG. 1, processors 1
though n communicate with each other through an on-chip chip bus
arbiter, via a UIC (universal interrupt controller). The system of
FIG. 1 additionally includes a single or multiple port memory
controller and network controller in communication with the on-chip
bus arbiter. In implementation, hundreds of cycles may pass before
there is full data transfer between the processors (or other
logic), thus impairing real-time communications. In the example of
FIG. 1, processor 1 transfers data to processor "n" by first
requesting authorization from the arbiter. Once this is granted,
data is written into memory. Processor 2 polls the system and
requests authorization from the arbiter to read the data from the
memory. Once authorization is granted, processor "n" uploads the
data for read operations. This same process would also occur for
non-interrupt network controllers. This, of course, can take many
hundreds of cycles to perform, taking into account the arbiters
role of prioritizing data transfer between many devices.
SUMMARY OF THE INVENTION
[0007] In a first aspect of the invention, a method comprises
transferring data from a first processor to at least one pulse
generator directly connected to an interrupt control of at least a
second processor. The transferring of the data bypasses memory. The
method further includes reading the transferred data directly from
the at least one pulse generator by the at least a second
processor.
[0008] In further embodiments, the method includes transferring of
the data and reading of the transferred data is in real-time in a
multiprocessor SoC design. The transferring step is provided in a
single clock cycle. The reading step is provided in a single clock
cycle. The method further includes, in embodiments, providing write
access directly to the at least one pulse generator. The
transferring data includes sending interrupts to the first
processor or at least a second processor through the at least one
pulse generator. The method further includes, in embodiments,
obtaining authorization from an arbiter to begin the transferring
of data. The reading of the transferred data is directly from the
at least one pulse generator. The transferring of the data and
reading of the transferred data is at least (i) processor to
processor data traffic, (ii) processor to enabled interrupt device
data traffic and (iii) processor to non-enable interrupt devices
data. In further embodiments, the method further includes
partitioning the at least one pulse generator such that each
partition is dedicated to at least one of separate functions and
separate processors. The method can be used to fabricate an
integrated circuit chip and distributing of the integrated circuit
chip.
[0009] In another aspect of the invention, the method includes
obtaining application and ordering requirements and selecting at
least one channel, an arbitration algorithm and an interrupt type.
Upon completion of the obtaining and selecting step, the method
includes sending a complex message over a bus to a pulse generator
and reading, by a processor, the complex message directly from the
pulse generator.
[0010] In further embodiments, the obtaining the application
requirement is at least one of an application code, data
transmission rates, and amount of time and data type to transmit.
The selecting the channel includes selecting all channels if there
is a broadcast message or one or more channels if there is no
broadcast message. The selection of the one or more channels is
based on at least a partitioning of the pulse generator. The
selecting of the arbitration algorithm provides priority to the
complex message. The selecting of the interrupt type is one of a
fast interrupt type, a normal interrupt type or a non-maskable
interrupt type.
[0011] The method further includes the pulse generator: [0012]
decoding the complex message and the interrupt type; [0013]
applying the arbitration algorithm and register ordering
requirement; [0014] registering the at least one channel; and
[0015] upon completion of the decoding, applying and registering
steps, applying the ordering requirement. The reading step is
provided after the above steps performed by the pulse generator.
The reading of the transferred data is in real time.
[0016] In another aspect of the invention, the system includes at
least two processors connected to a bus system and at least one
pulse generator connected to the bus system and each of the at
least two processors. The at least one pulse generator is a
write-only device receiving data from the at least two processors
which has bypassed memory, and the at least two processors read
data directly from the at least one pulse generator, bypassing the
memory.
[0017] In further embodiments of the system the at least one pulse
generator is equal to an amount of the at least two processors. The
at least one pulse generator is equal to or less than the number of
the at least two process and equal to or greater than 1. The bus
system is an on-chip bus arbiter or an on-chip crossbar/switch. The
at least one pulse generator is connected directly to an interrupt
controller of each of the at least two processors. In further
embodiments, at least one interrupt enabled device and one
non-interrupt enabled device write data directly to the at least
one pulse generator. The at least one pulse generator is
partitioned for at least one of each of the at least two
processors, functions and a combination thereof. The at least one
pulse generator is a single pulse generator connected to the at
least two processors.
[0018] In yet another aspect of the invention, the system includes
peer processors connected to a bus system. At least one pulse
generator receives data over the bus system and is connected to an
interrupt control of the peer processors such that data from one of
the peer processors is read directly from the at least one pulse
generator by the one of the peer processors or another of the peer
processors.
[0019] In embodiments, the at least one pulse generator is a
write-only device receiving data from the one of the peer
processors. The at least one pulse generator bypasses memory such
that the one or the another of the peer processors read data
directly from the at least one pulse generator, bypassing the
memory. The at least one pulse generator is equal to or less than
the number of the peer processors and equal to or greater than 1,
and the at least one pulse generator is partitioned such that the
partition is dedicated to one or more of the peer processors,
functions or a combination thereof. The bus system can be an
on-chip bus arbiter or an on-chip crossbar/switch.
[0020] In a further aspect of the invention, a computer program
product comprises a computer useable medium including a computer
readable program. The computer readable program when executed on a
computer causes the computer to provide a signal in one clock cycle
to a pulse generator. The signal has data associated therewith. A
processor reads the data directly from the pulse generator in one
clock cycle and bypasses memory.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] FIG. 1 is a block diagram describing current state of the
art;
[0022] FIG. 2 shows an environment which implements aspects of the
invention;
[0023] FIG. 3 shows a block diagram of an embodiment implementing
the system and method of the invention;
[0024] FIG. 4 shows a block diagram of an embodiment implementing
the system and method of the invention;
[0025] FIG. 5 shows a block diagram of an embodiment implementing
the system and method of the invention;
[0026] FIG. 6 shows a block diagram of an embodiment implementing
the system and method of the invention;
[0027] FIG. 7 is a flow diagram implementing steps of the
invention; and
[0028] FIG. 8 is a flow diagram implementing step of the
invention.
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
[0029] The invention relates to a method and system of
communicating or transferring data between multiple (peer)
processors in a system-on-chip (SoC) design verification
environment. In an embodiment of the invention, the system and
method uses a hardware device that sits as a slave on a bus system
(e.g., on-chip bus, on-chip crossbar/switch, et.) which includes
the peer processors as masters, enabling each processor write
access to this hardware device. The hardware device is a write-only
device which maps bits in a word to output ports, and which
minimizes the amount of time to communicate data to the processors
and any shared resources. Thus, in one implementation, the system
and method provides a structure for interrupt-based IPC signaling
between peer processors in a real-time, multiprocessor SoC design.
For instance, if a bus system is a 32 bit bus, the writeable entity
on hardware device will be any number of 32 bit words. Each bit in
each word has a built-in pulse generator such that if a "1" is
written to this bit, a pulse is driven out on its corresponding
port. If there are two 32 bit words, there would be a total of 64
pulses which can be generated. These pulses can be connected as
interrupts to the processors.
[0030] In implementation, this enables any processor to send any
combination of interrupts to any processor(s), including itself.
There is sufficient interlocking inside the hardware device such
that if two processors attempt to send interrupts at the same time,
the result is deterministic; the bus system will guarantee ordering
of the write operations to the hardware device, and the hardware
device, itself, will complete the first set of pulses(s) commanded
by the first write before accepting the second write operation, so
that it can generate the second set of pulse(s) independent of the
first set. For example, in such case, a processor may receive two
pulses relatively close together and the processor's interrupt
controller will maintain a record. The pulse duration is one clock
cycle of the clock driving hardware device, and the minimum width
between two pulses is also one clock cycle of the hardware device's
clock.
[0031] FIG. 2 shows a block diagram implementing the features of
the invention. In particular, FIG. 2 shows one or more workstations
denoted as reference numeral 100. The one or workstations 100
include a memory, one or more peer processors 200, 300 and other
well-known components. It should be understood by those of skill in
the art that any number of processors are contemplated by the
invention, and hence the designation "n" is provided with reference
to processor 300. In one implementation of the invention, the one
or more workstations 100 include a shared bus (or switch) 400 to
support inter-TOS protocols. (AutoTOS.TM. (or ADF (Application
Definition File) (where software resources are specified)) may be
used to compile user specified parameters (e.g., resources) in
order to generate a specific test to verify.)
[0032] Still referring to FIG. 2, the one or more workstations 100
additionally include one or more pulse generator (PGEN) 500. The
PGEN 500 is arranged to connect to the interrupt inputs of each
processor in the SoC. In different implementations, [0033] a single
PGEN 500 may be associated with all of the processors; [0034] a
single PGEN may be associated with each of the processors; or
[0035] there may be an equal number or less of PGENs than
processors (but greater than one). In the embodiments, data can be
transmitted directly between the peer processors 200, 300, via the
PGEN 500, thus bypassing memory.
[0036] By way of one illustration, the processor 200 can generate a
request to the bus 400 to transfer data to processor 300. Once the
request is granted, the processor 200 will transfer data directly
to the PGEN 500; that is, the data will be written directly into
the PGEN 500. The processor 300 can now read the data directly from
the PGEN 500 (i.e., directly connected to the interrupt control of
the processor(s), bypassing memory). In this manner, data can be
transferred between processors in real-time and the data transfer,
in preferred implementations, will also be deterministic. This
example is applicable between at least (i) processor to processor
data transfer, (ii) processor to enabled interrupt device data
transfer and (iii) processor to non-enable interrupt devices data
transfer.
[0037] FIG. 3 shows an illustrative example of the invention which
may equally be representative of a flow diagram showing steps of
the invention. In this example, processors 1 through n, e.g., 200,
300, are in data communication with the on-chip bus arbiter 400, in
embodiments via a 32 bit, 64 bit, 128 bit, etc. channel. A separate
PGEN is in data communication with the each of the processors 1 . .
. n. For example, PGEN 500a is in data communication with the
processor 200; whereas, the PGEN 500b is in data communication with
processor 300. As should thus be understood, FIG. 3 represents any
number of processors n in data communication with the on-chip bus
arbiter 400, and an equal number of PGENs each of which are
directly connected to the interrupt control of a respective
processor. A memory controller 600 and memory map device 650 are
also in data communication with the on-chip bus arbiter 400.
[0038] In the example of FIG. 3, in one non-limiting illustrative
example, processor 1, 200, is desirous of transferring data to
processor "n", 300. In this example, processor 1, 200, requests
authorization from the on-chip bus arbiter 400 to transfer data to
processor "n", 300. Upon obtaining such authorization, the
processor 1, 200, will write data directly to the PGEN 500b,
eliminating the need for a shared memory or processor "n", 300,
having to poll the system and request its own authorization to read
data from a shared memory. Processor "n", 300, reads the data
directly from the PGEN 500b. This same example can be implemented
for any number of processors, each having their own PGEN.
[0039] FIG. 4 shows an illustrative example of the invention which
may equally be representative of a flow diagram showing steps of
the invention. In this example, processors 1 through "n", e.g.,
200, 300, are in data communication with the on-chip bus arbiter
400, in embodiments, via a 32 bit, 64 bit, 128 bit, etc. channel. A
single PGEN 500 is directly connected to the interrupt control of
the processors 1 . . . "n". For example, PGEN 500 is in data
communication with the processor 200 and processor 300. As should
thus be understood, FIG. 4 represents any number of processors, n,
in data communication with the on-chip bus arbiter 400, and a
single PGEN is directly connected to the interrupt control of each
of the processors. A memory controller 600 and memory map device
650 are also in data communication with the on-chip bus arbiter
400.
[0040] In the example of FIG. 4, in one non-limiting illustrative
example, processor 1, 200, is desirous of transferring data to
processor "n", 300. In this example, processor 1, 200, requests
authorization from the on-chip bus arbiter 400 to transfer data to
processor "n", 300. Upon obtaining such authorization, the
processor 1, 200, will write data directly to the PGEN 500,
eliminating the need for a shared memory and processor "n", 300,
having to poll the system and request its own authorization to read
data from a shared memory. Processor "n", 300, reads the data
directly from the PGEN 500. This same example can be implemented
for any number of processors, each sharing the PGEN 500.
[0041] FIG. 5 shows an illustrative example of the invention which
may equally be representative of a flow diagram showing steps of
the invention. In this example, processors 1 through "n", e.g.,
200, 300, are in data communication with an on-chip crossbar/switch
800, in embodiments, via a 32 bit, 64 bit, 128 bit, etc. channel.
The on-chip crossbar/switch 450 provides a non-blocking
communication, e.g., allows more than one processor to transfer
data at one time. A separate PGEN is directly connected to the
interrupt control of each of the processors 1 . . . "n". For
example, PGEN 500a is in data communication with the processor 200;
whereas, the PGEN 500b is in data communication with processor 300.
As should thus be understood, FIG. 5 represents any number of
processors "n" in data communication with the on-chip
crossbar/switch 800, and an equal number of PGENs each of which are
directly connected to the interrupt control of the respective
processor. A memory controller 600 and memory map device 650 are
also in data communication with the on-chip bus arbiter 400.
[0042] In the example of FIG. 5, in one non-limiting illustrative
example, processor 1, 200, is desirous of transferring data to
processor "n", 300. In this example, processor 1, 200, requests
authorization from the on-chip crossbar/switch 450 to transfer data
to processor "n", 300. Upon obtaining such authorization, the
processor 1, 200, will write data directly to the PGEN 500b,
eliminating the need for a shared memory and processor "n", 300,
having to poll the system and request its own authorization to read
data from a shared memory. Processor "n", 300, reads the data
directly from the PGEN 500b. This same example can be implemented
for any number of processors, each having their own PGEN.
[0043] FIG. 6 shows an illustrative example of the invention which
may equally be representative of a flow diagram showing steps of
the invention. In this example, processors 1 through "n", e.g.,
200, 300, are in data communication with the on-chip
crossbar/switch 800, in embodiments, via a 32 bit, 64 bit, 128 bit,
etc. channel. A single PGEN 500 is in data communication with all
of the processors 1 . . . "n", i.e., directly connected to the
interrupt control of the processor(s). For example, PGEN 500 is in
data communication with the processor 200 and processor 300. As
should thus be understood, FIG. 6 represents any number of
processors "n" in data communication with the on-chip
crossbar/switch 800, and a single PGEN in direct data communication
with each of the respective processors. A memory controller 600 and
memory map device 650 are also in data communication with the
on-chip bus arbiter 400.
[0044] In the example of FIG. 6, in one non-limiting illustrative
example, processor 1, 200, is desirous of transferring data to
processor "n", 300. In this example, processor 1, 200, requests
authorization from the on-chip crossbar/switch 450 to transfer data
to processor "n", 300. Upon obtaining such authorization, the
processor 1, 200, will write data directly to the PGEN 500,
eliminating the need for a shared memory and processor "n", 300,
having to poll the system and request its own authorization to read
data from a shared memory. Processor "n", 300, reads the data
directly from the PGEN 500. This same example can be implemented
for any number of processors, each sharing the PGEN 500.
[0045] In the examples of FIGS. 3-6, the number of PGENs may be
optimally matched to the system requirements. For example, the PGEN
500 may be a 32 bit, 64 bit or 128 bit channel; although, other bit
channels are also contemplated by the invention. By way of example,
if there is a packet with 64 bits, it may be desirous to have a 64
bit data channel; although a 32 bit data channel (or less) is also
possible, with the understanding that two or more cycles will be
required for data transfer.
[0046] Also, other considerations to be taken into account are the
number of processors associated with the system. So, for example,
if there are one hundred processors, it may be advantageous to have
more than one PGEN with one hundred connections. Instead, as an
example, there may be four PGENs connected to the system, each with
25 connections, in addition to a 32 bit (64 bit, etc. channel to
the bus.
[0047] It is also contemplated by the invention to have the PGEN
partitioned such that a portion (partitioned section) of each PGEN
is associated with a single or multiple processors or function(s).
By way of example, a 32 bit PGEN can be partitioned into four
partitions of 8 bits each, with each partition being responsible
for a single processor and/or function. In this way, data can be
written into a single partition of a single PGEN, which can be
dedicated to a single processor (or multiple processors). The
partitions can be repartitioned across any processor or within one
processor such that, in one example, a single partition (8 bit
channel) can be dedicated to all processors, with the remaining
channels dedicated to variations of different processors and/or
functions. Thus, depending on the system requirements, it is
possible to reduce the number of PGENs to an optimal level. In the
embodiments, it is contemplated that the number of PGEN is less
than or equal to a number of processors and equal to or greater
than 1.
[0048] In any of the above examples, using the PGEN of the present
invention, structure is provided for interrupt-based IPC signaling
between peer processors in a real-time, multiprocessor SoC design.
Also, the use of the system and method of the present invention
provides scalability, thus eliminating any concerns about providing
additional processors and/or processes within the system.
Accordingly, regardless of the amount of processors and/or
processes, response time for the data transfer can be
increased.
[0049] FIG. 7 is a flow diagram implementing steps of the
invention. FIG. 7 (and any other flow diagrams) may equally
represent a high-level block diagram of the system, implementing
the steps thereof. The steps of FIG. 7 (and FIG. 8) may be
implemented on computer program code in combination with the
appropriate hardware. This computer program code may be stored on
storage media such as a diskette, hard disk, CD-ROM, DVD-ROM or
tape, as well as a memory storage device or collection of memory
storage devices such as read-only memory (ROM) or random access
memory (RAM).
[0050] Referring to FIG. 7, at step 700, the sending processor
obtains application requirements. These application requirements
may be, for example, application code, data transmission rates,
amount of time and data type to transmit. At step 705, the sending
processor selects at least one channel to transfer data. For
example, the sending processor may select all channels if there is
a broadcast message; however, if there is not a broadcast message,
the sending processor may select one or more channels. The
selection of one or more channels may depend on such variables as
the partitioning of the PGEN, the number of PGEN on the system,
etc., all readily implemented by those of skill in the art. At step
710, the sending processor obtains ordering requirements. By way of
example, if processor "A" would like to write data in a certain
order (e.g., 1, 2, 3, 4 . . . ), the PGEN must comply with this
ordering during the data transfer cycle.
[0051] At step 715, the sending processor will select the
arbitration algorithm. This arbitration algorithm may provide
priority to certain complex messages, e.g., priority to data
transfer over the on-chip bus or on-chip crossbar/switch. This may
be especially relevant when using the on-chip crossbar/switch since
multiple communications can occur at the same time. At step 720, an
interrupt type is selected. The interrupt type may be, for example,
a fast interrupt type, a normal interrupt type or a non-maskable
interrupt type, all known to those of skill in the art. At step
725, the complex message is sent over the bus (or switch) to the
PGEN. At step 730, the receipt of the complex message is
acknowledged. The step(s) described herein ensures that data is
read in a priority order and that data from multiple processors are
read in a deterministic manner.
[0052] FIG. 8 is a flow diagram implementing steps of the
invention. At step 800, the PGEN decodes the message. At step 805,
the PGEN receives the complex message. At step 810, the PGEN
decodes the interrupt type, e.g., fast interrupt type, normal
interrupt type or a non-maskable interrupt type. At step 815, the
PGEN applies the arbitration algorithm such that it can determine
the priority given to the complex message. At step 820, the PGEN
applies the register ordering requirement. At step 825, the PGEN
registers the channel and, at step 830, the PGEN applies the
ordering requirements. In this way, the PGEN can provide the
information directly to the receiving processor in a reliable
manner. Also, the step(s) described herein ensures that data is
read in a priority order and that data from multiple processors are
read in a deterministic manner.
[0053] Accordingly, the system and method of the invention provides
a flexible hardware pulse generator, arranged to connect to the
interrupt inputs of each processor in the SoC. The system of the
invention provides the ability to issue complex, real-time messages
between the processors in a multiple processor SoC design. The
system and method of the invention further provides global access
from each processor to any of the interrupt pulse controls, and
allows for broadcast, sub-broadcast and individual shoulder taps,
with automatic interlocking/deterministic mechanism. That is, the
system and method of the invention ensures that data is read in a
priority order and that data from multiple processors are read in a
deterministic manner.
[0054] The method as described herein is used in the fabrication of
integrated circuit chips. The resulting integrated circuit chips
can be distributed by the fabricator in raw wafer form (that is, as
a single wafer that has multiple unpackaged chips), as a bare die,
or in a packaged form. In the latter case the chip is mounted in a
single chip package (such as a plastic carrier, with leads that are
affixed to a motherboard or other higher level carrier) or in a
multichip package (such as a ceramic carrier that has either or
both surface interconnections or buried interconnections). In any
case the chip is then integrated with other chips, discrete circuit
elements, and/or other signal processing devices as part of either
(a) an intermediate product, such as a motherboard, or (b) an end
product. The end product can be any product that includes
integrated circuit chips, ranging from toys and other low-end
applications to advanced computer products having a display, a
keyboard or other input device, and a central processor.
[0055] The invention can take the form of an entirely hardware
embodiment, an entirely software embodiment or an embodiment
containing both hardware and software elements. In a preferred
embodiment, the invention is implemented in software, which
includes but is not limited to firmware, resident software,
microcode, etc. Furthermore, the invention can take the form of a
computer program product accessible from a computer-usable or
computer-readable medium providing program code for use by or in
connection with a computer or any instruction execution system. For
the purposes of this description, a computer-usable or computer
readable medium can be any apparatus that can contain, store,
communicate, propagate, or transport the program for use by or in
connection with the instruction execution system, apparatus, or
device.
[0056] The medium can be an electronic, magnetic, optical,
electromagnetic, infrared, or semiconductor system (or apparatus or
device) or a propagation medium. Examples of a computer-readable
medium include a semiconductor or solid state memory, magnetic
tape, a removable computer diskette, a random access memory (RAM),
a read-only memory (ROM), a rigid magnetic disk and an optical
disk. Current examples of optical disks include compact disk--read
only memory (CD-ROM), compact disk--read/write (CD-R/W) and
DVD.
[0057] A data processing system suitable for storing and/or
executing program code will include at least one processor coupled
directly or indirectly to memory elements through a system bus. The
memory elements can include local memory employed during actual
execution of the program code, bulk storage, and cache memories
which provide temporary storage of at least some program code in
order to reduce the number of times code must be retrieved from
bulk storage during execution.
[0058] Input/output or I/O devices (including but not limited to
keyboards, displays, pointing devices, etc.) can be coupled to the
system either directly or through intervening I/O controllers.
Network adapters may also be coupled to the system to enable the
data processing system to become coupled to other data processing
systems or remote printers or storage devices through intervening
private or public networks. Modems, cable modem and Ethernet cards
are just a few of the currently available types of network
adapters.
[0059] While the invention has been described in terms of exemplary
embodiments, those skilled in the art will recognize that the
invention can be practiced with modifications and in the spirit and
scope of the appended claims.
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