loadpatents
name:-0.046918153762817
name:-0.044041872024536
name:-0.00063800811767578
Devins; Robert J. Patent Filings

Devins; Robert J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Devins; Robert J..The latest application filed is for "optimal bus operation performance in a logic simulation environment".

Company Profile
0.23.17
  • Devins; Robert J. - Essex Junction VT US
  • Devins, Robert J. - Essex Juntion VT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method and system of communicating between peer processors in SoC environment
Grant 9,367,493 - Devins , et al. June 14, 2
2016-06-14
System and method for developing embedded software in-situ
Grant 8,234,624 - Devins , et al. July 31, 2
2012-07-31
Optimal bus operation performance in a logic simulation environment
Grant 8,140,314 - Devins , et al. March 20, 2
2012-03-20
Method of switching external models in an automated system-on-chip integrated circuit design verification system
Grant 7,917,348 - Devins , et al. March 29, 2
2011-03-29
Method and system of coherent design verification of inter-cluster interactions
Grant 7,849,362 - Devins , et al. December 7, 2
2010-12-07
Method and system for logic verification using mirror interface
Grant 7,729,877 - Devins , et al. June 1, 2
2010-06-01
Method and system of design verification
Grant 7,711,534 - Devins , et al. May 4, 2
2010-05-04
Optimal bus operation performance in a logic simulation environment
App 20080312896 - Devins; Robert J. ;   et al.
2008-12-18
Optimal bus operation performance in a logic simulation environment
Grant 7,451,070 - Devins , et al. November 11, 2
2008-11-11
Method And System For Logic Verification Using Mirror Interface
App 20080222583 - Devins; Robert J. ;   et al.
2008-09-11
System And Method For Developing Embedded Software In-situ
App 20080184193 - Devins; Robert J. ;   et al.
2008-07-31
Method Of Switching External Models In An Automated System-on-chip Integrated Circuit Design Verification System
App 20080133206 - Devins; Robert J. ;   et al.
2008-06-05
Method of switching external models in an automated system-on-chip integrated circuit design verification system
Grant 7,353,156 - Devins , et al. April 1, 2
2008-04-01
Method and system for logic verification using mirror interface
Grant 7,353,131 - Devins , et al. April 1, 2
2008-04-01
Method And System For Logic Verification Using Mirror Interface
App 20070204246 - Devins; Robert J. ;   et al.
2007-08-30
Method And System Of Coherent Design Verification Of Inter-cluster Interactions
App 20070168733 - Devins; Robert J. ;   et al.
2007-07-19
METHOD AND SYSTEM OF COMMUNICATING BETWEEN PEER PROCESSORS IN SoC ENVIRONMENT
App 20070136559 - Devins; Robert J. ;   et al.
2007-06-14
Method and system for graphics rendering using hardware-event-triggered execution of captured graphics hardware instructions
Grant 7,176,927 - Devins , et al. February 13, 2
2007-02-13
System, Method And Program Storage Device For Simulation
App 20060229858 - Devins; Robert J. ;   et al.
2006-10-12
Method And System Of Design Verification
App 20060064296 - Devins; Robert J. ;   et al.
2006-03-23
Method And Apparatus For Initializing Multiple Processors Residing In An Integrated Circuit
App 20060047939 - Devins; Robert J. ;   et al.
2006-03-02
Method and system for graphics rendering using captured graphics hardware instructions
Grant 6,952,215 - Devins , et al. October 4, 2
2005-10-04
Method and system for logic verification using mirror interface
App 20050144577 - Devins, Robert J. ;   et al.
2005-06-30
Method for re-using system-on-chip verification software in an operating system
Grant 6,868,545 - Devins , et al. March 15, 2
2005-03-15
Method and system for logic verification using mirror interface
Grant 6,865,502 - Devins , et al. March 8, 2
2005-03-08
Method and system for graphics rendering using hardware-event-triggered execution of captured graphics hardware instructions
Grant 6,762,761 - Devins , et al. July 13, 2
2004-07-13
Method and system for graphics rendering using hardware-event-triggered execution of captured graphics hardware instructions
App 20040054834 - Devins, Robert J. ;   et al.
2004-03-18
Automated system-on-chip integrated circuit design verification system
Grant 6,658,633 - Devins , et al. December 2, 2
2003-12-02
Processor-independent system-on-chip verification for embedded processor systems
Grant 6,615,167 - Devins , et al. September 2, 2
2003-09-02
Method of switching external models in an automated system-on-chip integrated circuit design verification system
App 20030149946 - Devins, Robert J. ;   et al.
2003-08-07
System for controlling external models used for verification of system on a chip (SOC) interfaces
App 20030145290 - Devins, Robert J. ;   et al.
2003-07-31
Simulator-independent system-on-chip verification methodology
Grant 6,571,373 - Devins , et al. May 27, 2
2003-05-27
Automated system-on-chip integrated circuit design verification system
App 20030093764 - Devins, Robert J. ;   et al.
2003-05-15
Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs
Grant 6,539,522 - Devins , et al. March 25, 2
2003-03-25
Method And System For Graphics Rendering Using Hardware-event-triggered Execution Of Captured Graphics Hardware Instructions
App 20030001849 - DEVINS, ROBERT J. ;   et al.
2003-01-02
Method of controlling external models in system-on-chip verification
Grant 6,487,699 - Devins , et al. November 26, 2
2002-11-26
Method and system for logic verification using mirror interface
App 20020147560 - Devins, Robert J. ;   et al.
2002-10-10
Method for efficient verification of system-on-chip integrated circuit designs including an embedded processor
Grant 6,427,224 - Devins , et al. July 30, 2
2002-07-30
DMA emulation for non-DMA capable interface cards
Grant 5,784,595 - Devins , et al. July 21, 1
1998-07-21

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