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Speculative checkin of ERAT cache entries
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Maintaining consistency between address translations in a data processing system
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Speculative Checkin Of Erat Cache Entries
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Promotion Of Erat Cache Entries
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Critical path delay prediction
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Chip performance monitoring system and method
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Techniques For Maintaining Consistency Between Address Translations In A Data Processing System
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Chip Performance Monitoring System And Method
App 20160231379 - Charlebois; Margaret R. ; et al. | 2016-08-11 |
Chip performance monitoring system and method
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Flexible performance screen ring oscillator within a scan chain
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Performance screen ring oscillator formed from paired scan chains
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Performance screen ring oscillator formed from multi-dimensional pairings of scan chains
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Chip Performance Monitoring System And Method
App 20140195196 - Charlebois; Margaret R. ; et al. | 2014-07-10 |
Ring oscillator
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Flexible Performance Screen Ring Oscillator Within A Scan Chain
App 20140132290 - Charlebois; Margaret R. ; et al. | 2014-05-15 |
Shadow registers for least recently used data in cache
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Ring Oscillator
App 20140028365 - Charlebois; Margaret R. ; et al. | 2014-01-30 |
Circuit design using design variable function slope sensitivity
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Shadow Registers For Least Recently Used Data In Cache
App 20130042068 - Chadwick, JR.; Thomas B. ; et al. | 2013-02-14 |
Critical Path Delay Prediction
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Semiconductor layer forming method and structure
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Method And Device For Identifying And Implementing Flexible Logic Block Logic For Easy Engineering Changes
App 20120167022 - HERZL; Robert D. ; et al. | 2012-06-28 |
Method for identifying and implementing flexible logic block logic for easy engineering changes
Grant 8,181,148 - Herzl , et al. May 15, 2 | 2012-05-15 |
Semiconductor Layer Forming Method And Structure
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Structure for identifying and implementing flexible logic block logic for easy engineering changes
Grant 8,141,028 - Herzl , et al. March 20, 2 | 2012-03-20 |
Minimizing impact of design changes for integrated circuit designs
Grant 8,060,845 - Herzl , et al. November 15, 2 | 2011-11-15 |
Method of switching external models in an automated system-on-chip integrated circuit design verification system
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Method for Minimizing Impact of Design Changes For Integrated Circuit Designs
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Method and Device for Identifying and Implementing Flexible Logic Block Logic for Easy Engineering Changes
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Design Structure For Identifying And Implementing Flexible Logic Block Logic For Easy Engineering Changes
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Asic Logic Library Of Flexible Logic Blocks And Method To Enable Engineering Change
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Asic Logic Library Of Flexible Logic Blocks And Method To Enable Engineering Change
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Method Of Switching External Models In An Automated System-on-chip Integrated Circuit Design Verification System
App 20080133206 - Devins; Robert J. ; et al. | 2008-06-05 |
Method of switching external models in an automated system-on-chip integrated circuit design verification system
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Method for re-using system-on-chip verification software in an operating system
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Processor-independent system-on-chip verification for embedded processor systems
Grant 6,615,167 - Devins , et al. September 2, 2 | 2003-09-02 |
Method of switching external models in an automated system-on-chip integrated circuit design verification system
App 20030149946 - Devins, Robert J. ; et al. | 2003-08-07 |
Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs
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Method of controlling external models in system-on-chip verification
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