U.S. patent application number 12/313368 was filed with the patent office on 2009-03-19 for complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress.
Invention is credited to Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Martin D. Giles, Been Y. Jin, Jack Kavalieros, Philippe Matagne, Matthew V. Metz, Lucian Shifren, Mark Stettler, Everett X. Wang.
Application Number | 20090075445 12/313368 |
Document ID | / |
Family ID | 36636953 |
Filed Date | 2009-03-19 |
United States Patent
Application |
20090075445 |
Kind Code |
A1 |
Kavalieros; Jack ; et
al. |
March 19, 2009 |
Complementary metal oxide semiconductor integrated circuit using
uniaxial compressive stress and biaxial compressive stress
Abstract
A transistor may be formed of different layers of silicon
germanium, a lowest layer having a graded germanium concentration
and upper layers having constant germanium concentrations such that
the lowest layer is of the form Si.sub.1-xGe.sub.x. The highest
layer may be of the form Si.sub.1-yGe.sub.y on the PMOS side. A
source and drain may be formed of epitaxial silicon germanium of
the form Si.sub.1-zGe.sub.z on the PMOS side. In some embodiments,
x is greater than y and z is greater than x in the PMOS device.
Thus, a PMOS device may be formed with both uniaxial compressive
stress in the channel direction and in-plane biaxial compressive
stress. This combination of stress may result in higher mobility
and increased device performance in some cases.
Inventors: |
Kavalieros; Jack; (Portland,
OR) ; Brask; Justin K.; (Portland, OR) ;
Doczy; Mark L.; (Beaverton, OR) ; Metz; Matthew
V.; (Hillsboro, OR) ; Datta; Suman;
(Beaverton, OR) ; Doyle; Brian S.; (Portland,
OR) ; Chau; Robert S.; (Beaverton, OR) ; Wang;
Everett X.; (San Jose, CA) ; Matagne; Philippe;
(Beaverton, OR) ; Shifren; Lucian; (Hillsboro,
OR) ; Jin; Been Y.; (Lake Oswego, OR) ;
Stettler; Mark; (Hillsboro, OR) ; Giles; Martin
D.; (Portland, OR) |
Correspondence
Address: |
TROP, PRUNER & HU, P.C.
1616 S. VOSS ROAD, SUITE 750
HOUSTON
TX
77057-2631
US
|
Family ID: |
36636953 |
Appl. No.: |
12/313368 |
Filed: |
November 19, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11078267 |
Mar 11, 2005 |
7470972 |
|
|
12313368 |
|
|
|
|
Current U.S.
Class: |
438/300 ;
257/E21.431 |
Current CPC
Class: |
H01L 21/823807 20130101;
H01L 21/823814 20130101; H01L 29/7848 20130101; H01L 29/1054
20130101; H01L 29/165 20130101; H01L 29/41783 20130101; Y10S
438/933 20130101; H01L 29/7834 20130101; H01L 29/66636
20130101 |
Class at
Publication: |
438/300 ;
257/E21.431 |
International
Class: |
H01L 21/336 20060101
H01L021/336 |
Claims
1. A method comprising: forming a PMOS transistor having both
uniaxial compressive stress in the channel direction and in-plane
biaxial compressive stress, including a first layer under said gate
electrode of Si.sub.1-yGe.sub.y and a second layer under said first
layer, said second layer having Si.sub.1-xGe.sub.x where x is less
than y.
2. The method of claim 1 including forming a substrate covered by a
first layer having an increasing concentration of germanium
extending upwardly through the layer.
3. The method of claim 2 including covering said first layer with a
second layer of constant germanium concentration.
4. The method of claim 3 including forming a source and drain of
epitaxial silicon germanium of the form Si.sub.1-zGe.sub.z.
5. The method of claim 4 including making z greater than x and x
less than y.
6. The method of claim 1 including forming uniaxial compressive
stress in the channel direction by forming a silicon germanium
epitaxial source drain.
7. The method of claim 1 including forming in-plane biaxial
compressive stress by depositing a silicon germanium layer as a
channel having the form Si.sub.1-yGe.sub.y and forming an
underlying buffer layer of the form Si.sub.1-xGe.sub.x where x is
less than y.
8. The method of claim 1 including forming NMOS and PMOS
transistors at the same time.
9. The method of claim 8 including forming a graded germanium
concentration silicon germanium buffer layer, covering said buffer
layer with a layer of silicon germanium of constant germanium
concentration, and covering said constant germanium concentration
layer with a tensile strained silicon layer on both the NMOS and
PMOS sides.
10. The method of claim 9 including selectively removing the
tensile strained biaxial silicon layer on the PMOS side.
11. The method of claim 10 including selectively removing the
tensile strained silicon layer using about 5 to 8 percent
NH.sub.4OH with a pH between about 10.2 and 10.4 at a temperature
between about 20.degree. C. and 27.degree. C.
12. The method of claim 10 including removing said tensile strained
silicon layer on the PMOS side using an etchant that solubilizes
the tensile strained silicon layer but does not solubilize
underlying layers having higher germanium concentrations.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This is a divisional application of U.S. patent application
Ser. No. 11/078,267, filed Mar. 11, 2005.
BACKGROUND
[0002] This invention relates generally to the fabrication of
integrated circuits.
[0003] To increase performance of NMOS and PMOS deep sub-micron
transistors in CMOS technology, current state-of-the-art technology
uses compressive stress in the channel of the PMOS transistors, and
tensile stress in the case of NMOS transistors. This is usually
achieved by substrate induced strain which is a very expensive
technology option and is also difficult to implement using a single
substrate approach.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 is an enlarged, cross-sectional view of an NMOS
transistor at an early stage of manufacture;
[0005] FIG. 2 is an enlarged, cross-sectional view of a PMOS
transistor at an early stage of manufacture;
[0006] FIG. 3 is an enlarged, cross-sectional view at a stage
subsequent to the stage shown in FIG. 1 in accordance with one
embodiment of the present invention;
[0007] FIG. 4 is an enlarged, cross-sectional view at a stage
subsequent to the stage shown in FIG. 2 in accordance with one
embodiment of the present invention;
[0008] FIG. 5 is an enlarged, cross-sectional view at a stage
subsequent to the stage shown in FIG. 3 in accordance with one
embodiment of the present invention;
[0009] FIG. 6 is an enlarged, cross-sectional view at a stage
subsequent to the stage shown in FIG. 4 in accordance with one
embodiment of the present invention;
[0010] FIG. 7 is an enlarged, cross-sectional view at a stage
subsequent to the stage shown in FIG. 6 in accordance with one
embodiment of the present invention;
[0011] FIG. 8 is an enlarged, cross-sectional view at a stage
subsequent to the stage shown in FIG. 7 in accordance with one
embodiment of the present invention;
[0012] FIG. 9 is an enlarged, cross-sectional view at a stage
subsequent to the stage shown in FIG. 8 in accordance with one
embodiment of the present invention;
[0013] FIG. 10 is an enlarged, cross-sectional view at a stage
subsequent to the stage shown in FIG. 9 in accordance with one
embodiment of the present invention; and
[0014] FIG. 11 is an enlarged, cross-sectional view at a stage
subsequent to the stage shown in FIG. 5 in accordance with one
embodiment of the present invention.
DETAILED DESCRIPTION
[0015] Referring to FIG. 1, a silicon substrate 12 may be covered
by a graded buffer layer 14. The buffer layer 14 may be formed of
silicon germanium of the formula Si.sub.1-xGe.sub.x where x is from
0.05 to 0.3. In one embodiment, the buffer layer 14 may be
epitaxially grown, while gradually increasing the concentration of
germanium. Thus, the germanium concentration is highest at the top
of the layer 14, lowest at the bottom, and linearly increases from
bottom to top in one embodiment.
[0016] Over the layer 14 may be deposited a constant concentration
silicon germanium buffer layer 16. In one embodiment of the present
invention, this layer 16 may have a thickness of from 2000 to
10,000 Angstroms. The layer 16 may have a constant germanium
concentration substantially equal to that of the highest germanium
level of the layer 14, in one embodiment.
[0017] A tensile strained silicon layer 18 is formed thereover.
Shallow trench isolations 20 may be provided as well. In one
embodiment of the present invention, the structure 10b, shown in
FIG. 1, will be utilized to form both NMOS and PMOS transistors of
a complementary metal oxide semiconductor integrated circuit
technology.
[0018] The gradient of germanium in the graded buffer layer 14 can
vary depending on the thickness and final germanium concentration.
In some embodiments, the concentration of germanium in the graded
layer 14 extends from about zero percent at the bottom to about 40
percent at the top. Other percentages may be utilized in different
situations. The layer 14 functions to achieve a relaxed silicon
germanium layer and to reduce dislocation formation due to mismatch
in the lattice constraints between silicon and the silicon
germanium. The constant germanium concentration silicon germanium
buffer layer 16 further stabilizes the structure.
[0019] The tensile strained silicon layer 18 may be grown. The
strained nature of the layer 18 is limited by the critical layer
thickness associated with the concentration of germanium in the
underlying buffer layer 16.
[0020] At the same time, the PMOS structure 10a may be fabricated,
as shown in FIG. 2. The PMOS structure 10a may initially have the
same components as the NMOS structure 10b.
[0021] Thereafter, as shown in FIG. 3, a hard mask 21 may be
deposited over the tensile strained silicon layer 18 on the NMOS
side 10b and PMOS side 10a.
[0022] Then, a hard mask etch and resist removal may be utilized to
remove the tensile strained silicon 18 and the hard mask 21 on the
PMOS transistor structure 10a as shown in FIG. 4. The selective
etch may use 5 to 8 percent NH.sub.4OH with a pH between about 10.2
and 10.4 at a temperature between 20.degree. C. and 27.degree. C.
in one embodiment. The resulting structure has the tensile strained
silicon removed on the PMOS side 10a. The NMOS side 10b is still
covered by the hard mask 21 (FIG. 3).
[0023] The selective wet etch of the strained silicon layer 18 is
such that nucleophillic binding energy of silicon is surpassed and
an etch of the silicon layer 18 is effected. However, the
nucleophillic binding energy may be only about 0.5 kJ/mol too
little to solubilize the germanium to the corresponding aqueous
species, so the layer 16 is preserved.
[0024] Then, a compressively strained silicon germanium layer 28 is
deposited as shown in FIG. 6 on the PMOS side 10a. The silicon
germanium may be of the formula Si.sub.1-yGe.sub.y, where y is
greater than x. The higher concentration y means the layer 28 has a
larger lattice than the underlying layers, resulting in compressive
strain applied upwardly by the layers 14 and 16 to biaxially
compress the layer 28.
[0025] The layer 28 may be selectively grown on the PMOS side 10a
only and not on the NMOS side 10b as indicated in FIG. 5 because
only the NMOS side 10b was covered by the hard mask 21 at the time
the layer 28 was deposited.
[0026] The fabrication of the PMOS transistor proceeds as shown in
FIGS. 7-11. On both the NMOS and PMOS sides a silicon dioxide gate
oxide 30 may be deposited in one embodiment. The gate oxide 30 may
be covered by a gate material 34, such as polysilicon, in turn
covered by a hard mask 34 for patterning. Then the gate material 34
and gate oxide 30 are patterned to generate the FIG. 7 structure on
the PMOS side 10a (and the same structure is created on the NMOS
side 10b with the layer 18 replacing the layer 28).
[0027] Then, separate tip implants I (FIG. 7) and standard
lithographic patterning form the lightly doped source drain regions
39 on both NMOS and PMOS sides (FIG. 8). A nitride spacer material
may be deposited and anisotropically etched on both NMOS and PMOS
sides to form the spacers 36.
[0028] On the PMOS side 10a only, a trench 24 is formed through the
layer 28 and into the layer 16, as shown in FIG. 9. The trench 24
may be formed by reactive ion etching using SF.sub.6 chemistry. The
etching is constrained by the isolation 20 on one side and may
isotropically undercut the gate structure on the other side. As a
result, an isotropic etch profile may be achieved on the inward
edges of the trench 24 as shown in FIG. 9. During this step the
NMOS side 10a may be covered by an oxide mask (not shown).
[0029] Then, an epitaxial silicon germanium source drain 40 may be
grown which fills the trench 24 and extends thereabove as indicated
at FIG. 10. The trench 24 may be filled using silicon germanium
having 10-40 atomic percent germanium. Source drain doping may be
done by insitu doping using a diborane source. The epitaxial source
drain 40 only grows in the trench 24 because all other material is
masked or covered. The source drain 40 is raised and continues to
grow until the facets meet.
[0030] The fabrication of the NMOS transistor 10b, shown in FIG.
11, proceeds correspondingly. However, a conventionally
non-epitaxially grown deeper source drain (not shown) may be
created.
[0031] The PMOS device 10a may have both uniaxial compressive
stress in the channel direction and in-plane biaxial compressive
stress. The Si.sub.1-yGe.sub.y layer 28 acts as a channel and is
grown on a relaxed Si.sub.1-xGe.sub.x buffer layer 16 with x less
than y to produce in-plane biaxial compressive stress. In addition,
a silicon germanium epitaxial source drain 40 produces uniaxial
compressive stress in the channel <110> crystallographic
direction. The source drain 40 has a higher germanium concentration
than the layer 14 so the source drain 40 pushes inwardly from the
sides compressing layer 28. With this combination of stress, higher
mobility and, thus, higher device performance may be achieved
compared to using either of the stresses alone in some
embodiments.
[0032] Once the optimal stress condition is known, the device may
be engineered to produce such stress through an epitaxial silicon
germanium source drain 40 and a silicon germanium layered
structure. Then, a graded silicon germanium buffer layer 14 may be
grown on the silicon substrate 12 followed by a relaxed
Si.sub.1-xGe.sub.x layer 16 as shown in FIG. 10. Then, a thin
Si.sub.1-yGe.sub.y layer 28 is grown to form a biaxial compressive
strained channel.
[0033] The uniaxial stress is produced by the epitaxial source
drain process using epitaxial Si.sub.1-zGe.sub.z grown in recessed
source drain regions 40. Selecting the germanium fractions so that
x is less than y and z is less than x achieves the desired
compressive states.
[0034] The mobility gain may remain high even as vertical field
(gate field) is applied in some embodiments. In addition, more head
room may be provided to increase performance before the device hits
the physical stress limit in some embodiments. With the provision
of combined stress, holes may stay in their lowest transport
effective mass in the <110> channel direction where
scattering suppression is also the strongest. Silicon band
structure has a minimum at the gamma point. It also has twelve
wings in (0, +-1, +-1), (+-1, 0, +-1) and (+-1, +-1, 0) directions.
Ideally, almost all of the holes are placed in two wings in the (1,
-1, 0) and (-1, 1, 0) direction to achieve the lowest possible
transport effective mass in the channel direction. This can be
achieved by applying both uniaxial compressive and biaxial
compressive stress.
[0035] The biaxial compressive stress lowers the energy level of
the four in-plane wings and removes holes from the eight off plane
wings, placing them in the four in-plane wings. The four in-plane
wings not only have smaller effective mass, but also have smaller
density states, which leads to a reduction of scattering. The
greatest mobility enhancement happens when the uniaxial compressive
stress along the channel direction is added to the biaxial
compressed device.
[0036] According to simulation, when hole-optical phonon and
surface roughness scattering occurs, most of the holes stay only in
the wings along (1, -1, 0) and (-1, 1, 0), which has the smallest
transport effective mass in the channel direction. Since only two
wings are occupied, the density of states is also greatly reduced,
enhancing scattering suppression. As a result, the combination
stressed device may have higher mobility.
[0037] While the present invention has been described with respect
to a limited number of embodiments, those skilled in the art will
appreciate numerous modifications and variations therefrom. It is
intended that the appended claims cover all such modifications and
variations as fall within the true spirit and scope of this present
invention.
* * * * *