U.S. patent application number 11/083926 was filed with the patent office on 2005-07-28 for method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus.
This patent application is currently assigned to FUJITSU LIMITED. Invention is credited to Ishizuki, Yoshikatsu, Mizukoshi, Masataka, Nakagawa, Kanae, Okamoto, Keishiro, Sakai, Taiji, Teshirogi, Kazuo.
Application Number | 20050161814 11/083926 |
Document ID | / |
Family ID | 34797095 |
Filed Date | 2005-07-28 |
United States Patent
Application |
20050161814 |
Kind Code |
A1 |
Mizukoshi, Masataka ; et
al. |
July 28, 2005 |
Method for forming bumps, semiconductor device and method for
manufacturing same, substrate processing apparatus, and
semiconductor manufacturing apparatus
Abstract
A semiconductor substrate (1) is secured by suction to a rear
face (1b) of a supporting face (11a) of a substrate supporting
table (11). In this event, the thickness of the semiconductor
substrate (1) is made fixed by planarization on the rear face (1b),
and the rear face (1b) is forcibly brought into a state free from
undulation by the suction to the supporting face (11a), so that the
rear face (1b) becomes a reference face for planarization of a
front face (1a). In this state, a tool (10) is used to cut surface
layers of Au projections (2) and a resist mask (12) on the front
face (1a), thereby planarizing the Au projections (2) and the
resist mask (12) so that their surfaces become continuously flat.
This can planarize the surfaces of fine bumps formed on the
substrate at a low cost and a high speed in place of CMP.
Inventors: |
Mizukoshi, Masataka;
(Kawasaki, JP) ; Ishizuki, Yoshikatsu; (Kawasaki,
JP) ; Nakagawa, Kanae; (Kawasaki, JP) ;
Okamoto, Keishiro; (Kawasaki, JP) ; Teshirogi,
Kazuo; (Kawasaki, JP) ; Sakai, Taiji;
(Kawasaki, JP) |
Correspondence
Address: |
WESTERMAN, HATTORI, DANIELS & ADRIAN, LLP
1250 CONNECTICUT AVENUE, NW
SUITE 700
WASHINGTON
DC
20036
US
|
Assignee: |
FUJITSU LIMITED
Kawasaki
JP
|
Family ID: |
34797095 |
Appl. No.: |
11/083926 |
Filed: |
March 21, 2005 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11083926 |
Mar 21, 2005 |
|
|
|
PCT/JP03/05092 |
Apr 22, 2003 |
|
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Current U.S.
Class: |
257/737 ;
257/E21.508; 257/E21.511; 257/E21.514; 257/E23.021 |
Current CPC
Class: |
H01L 2224/13155
20130101; H01L 2924/01029 20130101; H01L 2924/0132 20130101; H01L
24/29 20130101; H01L 2224/83192 20130101; H01L 2224/48227 20130101;
H01L 2224/81075 20130101; H01L 24/11 20130101; H01L 2224/05155
20130101; H01L 2224/48465 20130101; H01L 2924/0103 20130101; H01L
2924/0105 20130101; H01L 2924/014 20130101; H01L 2224/11602
20130101; H01L 2224/13144 20130101; H01L 21/78 20130101; H01L
2224/75252 20130101; H01L 2224/13111 20130101; H01L 2924/01011
20130101; H01L 22/12 20130101; H01L 2224/29111 20130101; H01L 24/94
20130101; H01L 2224/11019 20130101; H01L 2924/01079 20130101; H01L
2924/0133 20130101; H01L 2224/16225 20130101; H01L 2224/83193
20130101; H01L 22/14 20130101; H01L 2224/05568 20130101; H01L
2224/13012 20130101; H01L 2224/73104 20130101; H01L 21/4853
20130101; H01L 2224/838 20130101; H01L 2924/01015 20130101; H01L
24/81 20130101; H01L 2924/01006 20130101; H01L 2924/0781 20130101;
H01L 2224/05001 20130101; H01L 2224/1184 20130101; H01L 2224/13099
20130101; H01L 2924/01018 20130101; H01L 2924/01019 20130101; H01L
2224/81801 20130101; H01L 2924/00013 20130101; H01L 2224/1134
20130101; H01L 2224/11464 20130101; H01L 2224/119 20130101; H01L
2924/01033 20130101; H01L 2924/01047 20130101; H01L 24/05 20130101;
H01L 24/13 20130101; H01L 2224/75 20130101; H01L 24/27 20130101;
H01L 2224/05572 20130101; H01L 2224/05644 20130101; H01L 2224/48091
20130101; H01L 22/26 20130101; H01L 24/83 20130101; H01L 2224/05022
20130101; H01L 2224/16145 20130101; H01L 2924/15788 20130101; H01L
2224/05023 20130101; H01L 2224/05124 20130101; H01L 2224/274
20130101; H01L 2224/749 20130101; H01L 2924/01078 20130101; H01L
2924/12042 20130101; H01L 2224/11632 20130101; H01L 2924/01005
20130101; H01L 2224/0508 20130101; H01L 2924/01013 20130101; H01L
2924/01082 20130101; H01L 2224/48091 20130101; H01L 2924/00014
20130101; H01L 2924/0132 20130101; H01L 2924/01005 20130101; H01L
2924/01028 20130101; H01L 2924/0133 20130101; H01L 2924/01005
20130101; H01L 2924/01015 20130101; H01L 2924/01028 20130101; H01L
2924/0132 20130101; H01L 2924/01015 20130101; H01L 2924/01028
20130101; H01L 2924/0133 20130101; H01L 2924/01028 20130101; H01L
2924/01029 20130101; H01L 2924/01047 20130101; H01L 2924/0132
20130101; H01L 2924/0103 20130101; H01L 2924/0105 20130101; H01L
2924/0132 20130101; H01L 2924/01047 20130101; H01L 2924/0105
20130101; H01L 2224/13111 20130101; H01L 2924/01047 20130101; H01L
2924/00014 20130101; H01L 2224/13111 20130101; H01L 2924/0103
20130101; H01L 2924/00014 20130101; H01L 2224/48465 20130101; H01L
2224/48227 20130101; H01L 2924/00 20130101; H01L 2224/48465
20130101; H01L 2224/48091 20130101; H01L 2924/00 20130101; H01L
2924/00013 20130101; H01L 2224/29099 20130101; H01L 2924/15788
20130101; H01L 2924/00 20130101; H01L 2924/12042 20130101; H01L
2924/00 20130101; H01L 2224/13144 20130101; H01L 2924/00014
20130101; H01L 2224/05644 20130101; H01L 2924/00014 20130101; H01L
2224/05124 20130101; H01L 2924/00014 20130101; H01L 2224/05155
20130101; H01L 2924/00014 20130101; H01L 2224/1134 20130101; H01L
2924/00014 20130101 |
Class at
Publication: |
257/737 |
International
Class: |
H01L 023/48 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 27, 2002 |
JP |
2002-381582 |
Claims
What is claimed is:
1. A method for forming on a front face of a substrate bumps for
establishing an electrical connection with an external part, said
method comprising the steps of: forming the plurality of bumps and
an insulating film between the bumps on the front face of the
substrate; performing planarization by cutting using a tool so that
surfaces of the bumps and a surface of the insulating film become
continuously flat; and removing the insulating film.
2. The method for forming bumps according to claim 1, wherein in
forming the bumps, the insulating film is processed to form a mask
having a plurality of openings in a form of electrodes, and then
the openings of the mask are filled with a conductive material.
3. The method for forming bumps according to claim 2, wherein the
openings of the mask are filled with the conductive material by a
plating method.
4. The method for forming bumps according to claim 1, wherein the
bumps are formed by a nickel-based electroless plating method, and
wherein in cutting the surfaces of the bumps, layers with a high
concentration of phosphor created in surface layers of the bumps
are removed.
5. The method for forming bumps according to claim 4, wherein after
the bumps are formed by the nickel-based electroless plating
method, the insulating film is formed to cover the bumps.
6. The method for forming bumps according to claim 1, wherein LSI
elements are formed on the substrate, and the bumps are connected
with the LSI elements.
7. The method for forming bumps according to claim 1, wherein the
surfaces of the bumps are subjected to the cutting so that the
bumps have the same height on the substrate.
8. The method for forming bumps according to claim 7, further
comprising the step of: performing planarization by machining on a
rear face of the substrate with reference to the front face of the
substrate, wherein the planarization of the surfaces of the bumps
and the surface of the insulating film is performed with reference
to the rear face of the substrate.
9. The method for forming bumps according to claim 8, wherein said
steps are performed on a plurality of the substrates to uniformize
the substrates so that the thicknesses of the substrates become
identical.
10. The method for forming bumps according to claim 8, wherein in
performing planarization of the surfaces of the bumps and the
surface of the insulating film, correction of parallelism of the
semiconductor substrate is performed with reference to the rear
face, and a position of the front face is detected, so that a
cutting amount is calculated from the detected front face for
control.
11. The method for forming bumps according to claim 10, wherein in
detecting the position of the front face of the substrate, laser
light is applied to the insulating film at a plurality of points
within a peripheral region of the front face to heat and scatter an
insulator to thereby expose portions of the front face.
12. The method for forming bumps according to claim 10, wherein in
detecting the position of the front face of the substrate, infrared
laser light is applied to the rear face and reflected light from
the front face is measured.
13. A semiconductor device, comprising: a pair of semiconductor
substrates each having a plurality of bumps formed on a front face
thereof for establishing an electrical connection with an external
part, surfaces of the bumps being continuously uniformly planarized
by cutting using a tool above each of the semiconductor substrates,
and the semiconductor substrates being integrated, with the
planarized surfaces of the bumps opposing each other and
connected.
14. The semiconductor device according to claim 13, wherein LSI
elements are provided on each of the semiconductor substrates, in
which the bumps are connected with the LSI elements on each of the
semiconductor substrates.
15. The semiconductor device according to claim 13, wherein the
bumps are made to have the same height on each of the semiconductor
substrates.
16. The semiconductor device according to claim 15, wherein
machining is performed on a rear face side of each of the
semiconductor substrates with reference to the front face so that
the rear face is planarized and the thickness of the substrate is
made uniform.
17. A method for manufacturing a semiconductor device, comprising
the steps of: forming bumps on each front face of a pair of
semiconductor substrates in a manner to bury the bumps in an
insulating film; performing planarization by cutting using a tool
so that surfaces of the bumps and a surface of the insulating film
become continuously flat; removing the insulating film; and
integrating the semiconductor substrates, with the planarized
surfaces of the bumps opposing each other and connected.
18. The method for manufacturing a semiconductor device according
to claim 17, wherein LSI elements are provided on each of the
semiconductor substrates, in which the bumps are connected to the
LSI elements on each of the semiconductor substrates.
19. The method for manufacturing a semiconductor device according
to claim 17, further comprising the step of: performing
planarization by machining on a rear face of the substrate with
reference to the front face of the substrate, wherein the
planarization of the surfaces of the bumps and the surface of the
insulating film is performed with reference to the rear face of
each of the semiconductor substrates.
20. A method for forming on a front face of a substrate bumps for
establishing an electrical connection with an external part, said
method comprising the steps of: forming the plurality of bumps on
the front face of the substrate; and performing planarization by
cutting using a tool so that surfaces of the plurality of bumps
become continuously flat.
21. A method for manufacturing a semiconductor device, comprising
the steps of: forming a plurality of bumps on each front face of a
pair of semiconductor chips; performing planarization by cutting
using a tool so that surfaces of the plurality of bumps become
continuously flat; and integrating the pair of semiconductor chips
having the plurality of bumps having the planarized surfaces, with
the bumps connected opposing each other.
22. The method for manufacturing a semiconductor device according
to claim 21, further comprising the step of: performing
planarization by machining on each rear face with reference to each
front face of the pair of semiconductor chips, wherein the
planarization of the surfaces of the bumps is performed by the
cutting with reference to the rear face.
23. The method for manufacturing a semiconductor device according
to claim 21, wherein after the bumps are formed, a resin film is
formed to cover the bumps, and planarization is performed by the
cutting so that the surfaces of the bumps and a surface of the
resin film become continuously flat.
24. A semiconductor device, comprising: a pair of semiconductor
chips each having a plurality of bumps formed on a front face
thereof for establishing an electrical connection with an external
part, surfaces of the bumps being continuously uniformly planarized
by cutting using a tool above each of the semiconductor chips, and
the semiconductor chips being integrated, with the planarized
surfaces of the bumps opposing each other and connected.
25. The semiconductor device according to claim 24, wherein
machining is performed on a rear face side of each of the
semiconductor chips with reference to the front face so that the
rear face is planarized and the thickness of a substrate is made
uniform.
26. The semiconductor device according to claim 24, wherein a resin
film is formed to cover the bumps, and the surfaces of the bumps
and a surface of the resin film are planarized to be continuously
uniformly flat.
27. A method for forming on a front face of a semiconductor
substrate stud bumps using a wire bonding method, the stud bumps
being bumps for establishing an electrical connection with an
external part, said method comprising the steps of: forming a
plurality of projections using a bonding wire at electrical
connecting points on the front face of the semiconductor substrate;
and performing planarization by cutting using a tool so that top
surfaces of the plurality of projections become continuously flat
to thereby form the stud bumps.
28. The method for forming bumps according to claim 27, wherein the
cutting is repeatedly performed until the intensity of laser light
reaches a predetermined value for all of the projections, the
intensity being detected by a method using a detecting apparatus
comprising a laser emitter and a detector to sweep a laser beam
across the top surface of the projection after the machining to
detect laser light reflected off the top surface, by the
detector.
29. The method for forming bumps according to claim 28, wherein the
detector is placed at a rear in a traveling direction of the tool
and is moved in synchronism with an operation of the tool.
30. The method for forming bumps according to claim 27, further
comprising the steps of: forming a protective film to cover the
plurality of projections; and performing planarization by the
cutting so that top surfaces of the plurality of projections and a
surface of the protective film become continuously flat, and then
removing the protective film.
31. A semiconductor device, comprising: a semiconductor chip having
a plurality of stud bumps formed on a front face thereof using a
wire bonding method, the stud bumps being bumps for establishing an
electrical connection with an external part, top surfaces of the
plurality of stud bumps being continuously uniformly planarized by
cutting using a tool above the semiconductor chip.
32. A method for manufacturing a semiconductor device, comprising
the steps of: forming a plurality of bumps on a front face of a
semiconductor substrate; performing planarization by cutting using
a tool so that surfaces of the plurality of bumps become
continuously flat; cutting out each semiconductor chip from the
semiconductor substrate having the plurality of bumps with the
planarized surfaces; and connecting the bump of the semiconductor
chip with one end portion of a lead terminal.
33. The method for manufacturing a semiconductor device according
to claim 32, further comprising the step of: performing
planarization by machining on a rear face with reference to the
front face of the semiconductor substrate, wherein the
planarization of the surfaces of the bumps is performed by the
cutting with reference to the rear face.
34. A method for manufacturing a semiconductor device, comprising
the steps of: forming a plurality of projections using a wire
bonding method at electrical connecting points on a front face of a
semiconductor substrate; performing planarization by cutting using
a tool so that top surfaces of the plurality of projections become
continuously flat to thereby form stud bumps; cutting out each
semiconductor chip from the semiconductor substrate having the
plurality of stud bumps formed thereon; and connecting the stud
bump on the semiconductor chip with one end portion of a lead
terminal.
35. The method for manufacturing a semiconductor device according
to claim 34, further comprising the step of: performing
planarization by machining on a rear face with reference to the
front face of the semiconductor substrate, wherein the
planarization of the surfaces of the bumps is performed by the
cutting with reference to the rear face.
36. The method for manufacturing a semiconductor device according
to claim 34, further comprising the step of: performing inspection
by bringing a probe into contact with the surface of the bump,
after the surface of the bump is planarized and before the bump is
connected with the lead terminal.
37. A semiconductor device, comprising: a semiconductor chip having
a plurality of bumps formed on a front face thereof for
establishing an electrical connection with an external part,
surfaces of the bumps being continuously uniformly planarized above
the semiconductor chip, and the bump on the semiconductor chip
being integrally connected with one end portion of a lead
terminal.
38. The semiconductor device according to claim 37, wherein the
bumps is made of gold, and the one end portion of the lead terminal
has been subjected to surface treatment with gold or tin.
39. A semiconductor device, comprising: a semiconductor chip having
a plurality of stud bumps formed on a front face thereof using a
wire bonding method, the stud bumps being a plurality of bumps for
establishing an electrical connection with an external part,
surfaces of the stud bumps being continuously uniformly planarized
above the semiconductor chip, and the stud bump on the
semiconductor chip being integrally connected with one end portion
of a lead terminal.
40. The semiconductor device according to claim 39, wherein the
stud bump is made of gold, and the one end portion of the lead
terminal has been subjected to surface treatment with gold or
tin.
41. A method for manufacturing a semiconductor device, comprising
the steps of: introducing a semiconductor chip having a plurality
of electrodes formed on a front face thereof into an inert
atmosphere and performing planarization by cutting using a tool so
that surfaces of the plurality of electrodes become continuously
flat; and integrally connecting the plurality of electrodes on the
semiconductor chip and a circuit board in a state in which the
planarized surfaces of the plurality of electrodes are kept clean
in the inert atmosphere.
42. The method for manufacturing a semiconductor device according
to claim 41, wherein a plurality of electrodes formed on a front
face of the circuit board have been subjected to planarization by
cutting using a tool so that the surfaces thereof become
continuously flat, and wherein the semiconductor chip and the
circuit board are integrated, with the surfaces of the respective
electrodes connected opposing each other.
43. A semiconductor manufacturing apparatus, comprising: a cutting
unit having a tool; a joining unit joining a pair of bases
introduced; and an inert atmosphere unit keeping an environment of
said cutting unit and said joining unit in a state of an inert
atmosphere, said cutting unit having a function of performing
planarization by cutting using the tool at least on one of the pair
of bases having a plurality of electrodes formed on front faces
thereof in the inert atmosphere so that surfaces of the plurality
of electrodes become continuously flat, and said joining unit
having a function of integrating the pair of bases by connecting
the plurality of electrodes in the state in which the planarized
surfaces of the plurality of electrodes are kept clean in the inert
atmosphere.
44. A substrate processing apparatus in forming on a front face of
a substrate bumps for establishing an electrical connection with an
external part, comprising: a substrate supporting table including a
flat supporting face and vacuum-sucking one face of the substrate
to the supporting face to forcibly support and secure the one face
as a flat reference face; and a tool cutting another face of the
substrate, wherein the substrate having the plurality of bumps and
an insulating film between the bumps formed on the front face
thereof is supported and secured on said supporting table, and
subjected to planarization by the cutting using the tool so that
surfaces of the bumps and a surface of the insulating film become
continuously flat.
45. The substrate processing apparatus according to claim 44,
wherein a rear face of the substrate is cut by the tool using the
front face of the substrate as a reference face through use of said
substrate supporting table, and then the front face of the
substrate is cut by the tool using the rear face of the substrate
as a reference face through use of said supporting table, to
thereby perform planarization so that the surfaces of the bumps and
the surface of the insulating film become continuously flat.
46. The substrate processing apparatus according to claim 44,
wherein correction of parallelism of the semiconductor substrate is
performed with reference to the rear face, and a position of a wire
formation face is detected, so that a cutting amount is calculated
from the detected wire formation face for control.
47. The substrate processing apparatus according to claim 46,
wherein when the position of the wire formation face is detected,
laser light is applied to the insulating film at a plurality of
points within a peripheral region of the wire formation face to
heat and scatter an insulator to thereby expose portions of the
wire formation face.
48. The substrate processing apparatus according to claim 46,
wherein when the position of the wire formation face is detected,
infrared laser light is applied to the rear face and reflected
light from the wire formation face is measured.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Application No.
2002-381582, filed on Dec. 27, 2002, the entire contents of which
are incorporated herein by reference.
TECHNICAL FIELD
[0002] The present invention relates to a method for forming on the
front face of a substrate fine bumps for establishing an electrical
connection with an external part, a semiconductor device and a
method for manufacturing the same, a substrate processing
apparatus, and a semiconductor manufacturing apparatus.
BACKGROUND ART
[0003] Conventionally, for a fine metal terminal for establishing
an electrical connection with an external part on the front face of
a semiconductor substrate, a gold (Au) bump or the like is used.
This Au bump is formed by plating and thus has a large surface
roughness. To planarize such a metal terminal, a chemical
mechanical polishing (CMP) method is used. This method presses a
flat polishing pad against a metal and a resin, which are faces to
be processed have been formed relatively flat in advance, to
planarize with high accuracy their surfaces chemically and
mechanically using slurry (a chemical polishing agent). The CMP is
finished at a stopper layer which is a rigid resin or a metal face
provided in advance. The CMP method is a method not depending on a
TTV (total thickness variation) that is defined by variations in
thickness of a semiconductor substrate or by the difference between
a maximum thickness and a minimum thickness of a semiconductor
substrate.
[0004] Further, to join the Au bump or the like in the conventional
art that has a large surface roughness, a mounting method is
required that loads the bump with a load, heat, ultrasound, or the
like until the roughness is eliminated.
[0005] In addition to the CMP, some other planarizing methods
using, for example, a cutting tool have been devised (see, for
example, Japanese Patent Application Laid-open No. Hei 7-326614,
Japanese Patent Application Laid-open No. Hei 8-11049, Japanese
Patent Application Laid-open No. Hei 9-82616, and Japanese Patent
Application Laid-open No. 2000-173954). However, any of them aims
to planarize an SOG film within a partial region on an LSI, and is
a method of cutting with reference to a face to be cut, which does
not depend on the TTV of a semiconductor substrate similarly to the
CMP. Further, there is another method of exposing a surface of a
bump by cutting (see Japanese Patent Application Laid-open No.
2000-173954 (Japanese Patent Application No. Hei 10-345201)), which
aims to planarize a bump portion formed on an LSI, and is a method
of cutting with reference to a face to be cut, which does not
depend on the TTV of a semiconductor substrate.
[0006] As described above, the Au bump is used for fine connection,
but it is difficult to join the bumps because of the large surface
roughness of the bumps. Further, when the CMP is used to
concurrently planarize a metal such as Au and a resin, a depression
called dishing appears caused by the difference in polishing speed
between the metal and the resin. Due to the dishing, it is
necessary to load the bump with a load, heat, ultrasound, or the
like to reliably join the bumps.
[0007] The present invention has been developed in consideration of
the above-described problems, and has an object to provide, in
place of the CMP, a method for forming bumps, which makes it
possible to planarize surfaces of fine bumps formed on a substrate
at a low cost and a high speed and to connect the bumps with each
other easily and reliably without causing any inconvenience such as
dishing or the like, a reliable semiconductor device and a method
for forming the same, and a semiconductor manufacturing
apparatus.
SUMMARY OF THE INVENTION
[0008] A method for forming bumps of the present invention is a
method for forming on a front face of a substrate bumps for
establishing an electrical connection with an external part,
including the steps of: forming the plurality of bumps and an
insulating film between the bumps on the front face of the
substrate; performing planarization by cutting using a tool so that
surfaces of the bumps and a surface of the insulating film become
continuously flat; and removing the insulating film.
[0009] A semiconductor device of the present invention, includes: a
pair of semiconductor substrates each having a plurality of bumps
formed on a front face thereof for establishing an electrical
connection with an external part, surfaces of the bumps being
continuously uniformly planarized above each of the semiconductor
substrates, and the semiconductor substrates being integrated, with
the planarized surfaces of the bumps opposing each other and
connected.
[0010] A method for manufacturing a semiconductor device of the
present invention includes the steps of: forming bumps on each
front face of a pair of semiconductor substrates in a manner to
bury the bumps in an insulating film; performing planarization by
cutting using a tool so that surfaces of the bumps and a surface of
the insulating film become continuously flat; removing the
insulating film; and integrating the semiconductor substrates, with
the planarized surfaces of the bumps opposing each other and
connected.
[0011] A method for forming bumps of the present invention is a
method for forming on a front face of a substrate bumps for
establishing an electrical connection with an external part,
including the steps of: forming the plurality of bumps on the front
face of the substrate; and performing planarization by cutting
using a tool so that surfaces of the plurality of bumps become
continuously flat.
[0012] A method for manufacturing a semiconductor device of the
present invention includes the steps of: forming a plurality of
bumps on each front face of a pair of semiconductor chips;
performing planarization by cutting using a tool so that surfaces
of the plurality of bumps become continuously flat; and integrating
the pair of semiconductor chips having the plurality of bumps
having the planarized surfaces, with the bumps connected opposing
each other.
[0013] A semiconductor device of the present invention includes: a
pair of semiconductor chips each having a plurality of bumps formed
on a front face thereof for establishing an electrical connection
with an external part, surfaces of the bumps being continuously
uniformly planarized above each of the semiconductor chips, and the
semiconductor chips beingintegrated, with the planarized surfaces
of the bumps opposing each other and connected.
[0014] A method for forming bumps of the present invention is a
method for forming on a front face of a semiconductor substrate
stud bumps using a wire bonding method, the stud bumps being bumps
for establishing an electrical connection with an external part,
including the steps of: forming a plurality of projections using a
bonding wire at electrical connecting points on the front face of
the semiconductor substrate; and performing planarization by
cutting using a tool so that top surfaces of the plurality of
projections become continuously flat to thereby form the stud
bumps.
[0015] A semiconductor device of the present invention includes: a
semiconductor chip having a plurality of stud bumps formed on a
front face thereof using a wire bonding method, the stud bumps
being bumps for establishing an electrical connection with an
external part, top surfaces of the plurality of stud bumps being
continuously uniformly planarized above the semiconductor chip.
[0016] A method for manufacturing a semiconductor device of the
present invention includes the steps of: forming a plurality of
bumps on a front face of a semiconductor substrate; performing
planarization by cutting using a tool so that surfaces of the
plurality of bumps become continuously flat; cutting out each
semiconductor chip from the semiconductor substrate having the
plurality of bumps with the planarized surfaces; and connecting the
bump of the semiconductor chip with one end portion of a lead
terminal.
[0017] A method for manufacturing a semiconductor device of the
present invention includes the steps of: forming a plurality of
projections using a wire bonding method at electrical connecting
points on a front face of a semiconductor substrate; performing
planarization by cutting using a tool so that top surfaces of the
plurality of projections become continuously flat to thereby form
stud bumps; cutting out each semiconductor chip from the
semiconductor substrate having the plurality of stud bumps formed
thereon; and connecting the stud bump on the semiconductor chip
with one end portion of a lead terminal.
[0018] A semiconductor device of the present invention includes: a
semiconductor chip having a plurality of bumps formed on a front
face thereof for establishing an electrical connection with an
external part, surfaces of the bumps being continuously uniformly
planarized above the semiconductor chip, and the bump on the
semiconductor chip being integrally connected with one end portion
of a lead terminal.
[0019] A semiconductor device of the present invention includes: a
semiconductor chip having a plurality of stud bumps formed on a
front face thereof using a wire bonding method, the stud bumps
being a plurality of bumps for establishing an electrical
connection with an external part, surfaces of the stud bumps being
continuously uniformly planarized above the semiconductor chip, and
the stud bump on the semiconductor chip being integrally connected
with one end portion of a lead terminal.
[0020] A method for manufacturing a semiconductor device of the
present invention includes the steps of: introducing a
semiconductor chip having a plurality of electrodes formed on a
front face thereof into an inert atmosphere and performing
planarization by cutting using a tool so that surfaces of the
plurality of electrodes become continuously flat; and integrally
connecting the plurality of electrodes on the semiconductor chip
and a circuit board in a state in which the planarized surfaces of
the plurality of electrodes are kept clean in the inert
atmosphere.
[0021] A semiconductor manufacturing apparatus of the present
invention includes: a cutting unit having a tool; a joining unit
joining a pair of bases introduced; and an inert atmosphere unit
keeping an environment of the cutting unit and the joining unit in
a state of an inert atmosphere, the cutting unit having a function
of performing planarization by cutting using the tool at least on
one of the pair of bases having a plurality of electrodes formed on
front faces thereof in the inert atmosphere so that surfaces of the
plurality of electrodes become continuously flat, and the joining
unit having a function of integrating the pair of bases by
connecting the plurality of electrodes in the state in which the
planarized surfaces of the plurality of electrodes are kept clean
in the inert atmosphere.
[0022] A substrate processing apparatus of the present invention is
a substrate processing apparatus in forming on a front face of a
substrate bumps for establishing an electrical connection with an
external part, including: a substrate supporting table including a
flat supporting face and vacuum-sucking one face of the substrate
to the supporting face to forcibly support and secure the one face
as a flat reference face; and a tool cutting another face of the
substrate, wherein the substrate having the plurality of bumps and
an insulating film between the bumps formed on the front face
thereof is supported and secured on the supporting table, and
subjected to planarization by the cutting using the tool so that
surfaces of the bumps and a surface of the insulating film become
continuously flat.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] FIG. 1A to FIG. 1D are schematic cross-sectional views
showing a method for forming bumps according to a first embodiment
in the order of steps;
[0024] FIG. 2A and FIG. 2B are schematic cross-sectional views
showing the method for forming bumps according to the first
embodiment in the order of steps;
[0025] FIG. 3A and FIG. 3B are views showing the result of
planarization by cutting;
[0026] FIG. 4A and FIG. 4B are a schematic cross-sectional view and
plan view showing a concrete example of the planarization by the
cutting;
[0027] FIG. 5 is a schematic cross-sectional view showing a
concrete example of the planarization by the cutting;
[0028] FIG. 6 is a block diagram showing a configuration of a
cutting apparatus;
[0029] FIG. 7 is a schematic configuration diagram of the cutting
apparatus;
[0030] FIG. 8 is a flowchart of cutting steps;
[0031] FIG. 9A to 9C are schematic cross-sectional views showing a
method for manufacturing a semiconductor device according to a
second embodiment in the order of steps;
[0032] FIG. 10A to FIG. 10F are schematic cross-sectional views
showing a method for forming bumps according to the second
embodiment in the order of steps;
[0033] FIG. 11A and FIG. 11B are schematic cross-sectional views
showing a method for manufacturing a semiconductor device according
to a third embodiment in the order of steps;
[0034] FIG. 12A to FIG. 12C are schematic cross-sectional views
showing a method for manufacturing a semiconductor device according
to Modification 1 of the third embodiment in the order of
steps;
[0035] FIG. 13A to FIG. 13C are schematic cross-sectional views
showing a method for manufacturing a semiconductor device according
to Modification 2 of the third embodiment in the order of
steps;
[0036] FIG. 14A to FIG. 14F are schematic cross-sectional views
showing a method for manufacturing a semiconductor device according
to a fourth embodiment in the order of steps;
[0037] FIG. 15A to FIG. 15D are views showing a cutting end point
detecting method according to the fourth embodiment;
[0038] FIG. 16 is a schematic cross-sectional view showing a method
for manufacturing a semiconductor device according to a fifth
embodiment;
[0039] FIG. 17 is a schematic cross-sectional view showing the
method for manufacturing a semiconductor device according to the
fifth embodiment; and
[0040] FIG. 18 is a schematic diagram showing a semiconductor
manufacturing apparatus according to a sixth embodiment.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Basic Gist of the Present Invention
[0041] First of all, a basic gist of the present invention will be
described.
[0042] The present inventor has devised application of cutting
using a tool, in place of the CMP method, as a technique of
planarizing the surfaces of a number fine bumps formed on a
substrate at a time at a low cost and a high speed. This cutting,
even in the case in which the bumps are formed buried in an
insulating film on a semiconductor substrate, can continuously cut
a metal and an insulator above the substrate at a time, unlike the
CMP method which depends on the polishing speed or the like of the
metal and the insulator, to thereby uniformly planarize both of
them as a whole without causing inconvenience such as dishing or
the like. Metals such as copper, aluminum, nickel, and the like and
insulating materials such as polyimide and the like are materials
which can be easily cut by the tool. In the present invention, it
is preferable to employ as the metal material of the bumps and the
insulating material, a ductile metal as the former and a resin or
the like with a modulus of rigid of, for example, 200 GPa or higher
as the latter.
[0043] In this case, to utilize the above-described cutting for
planarizing the bump surface, the cutting is preferably performed
with reference to a back face (a rear face) of the substrate.
Generally, the TTV of a silicon substrate ranges from 1 .mu.m to 5
.mu.m, and a TTV of about 5 .mu.m never affects photolithography in
an LSI process and is thus generally left out of consideration.
However, the cutting is greatly affected by the value of the TTV.
The flatness accuracy by cutting never becomes equal to or less
than the TTV value. Accordingly, when utilizing the cutting for
planarizing the semiconductor substrate, it is first necessary to
control the TTV of the substrate so that it falls within a target
cutting accuracy.
[0044] In consideration of the above circumstances, the present
inventor has devised a technique of cutting a rear face of a
substrate with reference to its front face to restrain the TTV of a
semiconductor substrate so that it falls within the target cutting
accuracy, as a concrete method of surely performing planarization
of the bump surface when using the above-described cutting. In this
case, it is ideal to decrease the TTV and restrain variations in
thickness of an individual semiconductor substrate to within the
cutting accuracy. However, if only the TTV can be decreased, the
thickness of the individual semiconductor substrate can be detected
during the cutting. The cutting amount is controllable by detecting
the thickness of the individual semiconductor substrate.
[0045] Bumps include, in addition to a bump formed by the plating
method, a bump formed by a wire bonding method, that is, by
pressure-bonding a mass in a ball shape formed by melting the tip
of a bonding wire onto an electrode pad and tearing off the wire
(hereinafter referred to as a stud bump).
[0046] When forming the stud bump, a projection in a pin shape is
formed by the tear of the bonding wire, and therefore that
projection needs to be planarized. In the present invention, a
planarizing method by the above-described cutting is also applied
to the stud bump. In this case, projections vary in height during
the tear (precut) of the wire, and the planarization is performed
to align them with the lowest bump. However, the higher the stud
bump is, the more the stud bump mitigates the stress on a device to
increase the device life, and therefore it is necessary to define
the height of the projections. In the present invention, the height
of the projection from the electrode pad during the precut is
defined to be double or more the wire diameter, and the point of
time when the diameters of cut faces of all of the stud bumps
become equal to or larger than the wire diameter is assumed as the
end point of the cutting. This can make the height of the stud bump
after the cutting planarization 1.5 times or more that when the
wire diameter is not defined, thereby making it possible to
mitigate the stress on a semiconductor element, resulting in
increased device life.
[0047] Then, the TTV is controlled in the above-described manner,
and the surfaces of the fine bumps are planarized by the cutting,
and then the individual semiconductor chip which will be a
semiconductor component is cut out from a semiconductor substrate
(wafer). Thereafter, the semiconductor substrate with the
planarized front face and the semiconductor chip, or the
semiconductor chips are joined, with their bumps opposing each
other and electrically connected. In this event, since both of the
top surfaces of the opposing bumps are planarized with high
accuracy, they are joined, unlike the conventional art, without
requiring a high temperature, a high pressure, and so on.
[0048] Here the present inventor has further found concrete
conditions and states for surely joining the opposing bumps. In
consideration that it is ideal to keep the bumps in the planarized
state immediately after the cutting even during the above-described
joining, the present inventor has devised performance of both of
the planarization step and the joining step in a cleaning
atmosphere, specifically, in an inert atmosphere in order to keep
as long as possible the planarized state immediately after the
cutting. This can be addressed by addition of a cleaning step using
Ar plasma or the like immediately before the joining step, which
brings about a drawback, that is, an increase in the number of
steps. In the present invention, the planarized state very close to
the ideal state can be relatively easily maintained to ensure
joining of the bumps without causing an increase in the number of
steps.
[0049] The present inventor focuses attention on the state of the
semiconductor chip as another aspect of the present invention. More
specifically, the TTV of the semiconductor substrate is important
as described above at a wafer level, whereas an individually
separated semiconductor chip or the like is affected by the TTV
within a chip area only to an almost negligible extent during
cutting.
[0050] Hence, the present inventor has devised planarization in
which each semiconductor chip is first cut out from the
semiconductor substrate and then the surfaces of fine bumps are
planarized in the state of the semiconductor chip by the
above-described cutting using the tool. Then, the semiconductor
chips are joined, with their bumps opposing each other and
electrically connected. This can omit the step of controlling the
TTV and easily join the bumps.
[0051] Further, in the present invention, the above-described
cutting technique is also applied to a semiconductor device by a
so-called TAB bonding method.
[0052] Generally, in the plating bump method, the TAB connection
requires directly aligning with a gold plated bump a copper foil
lead in a strip shape which has undergone surface treatment with
gold, heating them to 300.degree. C. or higher, and
pressure-bonding with 30 g or greater per bump. On the other hand,
in the case of using the stud bump method, it is required to press
the semiconductor chip formed with stud bumps in advance against a
glass plate or a metal plate and heat it to thereby process the
tips of the stud bumps to be flat for use.
[0053] On plating end faces, there is specific metallic and organic
contamination in depressions and projections and on its surface.
Further, there occur variations in height of plating within a chip
to a level of several microns. When the TAB bonding is performed
for these plating end faces, a high temperature and a high load are
required. The connection of leads with fine pitches is susceptible
to positional displacement at a higher temperature during bonding
because the difference in coefficient of thermal expansion between
copper and silicon becomes larger. On the other hand, the stud
bumps have large variations in height and their shapes are unfixed
and thus require a much higher temperature and a higher load, so
that connection with fine pitches is similarly difficult.
[0054] To decrease the positional displacement during the TAB
bonding, it is necessary to lower the temperature and to bring
copper lead terminals into contact with the bumps at the same time.
In the present invention, the cutting technique through use of the
tool can be used to planarize by the cutting the surfaces of the
plated bumps and the stud bumps for cleaning them, thereby
decreasing the temperature and the load during the TAB bonding so
as to connect the leads with fine pitches without positional
displacement.
CONCRETE EMBODIMENTS OF THE PRESENT INVENTION
[0055] Hereinafter, based on the above-described basic gist,
concrete embodiments of the present invention will be described in
detail using the drawings.
First Embodiment
[0056] Here a silicon semiconductor substrate is illustrated as an
example of a substrate to disclose a method for forming bumps
provided on the semiconductor substrate to electrically connect to
an external part, and a semiconductor device using this method and
a method for manufacturing the same.
[0057] (Method for Forming Bump)
[0058] FIG. 1A to FIG. 1D, FIG. 2A, and FIG. 2B are schematic
cross-sectional views showing a method for forming bumps according
to this embodiment in the order of steps.
[0059] First, a silicon semiconductor substrate 1 is prepared, and
desired LSI semiconductor elements (not shown) are formed within
element formation regions on a substrate front face 1a. For the
semiconductor substrate 1 on which the LSI semiconductor elements
and the like are formed in this manner, steps will be described
below.
[0060] As shown in FIG. 1A, the silicon semiconductor substrate is
generally not uniform in thickness and has undulation as shown in
the drawing. Hence, as a preceding step for performing
later-described cutting using a tool for the front face 1a of the
semiconductor substrate 1, its rear face 1b is planarized.
[0061] Specifically, a substrate supporting table (not shown)
having a supporting face made flat is prepared, and the front face
1a is sucked, for example, by vacuum suction to this supporting
face so that the semiconductor substrate 1 is secured to the
substrate supporting table. In this event, the front face 1a is
forcibly made flat due to the suction to the supporting face,
whereby the front face 1a becomes a reference face for
planarization of the rear face 1b. In this state, machining, that
is, mechanical-cutting here, is performed for the rear face 1b to
cut and remove a protruding portion 1c on the rear face 1b for
planarization. In this case, the amount of cutting the rear face 1b
is preferably controlled based on the distance from the front face
1a. This controls the semiconductor substrate 1 so that its
thickness becomes fixed, specifically the TTV (the difference
between a maximum thickness and a minimum thickness of the
substrate) being a predetermined value or less, specifically the
TTV being 1 .mu.m or less as shown in FIG. 1B.
[0062] Subsequently, as shown in FIG. 1C, after the semiconductor
substrate 1 is detached from the substrate supporting table, a
photosensitive resin, for example, a photoresist is applied onto
the front face 1a of the semiconductor substrate 1, and
photolithography is employed to process the photoresist to form a
resist mask 12 having predetermined bump patterns 12a.
[0063] Subsequently, a metal, for example, a copper film is formed,
for example, by a vapor deposition method using the resist mask 12
as a mask to form plated electrodes (not shown), and then gold (Au)
is deposited using the plated electrodes as seeds to bury the bump
patterns 12a of the resist mask 12 by the plating method, thereby
forming Au projections 2 as shown in FIG. 1D. Note that Cu, Ag, Ni,
Sn, an alloy of these, and so on as well as Au may be used to form
the projections.
[0064] Subsequently, the front face 1a of the semiconductor
substrate 1 is subjected to cutting using the tool for
planarization.
[0065] Specifically, as shown in FIG. 2A, for example, the rear
face 1b is sucked, for example, by vacuum suction to a supporting
face 11a of a substrate supporting table 11, whereby the
semiconductor substrate 1 is secured to the substrate supporting
table 11. In this event, the thickness of the semiconductor
substrate 1 is fixed because of the planarization in FIG. 1B on the
rear face 1b, and further the rear face 1b is forcibly brought into
a state free from undulation and the like because the suction to
the supporting face 11a, whereby the rear face 1b becomes a
reference face for planarization of the front face 1a. In this
state, machining, that is, cutting using a tool 10 made of diamond
or the like here, is performed for surface layers of the Au
projections 2 and the photoresist 12 on the front face 1a to
thereby planarize them so that the surfaces of the Au projections 2
and the resist mask 12 become continuously flat. This planarizes
the top surfaces of the Au projections 2 into mirror surfaces.
[0066] The result of the planarization by the cutting is shown in
microphotographic views and schematic views in FIG. 3A and FIG.
3B.
[0067] It is found that the surface of the Au projection is uneven
as in FIG. 3A before the cutting, whereas the surface of the Au
projection is planarized with high accuracy as shown in FIG. 3B
after the cutting.
[0068] Subsequently, as shown in FIG. 2B, the resist mask 12 is
removed by ashing or the like. In this event, bumps 3 having a
uniform height and top surfaces 3a uniformly planarized which are
formed by cutting the Au projections 2, are formed on the front
face 1a of the semiconductor substrate 1. This semiconductor
substrate 1 is used and brought into, for example, a chip which is
thereafter electrically connected to another semiconductor
substrate 4 via the bumps 3.
[0069] Noted that although one semiconductor substrate is described
in this embodiment, it is preferred to perform the steps of this
embodiment for a plurality of semiconductor substrates constituting
a lot, to uniformize the semiconductor substrates so that they have
the same thickness.
[0070] Further, control in the planarization step in FIG. 2A is
performed by correcting parallelism of the semiconductor substrate
1 with reference to the rear face 1b and detecting a position of
the front face 1a to calculate the cutting amount from the detected
front face 1a as shown in FIG. 4A and FIG. 4B.
[0071] Specifically, it is preferred, when detecting the position
of the front face 1a, to apply laser light 13 to the resist mask
12, as shown in FIG. 4A, at a plurality of points within a
peripheral region of the front face 1a of the semiconductor
substrate 1, for example, three points A, B, and C shown in FIG. 4B
here, and to heat and scatter the resist mask 12 there to thereby
expose portions of the front face 1a.
[0072] In this case, it is also suitable, when detecting the
position of the front face 1a, to fix by suction the semiconductor
substrate 1 to the substrate supporting table 11 formed with an
opening 11b as shown in FIG. 5, and to apply infrared laser light
to the rear face 1b through the opening 11b and measure reflected
light from the front face 1a, for example, by an infrared laser
measuring instrument 14.
[0073] (Configuration of Cutting Apparatus)
[0074] Here a concrete apparatus configuration for performing the
above-described cutting step will be described.
[0075] FIG. 6 is a block diagram showing a configuration of the
cutting apparatus, and FIG. 7 is a similar schematic configuration
diagram. This cutting apparatus constructed having a housing
section 101 which houses a semiconductor substrate; a hand section
102 for carrying the semiconductor substrate 1 to each processing
unit; a sensing section 103 which positions the semiconductor
substrate 1; a chuck table section 104 which chucks the
semiconductor substrate 1 during cutting; a cutting section 105
which performs planarization cutting of the semiconductor substrate
1; a cleaning section 106 which performs cleaning after the
cutting; and a control section 107 which controls these sections.
The chuck table section 104 constitutes the substrate supporting
table (chuck table) 11 which mounts thereon and secures the
semiconductor substrate 1 as described above, and the cutting
section 105 has a rigid tool 10 that is a cutting tool made of
diamond or the like.
[0076] Next, the flow of the cutting step is described using FIG. 7
and FIG. 8.
[0077] First, a carrier hand of the hand section 102 takes out the
semiconductor substrate 1 from a housing cassette 111 of the
housing section 101 in which the semiconductor substrate 1 is
housed. In the housing section 101, an elevator mechanism is
provided and rises/lowers to a level where the carrier hand takes
out the semiconductor substrate 1. Next, the carrier hand
vacuum-sucks the semiconductor substrate and carries it to the
sensing section 103. The carrier hand is a .THETA. three axes and
Z-axis SCARA-type robot and can easily realize handling to each
processing unit. The mechanism of the robot is not limited to this,
but an X- and Y-axes orthogonal-type is also employable.
[0078] In the sensing section 103, the semiconductor substrate 1 is
rotated 360.degree. by a rotation table 113, and a CCD camera 112
captures an image of the outer periphery of the semiconductor
substrate 1, so that a calculating part of the control section 107
processes the result to calculate the center position of the
semiconductor substrate 1.
[0079] Next, the carrier hand corrects the position based on the
result and carries the semiconductor substrate 1 to the chuck table
section 104, and the chuck table 11 secures it by vacuum. This
chuck table 11 becomes a reference face for processing. Therefore,
to maintain the planar accuracy during the securing and processing,
the chuck face is preferably made of a porous material and has a
structure to chuck the entire face of the semiconductor substrate
1. The quality of the material used is metallic, ceramic, resin, or
the like. Opposite the chucked semiconductor substrate 1, a
photosensor part being a light projecting part 114 is located to
measure and calculate the dimensions of the semiconductor substrate
1 in cooperation with a camera part being a light receiving part
115 and feed the result back to an X-axis drive part of the cutting
section 105 to thereby issue a command for the moving amount for
cutting.
[0080] When the face to be cut is a face to be formed with a wire,
it is concretely preferred to apply laser light thereto to heat and
scatter the resist mask as shown in FIGS. 4A and 4B, thereby
exposing the surface. Then, a transmission-type sensor utilizing an
infrared laser beam is used to measure the position as shown in
FIG. 5. Based on the result calculated there, the table, on which
the tool 10 which actually performs cutting is mounted, moves in
the X-direction, and then cutting is started. The tool 10 used here
is made of diamond or the like. In this way, the cutting to the set
dimensions is completed.
[0081] Next, the carrier hand detaches the semiconductor substrate
1 from the chuck table 11 and carries it to the cleaning section.
In the cleaning section 105, residual foreign substances on the
surface after the processing are washed away with cleaning water
while the semiconductor substrate 1 is secured by vacuum and being
rotated. Thereafter, the semiconductor substrate 1 is dried while
the cleaning water is being blown away in a manner that the
semiconductor substrate 1 is being rotated at a high speed while
air is being blown thereto. After the completion of the drying,
again the carrier hand takes out the semiconductor substrate 1 and
houses it into the housing cassette 111 of the housing section
101.
[0082] The above-described steps are performed in a manner that the
rear face is first cut with reference to the face on which the
bumps and the insulating film between the bumps are formed, and
then the surfaces of the bumps and the surface of the insulating
film are cut with reference to the rear face, thereby completing
the planarization.
[0083] (Semiconductor Device and Method for Manufacturing the
Same)
[0084] Next, a method for manufacturing a semiconductor device will
be described using a semiconductor manufacturing apparatus which
performs the above-described method for forming bumps. Note that a
configuration of the semiconductor device will be discussed here
together with the method for manufacturing the same.
[0085] FIG. 9A to FIG. 9C are schematic cross-sectional views
showing the method for manufacturing the semiconductor device
according to this embodiment in the order of steps.
[0086] First, as shown in FIG. 9A, each semiconductor chip 21 is
cut out from a semiconductor substrate 1 which has LSI elements and
the like mounted thereon and bumps 3 with top surfaces 3a
planarized by cutting using a tool, after undergoing the respective
steps illustrated in FIGS. 1A to 1D and FIGS. 2A and 2B.
[0087] Subsequently, as shown in FIG. 9B, a semiconductor substrate
22 having bumps 3 with top surfaces planarized by the cutting using
the tool is prepared, and semiconductor chips 21 are electrically
connected onto the semiconductor substrate 22 through the
respective planarized top surfaces 3a of the bumps 3. Specifically,
the semiconductor substrate 22 and a semiconductor chip 21a are
arranged to oppose each other at the respective top surfaces 3a and
connected with each other by pressure-bonding at room temperatures
to 350.degree. C., about 170.degree. C. here. Since both of the
respective top surfaces 3a are planarized with high accuracy, the
semiconductor substrate 22 and the semiconductor chip 21 can be
easily connected with each other, unlike the conventional art,
without requiring a high temperature, a high pressure, and so
on.
[0088] Then, as shown in FIG. 9C, semiconductor chips 23 are cut,
on a chip by chip bases, from the semiconductor substrate 22 with
which the semiconductor chips 21 are connected, and undergo steps
such as the wire bonding method (connection using wires 25) and so
on. Then, the semiconductor chip 23 is mounted on a substrate 24,
thereby completing a semiconductor device.
[0089] As described above, according to this embodiment, in place
of the CMP, it becomes possible to planarize the surfaces of the
fine bumps 3 formed on the semiconductor substrate 1 at a low cost
and a high speed without causing inconvenience such as dishing or
the like, and to establish the connection of the bumps 3 easily and
securely. This enables the connection between the bumps 3, without
requiring conditions such as a high temperature, a high pressure,
and so on, so that reliable semiconductor devices can be
manufactured with high yields.
Second Embodiment
[0090] Next, a second embodiment will be described. Although Au is
illustrated as an example of the bump material in the first
embodiment, the case of using nickel (Ni) is illustrates in this
embodiment.
[0091] FIG. 10A to FIG. 10F are schematic cross-sectional views
showing a method for forming bumps according to this embodiment in
the order of steps.
[0092] First, through steps similar to those in FIGS. 1A and 1B of
the first embodiment, a rear face of a semiconductor substrate 1 is
cut so that the TTV is controlled to be a predetermined value or
less, specifically, 1 .mu.m or less.
[0093] This semiconductor substrate 1 is used, and an electrode 31
made of an aluminum-based metal is pattern-formed on the front face
of the semiconductor substrate 1, and then a nickel-phosphorous
plating film 32 is formed in a thickness of about 5 .mu.m to about
10 .mu.m on the electrode 31 by an electroless plating method as
shown in FIG. 10A.
[0094] The nickel-phosphorous plating film 32 is formed by a
general electroless plating method using nickel-phosphor,
nickel-phosphor-boron, nickel-boron, or the like. For example, a
nickel-phosphor alloy is formed in a bath of hypophosphite (sodium
hypophosphite or potassium hypophosphite), a nickel-boron alloy is
formed in a bath of sodium borohydride or in a weakly acidic bath
or a neutral bath using dimethylaminoborane, and a
nickel-phosphor-boron alloy is formed in a neutral bath.
[0095] Here in the nickel-phosphor-based electroless plating, a
phosphor concentrated layer 33 being a mechanically vulnerable
layer is formed in the surface layer of the nickel-phosphorous
plating layer 32 even if any of the above-described alloys is
selected. After the formation of a solder bump, this phosphor
concentrated layer causes a decrease in strength of an interface
between the plating and the solder bump. The thickness of the
phosphor concentrated layer is about 20 nm to about 40 nm, and
increases with an increase in phosphor content in the plating
bath.
[0096] Further, the phosphor concentrated layer is created
independent of the material of a base (a glass substrate, an iron
substrate, or an aluminum substrate) and of the thickness of the
plating. In addition, the phosphor concentrated layer is
necessarily formed in the surface layer even through the
nickel-based electroless plating is subjected to annealing
processing at a solder melting point or higher as described in, for
example, Patent Document 6. Unless the phosphor concentrated layer
is removed, it is difficult to form reliable plating coating and
solder bump.
[0097] An approach to these problems is a method of forming a
copper-nickel-silver-based compound layer by adding copper to a
solder material and using its barrier effect to restrain the
formation of the phosphor concentrated layer. However, there is a
problem of formation of the phosphor concentrated layer when the
thickness of the Au plating is 500 nm more, which leads to
restriction on the Au plating thickness and narrower selectivity of
the solder material.
[0098] Hence, in this embodiment, during the planarization by the
cutting of the nickel-phosphorous plating film 32, the phosphor
concentrated layer 33 is removed concurrently.
[0099] Specifically, first, as shown in FIG. 10B, a liquid resist
is applied as a protective film 34 to cover the front face of the
substrate to form a shock absorbing layer against a physical shock
caused by the later-described cutting. The protective film 34 is
formed by applying the resist in a thickness of about 10 .mu.m to
about 15 .mu.m by spin coating or the like and curing it.
[0100] Thereafter, similarly to FIG. 2A, the rear face is sucked,
for example, by vacuum suction to the supporting face of the
substrate supporting table, whereby the semiconductor substrate 1
is secured to the substrate supporting table. In this event, the
thickness of the semiconductor substrate 1 is fixed by the
planarization in FIG. 1B on the rear face 1b, and further the rear
face 1b is forcibly brought into a state free from undulation and
the like because of the suction to the supporting face 11a, whereby
the rear face 1b becomes a reference face for the planarization of
the front face 1a. In this state, as shown in FIG. 10C, machining,
that is, cutting using a tool made of diamond or the like here, is
performed for the surface layers of each nickel-phosphorous plating
film 32 and the protective film 34 on the front face 1a to remove
the phosphor concentrated layer 33 of the nickel-phosphorous
plating film 32 and to perform planarization so that the surfaces
of the nickel-phosphorous plating film 32 and the protective film
34 become continuously flat. The amount of cutting is set to about
1 .mu.m to about 2 .mu.m with which the phosphor concentrated layer
33 can be surely removed.
[0101] Subsequently, as shown in FIG. 10D, a gold plating film 35
is formed on the nickel-phosphorous plating film 32 as required by
the electroless plating method. The thickness of the gold plating
film 35 preferably ranges from about 30 nm to about 50 nm.
[0102] Subsequently, as shown in FIG. 10E, the protective film 34
is removed by ashing or the like. In this event, on the front face
1a of the semiconductor substrate 1, bumps 36 are formed which have
a uniform thickness and top surfaces uniformly planarized by the
cutting and in which the gold plating films 35 are formed.
[0103] Then, as show in FIG. 10F, a solder bump 37 is formed on the
bump 36 when necessary. This solder bump 37 is formed by the screen
printing, solder ball method, melting, or the like. It is
preferable to use, as the material of the solder, a
tin-silver-based, or tin-zinc-based solder or the like which
contains no lead.
[0104] Then, the semiconductor substrate 1 is divided by full-cut
dicing, thereby cutting out semiconductor chips to complete
semiconductor devices as in the first embodiment.
[0105] As described above, according to this embodiment, in place
of the CMP, it becomes possible to planarize the surfaces of the
nickel bumps 36 formed on the semiconductor substrate 1 at a low
cost and a high speed without causing inconvenience such as dishing
or the like. This enables the connection between the bumps 36,
without requiring conditions such as a high temperature, a high
pressure, and so on, so that reliable semiconductor devices can be
manufactured with high yields. In addition, the phosphor
concentrated layer 34 which degrades the reliability in a joint
between the bump 36 and the solder bump 37 can be completely
removed at a low cost, thus allowing the solder bump 37 to be
surely formed on the bump 36 having the planarized top surface.
Third Embodiment
[0106] Next, a third embodiment will be described. Although the
case in which a number of semiconductor chips are joined to the
semiconductor substrate is illustrated in the first embodiment,
this embodiment discloses the case in which the above-described
planarization is performed on the semiconductor chips and the
semiconductor chips are joined together.
[0107] FIG. 11A and FIG. 11B are schematic cross-sectional views
showing a method for manufacturing a semiconductor device according
to this embodiment in the order of steps.
[0108] First, as shown in FIG. 11A, an individual semiconductor
chip 41 is cut out, without performance of the rear face cutting in
the first embodiment, from a semiconductor substrate on which LSI
elements and the like are mounted and a plurality of bumps
different in height (still having variations in height), Au bumps
42 here, are formed.
[0109] Subsequently, machining, that is, cutting using a tool made
of diamond or the like here, is performed on the surface layer of
the semiconductor chip 41 to thereby perform planarization so that
the surfaces of the Au bumps 42 become continuously flat. This
makes the Au bumps 42 uniform in height and planarizes their tops
surfaces into mirror surfaces.
[0110] Subsequently, as shown in FIG. 11B, a pair of semiconductor
chips 41 are arranged to oppose each other and electrically
connected via the planarized top surfaces of the Au bumps 42.
Specifically, the pair of semiconductor chips 41 are placed to
oppose each other at the top surfaces and connected with each other
by pressure-bonding at room temperatures to 350.degree. C., about
170.degree. C. here. Since both of the top surfaces are planarized
with high accuracy, the pair of semiconductor chips 41 can be
easily connected, unlike the conventional art, without requiring a
high temperature, a high pressure, and so on.
[0111] As described above, according to this embodiment, in place
of the CMP, it becomes possible to planarize the surfaces of the
fine Au bumps 42 formed on the semiconductor chip 41 at a low cost
and a high speed without causing inconvenience such as dishing or
the like, and to establish the connection between the Au bumps 42
in the pair of semiconductor chips 41 easily and securely. This
enables the connection between the Au bumps 42, without requiring
conditions such as a high temperature, a high pressure, and so on,
so that reliable semiconductor devices can be manufactured with
high yields. In addition, the performance of the above-described
cutting after the cutting out of the individual semiconductor chip
41 from the semiconductor substrate can omit the step of
controlling the TTV, thereby contributing to a reduction in the
number of steps.
[0112] Modification 1
[0113] Here Modification 1 of this embodiment is described.
[0114] FIG. 12A to FIG. 12C are schematic cross-sectional views
showing a method for manufacturing a semiconductor device according
to Modification 1 in the order of steps.
[0115] First, as shown in FIG. 12A, an individual semiconductor
chip 41 is cut out, without performance of the rear face cutting in
the first embodiment, from a semiconductor substrate on which LSI
elements and the like are mounted and a plurality of bumps
different in height (still having variations in height), Au bumps
42 here, are formed.
[0116] Subsequently, a resin layer 43 made of an insulating
material is formed on the front face of the semiconductor chip 41
to bury the Au bumps 42. Note that the individual semiconductor
chip 41 may be cut out after the resin layer 43 is formed to bury
the Au bumps 42 in the state of the semiconductor substrate.
[0117] Subsequently, as shown in FIG. 12B, machining, that is,
cutting using a tool made of diamond or the like here as in the
first embodiment, is performed for the surface layer of the
semiconductor chip 41 to thereby perform planarization so that the
surfaces of the Au bumps 42 and the surface of the resin layer 43
become continuously flat. This makes the Au bumps 42 uniform in
height and planarizes their top surfaces into mirror surfaces.
[0118] Subsequently, a pair of semiconductor chips 41 are arranged
to oppose each other and electrically connected via the planarized
top surfaces of the Au bumps 42 and the resin layers 43.
Specifically, the pair of semiconductor chips 41 are placed to
oppose each other at the top surfaces and connected with each other
by pressure-bonding at room temperatures to 350.degree. C., about
170.degree. C. here. Since both of the top surfaces are planarized
with high accuracy, the pair of semiconductor chips 41 can be
easily connected, unlike the conventional art, without requiring a
high temperature, a high pressure, and so on. Further, the resin
layers 43 ensure joining of the pair of semiconductor chips 41 and
contribute as an underfill which protects the electrodes 42 and so
on.
[0119] As described above, according to this Modification 1, in
place of the CMP, it becomes possible to planarize the surfaces of
the fine Au bumps 42 formed on the semiconductor chip 41 at a low
cost and a high speed without causing inconvenience such as dishing
or the like, and to establish the connection between the Au bumps
42 in the pair of semiconductor chips 41 easily and securely. This
enables the connection between the Au bumps 42, without requiring
conditions such as a high temperature, a high pressure, and so on,
so that reliable semiconductor devices can be manufactured with
high yields. In addition, the performance of the above-described
cutting after the cutting out of the individual semiconductor chip
41 from the semiconductor substrate can omit the step of
controlling the TTV, thereby contributing to a reduction in the
number of steps.
[0120] Modification 2
[0121] Next, Modification 2 of this embodiment is described.
[0122] FIG. 13A to FIG. 13C are schematic cross-sectional views
showing a method for manufacturing a semiconductor device according
to Modification 2 in the order of steps.
[0123] First, as shown in FIG. 13A, an individual semiconductor
chip 41 is cut out, without performance of the rear face cutting in
the first embodiment, from a semiconductor substrate on which LSI
elements and the like are mounted and a plurality of bumps
different in height (still having variations in height), Au bumps
42 here, are formed.
[0124] Subsequently, machining, that is, cutting using a tool made
of diamond or the like here as in the first embodiment, is
performed for the surface layer of the semiconductor chip 41 to
thereby perform planarization so that the surfaces of the Au bumps
42 become continuously flat. This makes the Au bumps 42 uniform in
height and planarizes their top surfaces into mirror surfaces.
[0125] Subsequently, as shown in FIG. 13B, two semiconductor chips
41 which have been subjected to the planarization are made into a
pair of semiconductor chips 41, and a resin layer 44 containing
conductive fine particles 45 in an insulating resin is formed on
the front face of one of the semiconductor chips 41 in a thickness
to completely bury the Au bumps 42.
[0126] Subsequently, the pair of semiconductor chips 41 are
arranged to oppose each other and electrically connected via the
planarized top surfaces of the Au bumps 42. Specifically, the pair
of semiconductor chips 41 are placed to oppose each other at the
top surfaces and connected with each other by pressure-bonding at
room temperatures to 350.degree. C., about 170.degree. C. here.
Here the opposing Au bumps 42 are brought into contact with each
other through the conductive fine particles 45 due to the
thermocompression-bonding to be electrically connected. Since both
of the top surfaces are planarized with high accuracy, the pair of
semiconductor chips 41 can be easily connected unlike the
conventional art, without requiring a high temperature, a high
pressure, and so on. Further, the resin of the resin layer 44
ensures the adhesiveness and electrical connection between the pair
of semiconductor chips 41 and contributes as an underfill which
protects the electrodes 42 so on.
[0127] As described above, according to this Modification 2, in
place of the CMP, it becomes possible to planarize the surfaces of
the fine Au bumps 42 formed on the semiconductor chip 41 at a low
cost and a high speed without causing inconvenience such as dishing
or the like, and to establish the connection between the Au bumps
42 in the pair of semiconductor chips 41 easily and securely. This
enables the connection between the Au bumps 42, without requiring
conditions such as a high temperature, a high pressure, and so on,
so that reliable semiconductor devices can be manufactured with
high yields. In addition, the performance of the above-described
cutting after the cutting out of the individual semiconductor chip
41 from the semiconductor substrate can omit the step of
controlling the TTV, thereby contributing to a reduction in the
number of steps.
Fourth Embodiment
[0128] Next, a fourth embodiment will be described. Although the
case in which the bumps for external connection are formed on the
semiconductor substrate is illustrated in the first embodiment,
this embodiment discloses the case in which stud bumps are formed
using the wire bonding method.
[0129] FIG. 14A to FIG. 14F are schematic cross-sectional views
showing a method for manufacturing a semiconductor device according
to this embodiment in the order of steps.
[0130] First, as shown in FIG. 14A and FIG. 14B, a rear face of a
semiconductor substrate 51 on which LSI elements, electrode pads,
and so on are formed within element formation regions as in FIG. 1A
is cut so that the thickness of the semiconductor substrate 51 is
controlled to become fixed, specifically the TTV (the difference
between a maximum thickness and a minimum thickness of the
substrate) being 1 .mu.m or less.
[0131] Here, in the above-described cutting step, it is also
suitable to form a metal film, for example, an Al film on the
semiconductor substrate 51 by the sputtering method or the like
after the cutting of the rear face of the semiconductor substrate
51, and patterning the Al film to thereby form electrode pads 52 at
regions which will be electrical connecting points.
[0132] Subsequently, as shown in FIG. 14C, the wire bonding method
using Au as metal is used to form Au projections 53 on the
electrode pads 52 by pressure-bonding onto the electrode pads 52 a
mass in a ball shape of a Au bonding wire having a diameter of, for
example, 20 .mu.m formed by melting its tip and then tearing off
(precutting) the wire. In this event, the height of each Au
projection 53 from the electrode pad 52 is defined to be double or
more the diameter of the bonding wire, about 60 .mu.m here. In this
case, the Au projections 53 actually vary in height, and they only
need to range from about 50 .mu.m to about 60 .mu.m.
[0133] Subsequently, as shown in FIG. 14D, cutting is performed
using a tool 10 made of diamond or the like, thereby performing
planarization so that the top surfaces of the Au projections 53
become continuously flat to thereby form stud bumps 54. Here the
cutting position is set at a height of, for example, about 50 .mu.m
from the electrode pad 52. Under the cutting conditions set such
that the cutting speed is 10 m/s and the advance per cutting is 20
.mu.m, the tool 10 is driven from the initial cutting position by 2
.mu.m. This planarizes the top surfaces of the Au projections 53
into mirror surfaces as shown in FIG. 14E, thus forming the stud
bumps 54.
[0134] This planarization method by the cutting costs low relative
to the CMP because no slurry or the like is required and the tool
being a cutting tool, even though having worn, can be applied to
repeated use by grinding it. Since the semiconductor substrate
chucked on the chuck table is rotated at a high speed, and the tool
is moved on the semiconductor substrate at a predetermined speed to
cut an arbitrary cutting amount at a time, the cutting can be
finished in one to two minutes per semiconductor substrate, thus
realizing a method with a very high throughput. In the cutting
through use of the tool, it is possible to perform flattening on
the projections or the like of the stud bumps using the Au bonding
wire without tilt or breakage even when the projections are cut at
tip portions, by appropriately setting the cutting conditions.
However, since the projection may tilt during the cutting at a
hardness of 30 Hv or lower, the hardness of the wire is preferably
30 Hv or higher.
[0135] In this embodiment, the point of time when the diameters of
the cut faces of all of the stud bumps become equal to or larger
than the wire diameter is regarded as the end point of the cutting.
Generally, the stud bumps after the precut greatly vary in height,
and therefore it is difficult to verify the point of time when the
diameters of the cut faces of all of the stud bumps become equal to
or larger than the wire diameter. The suitable cutting method is
one driving the tool by 1 .mu.m to 3 .mu.m from a point where it
comes in contact with the highest bump to thereby expose all of cut
faces by the tool, but it is inefficient to verify every time the
cut face in a camera image or the like.
[0136] Hence, this embodiment employs, as an end point detecting
method, a method of sweeping a laser beam across the top surfaces
of the stud bumps 54 after the cutting through use of a detecting
apparatus including a laser emitter 61 and a detector 62, and
detecting the laser reflected off the top surfaces by the detector
62, as shown in FIG. 15A.
[0137] Then, the processing is repeated until after the detected
laser intensity reaches a predetermined level at all of the Au
projections 53 as shown in FIG. 15B. Preferably, this detecting
apparatus is placed at a rear in the traveling direction of the
cutting tool and travels in synchronism with the cutting tool. The
top surfaces (cut faces) of the stud bumps 54 are formed into
substantially mirror surfaces and thus totally reflect the laser
light and the like. In the case in which the detecting apparatus is
in synchronism with the cutting tool, all of the reflected light is
not always detected, in the strict sense, because there occurs a
delay in proportion to the traveling speed of the cutting tool, but
substantially all of them may be assumed to be detected because the
cutting speed is over 10 m/s at the highest.
[0138] In this embodiment, the detecting apparatus is driven while
the laser emitter 61 and the detector 62, which move in synchronism
with the travel of the tool and behind the tool, are measuring the
intensity of the laser light reflected off the planarized top
surfaces of the Au projections 53, so that when it detects that the
top surfaces of all of the Au projections 53 are exposed at a
height of, for example, 46 .mu.m, the cutting is finished.
[0139] Here if the cutting is insufficient, or if the diameter of
the cut face is equal to or less than the wire diameter as shown in
FIG. 15C, the laser light impinging on a point other than the cut
face reflects diffusely and is thus not detected by the detector.
Therefore, as shown in FIG. 15D, the detected laser light intensity
is weaker than that from the face which has been cut to have the
same diameter as that of the bonding wire. If such a stud bump is
found even at one point, the cutting tool is automatically driven
to cut the bumps by about 1 .mu.m to about 2 .mu.m until after the
laser intensity of a certain amount or more is finally detected at
all of the bumps. This can prevent poor connection due to uncutting
or insufficient cutting as well as substantially reduce the
processing time.
[0140] Then, as shown in FIG. 14F, each semiconductor chip 55 is
cut out from the semiconductor substrate 51, and the semiconductor
chip 55 is connected to a circuit board 56, for example, by the
flip-chip method. Specifically, the stud bumps 54 with the
planarized top surfaces on the semiconductor chip 55 and electrodes
57 formed on the front face of the circuit board 56 are arranged to
oppose each other and brought into contact, and joined by pressure
and heating. Note that, in this case, it is also preferable to
planarize the electrodes 57 on the circuit board 56 by the
above-described cutting similarly to the stud bumps 54 and then
flip-chip connect them.
[0141] As described above, according to this embodiment, in place
of the CMP, it becomes possible to planarize the surfaces of the
fine stud bumps 54 formed on the semiconductor substrate 51 at a
low cost and a high speed without causing inconvenience such as
dishing or the like, and to establish the connection between the
stud bumps 54 easily and securely. This enables the connection
between the bumps without requiring conditions such as a high
temperature, a high pressure, and so on, so that reliable
semiconductor devices can be manufactured with high yields. In
addition, the height of the stud bumps 54 after the cutting
planarization can be made 1.5 times or more that when the wire
diameter is not defined, thereby making it possible to mitigate the
stress on the semiconductor device, resulting in increased device
life. Furthermore, since the flat face created in the cutting has a
diameter equal to or larger than the wire diameter, a joining
strength of twice or more that in the conventional art can be
obtained even with the same wire diameter. Further, if only the
joining strength at the same level as that in the conventional art
is required, the wire diameter can be decreased, so that the bump
pitch can be decreased as well as the cost associated with the
bonding wire can be reduced.
Fifth Embodiment
[0142] Next, a fifth embodiment will be described. Here a
semiconductor device by a so-called TAB bonding method is
exemplified.
[0143] FIG. 16 and FIG. 17 are schematic cross-sectional views
showing a method for manufacturing a semiconductor device according
to this embodiment.
[0144] To manufacture this semiconductor device, first, through the
various steps shown in FIGS. 1A to 1D and FIGS. 2A and 2B as in the
first embodiment, bumps 3, which have a uniform height and
uniformly planarized top surfaces 3a created by cutting Au
projections 2, are formed via base metal films 72 on electrodes 71
of a semiconductor substrate 1 on which LSI semiconductor elements
and so on are formed within element formation regions. Here an
insulating protective film 73 is formed around the bumps 3 on the
semiconductor substrate 1.
[0145] Subsequently, a probe is brought into contact with the top
surface of the bump 3 to thereby inspect electrical characteristics
of the semiconductor element and the like on the semiconductor
substrate 1. Here the probe is brought into contact with
depressions and projections on the bump or a plating end face where
contamination exists to fail to obtain a stable contact in the
inspection in the conventional art, leading to a trouble in which
the tip of the probe is caught in the depressions and projections
to break. In contrast, in this embodiment, the probe is brought
into contact with the surface of the bump 3 which has been
planarized by the above-described cutting to a high level and
cleaned, so that the inspection can be conducted in a very stable
state.
[0146] Subsequently, an individual semiconductor chip 21 is cut out
from the semiconductor substrate 1, and then connection of the
semiconductor chip 21 is established by the TAB bonding method as
shown in FIG. 16.
[0147] Specifically, TAB leads 74 are prepared each of which is
made of a copper foil 75 on which a Au film 76 is formed by surface
treatment with Au and has a portion located at one end
corresponding to the connecting region and a resin layer 77
provided at the other end. The semiconductor chip 21 is then
securely mounted on a bonding stage 80, and the Au films 76 of the
TAB leads 74 within the connecting regions are brought into contact
with the planarized and cleaned top surfaces of the bumps 3 on the
semiconductor chip 21, and a pressure is applied while a heater 78
is heating them to thereby join them. Here the heating temperature
may be relatively low, such as about 200.degree. C., and the
bonding load can also be reduced to about 20 g that is about 2/3
that in the conventional art. As a result, it becomes possible to
connect the TAB leads with a fine pitch of 40 .mu.m or less without
positional displacement.
[0148] Thereafter, as shown in FIG. 17, the semiconductor chip 21
is detached from the bonding stage 80, and a sealing resin 79 is
formed to cover the front face of the semi-conductor chip 21
including the connecting regions between the bumps 3 and the TAB
leads 74, thereby completing a semiconductor device.
[0149] Note that although the case in which the plated bumps are
formed as bumps is illustrated in this embodiment, the stud bumps
by the wire bonding method may be formed.
[0150] As described above, according to this embodiment, in place
of the CMP, it becomes possible to planarize the surfaces of the
fine bumps 3 formed on the semiconductor substrate 1 at a low cost
and a high speed without causing inconvenience such as dishing or
the like, and to establish the connection of the bumps 3 easily and
securely. This enables secure connection between the bump and a
lead terminal without requiring conditions such as a high
temperature, a high pressure, and so on, so that reliable TAB
bonding-type semiconductor devices can be manufactured with high
yields.
Sixth Embodiment
[0151] Next, a sixth embodiment will be described. Here an
apparatus configuration is disclosed for performing the
above-described cutting step and joining step on a pair of bases (a
semiconductor chip and a circuit board by the flip-chip method is
exemplified here) in performing the above-described various
embodiments.
[0152] FIG. 18 is a schematic diagram showing a semiconductor
manufacturing apparatus according to this embodiment.
[0153] This semiconductor manufacturing apparatus comprises a chip
introduction section 81 for introducing a semiconductor chip with
bumps formed on its front face; a circuit board introduction
section 82 for introducing a circuit board with electrodes formed
on its front face; a cutting section 83 performing a step of
planarizing the surfaces of the bumps on the semiconductor chip by
the above-described cutting using a tool; a joining section 84
performing a step of joining the semiconductor chip and the circuit
board via the planarized bumps and the electrodes; and a carry-out
section 85 for carrying out a joined and integrated semiconductor
device, and further has a cleaning holding section 86 including the
cutting section 83 and the joining section 84 in an inert
atmosphere. Here in the cutting section 83, not only the
semiconductor chip but also the surfaces of the electrodes on the
circuit board may be similarly planarized by the cutting.
[0154] The cleaning holding section 86 has a function of holding a
cleaning atmosphere, specifically, an inert atmosphere, for
example, a gas phase not containing Ar, N.sub.2, or the like, or an
atmosphere at 1 atm or less containing oxygen, in the planarizing
step and the joining step. This can relatively easily hold a
planarization state very close to an ideal state without addition
of a cleaning step using Ar plasma or the like immediately before
the joining step, realizing secure joining between the bumps and
the electrodes.
[0155] Note that the flip-chip mounting is illustrated in this
embodiment, but the present invention is not limited to this and
preferably used for joining a semiconductor chip and a
semiconductor wafer, semiconductor chips, or the like.
Industrial Applicability
[0156] According to the present invention, in place of the CMP, it
becomes possible to planarize the surfaces of the fine bumps formed
on the substrate at a low cost and a high speed, and to establish
the connection between the bumps easily and securely without
causing inconvenience such as dishing or the like.
* * * * *