U.S. patent application number 10/810718 was filed with the patent office on 2004-09-16 for electroplated copper interconnection structure, process for making and electroplating bath.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to Andricacos, Panayotis C., Boettcher, Steven H., Chung, Dean S., Deligianni, Hariklia, Fluegel, James E., Horkans, Wilma Jean, Kwietniak, Keith T., Locke, Peter S., Parks, Christopher C., Seo, Soon-Cheon, Simon, Andrew H., Walton, Erick G..
Application Number | 20040178077 10/810718 |
Document ID | / |
Family ID | 32962840 |
Filed Date | 2004-09-16 |
United States Patent
Application |
20040178077 |
Kind Code |
A1 |
Andricacos, Panayotis C. ;
et al. |
September 16, 2004 |
Electroplated copper interconnection structure, process for making
and electroplating bath
Abstract
Interconnect structures with copper conductors being at least
substantially free of internal seams or voids are obtained
employing an electroplating copper bath containing dissolved cupric
salt wherein the concentration of the salt is at least about 0.4
molar and up to about 0.5 molar concentration of an acid. Also
provided are copper damascene structures having an aspect ratio of
greater than about 3 and a width of less than about 0.275 .mu.m and
via openings filled with electroplated copper than is substantially
free of internal seams or voids.
Inventors: |
Andricacos, Panayotis C.;
(Croton-On-Hudson, NY) ; Boettcher, Steven H.;
(Fishkill, NY) ; Chung, Dean S.; (Essex Junction,
VT) ; Deligianni, Hariklia; (Edgewater, NJ) ;
Fluegel, James E.; (Rhinebeck, NY) ; Horkans, Wilma
Jean; (Ossining, NY) ; Kwietniak, Keith T.;
(Highlandfalls, NY) ; Locke, Peter S.; (Hopewell
Junction, NY) ; Parks, Christopher C.; (Poughkeepsie,
NY) ; Seo, Soon-Cheon; (White Plains, NY) ;
Simon, Andrew H.; (Fishkill, NY) ; Walton, Erick
G.; (Underhill, VT) |
Correspondence
Address: |
CONNOLLY BOVE LODGE & HUTZ LLP
SUITE 800
1990 M STREET NW
WASHINGTON
DC
20036-3425
US
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
32962840 |
Appl. No.: |
10/810718 |
Filed: |
March 29, 2004 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10810718 |
Mar 29, 2004 |
|
|
|
09684786 |
Oct 10, 2000 |
|
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Current U.S.
Class: |
205/123 ;
205/291 |
Current CPC
Class: |
C25D 5/024 20130101;
C25D 3/38 20130101; H01L 21/76877 20130101; H01L 21/2885 20130101;
C25D 5/18 20130101; C25D 7/123 20130101; C25D 5/617 20200801 |
Class at
Publication: |
205/123 ;
205/291 |
International
Class: |
C25D 005/02 |
Claims
What is claimed is:
1. A process for fabricating an interconnect structure on an
electronic device with copper conductor substantially free of
internal seams or voids which comprises: forming an insulating
material on a substrate; lithographically defining and forming
recesses for lines and/or vias in the insulating material in which
interconnection conductor material will be deposited; depositing a
barrier layer against copper diffusion; depositing a current
carrying copper seed layer; depositing the copper conductor by
electroplating from a bath containing a dissolved cupric salt
wherein the concentration of the cupric salt is at least about 0.4
molar and an acid and wherein the bath has an acidic pH.
2. The process of claim 1 wherein the concentration of the cupric
salt is at least about 0.8 molar.
3. The process of claim 1 wherein the cupric salt comprises
CuSO.sub.4.
4. The process of claim 1 wherein the concentration of the acid is
an amount up to about 0.5 molar.
5. The process of claim 1 wherein the concentration of the acid is
about 0.1 to about 0.25 molar.
6. The process of claim 4 wherein the acid is sulfuric acid.
7. The process of claim 1 wherein the electroplating bath has a pH
of up to about 5.
8. The process of claim 1 wherein the electroplating bath has a pH
of about 0.6.
9. The process of claim 1 wherein the electroplating bath contains
at least one auxiliary additive selected from the group consisting
of brightener, leveling agent, ductility enhancer and stress
reducer.
10. The process of claim 1 wherein the electroplating bath is free
of complexing agents.
11. The process of claim 1 wherein the substrate is coupled to a
plating power supply with the current enabled before introducing
the substrate into the bath.
12. The process of claim 11 wherein the initial current of the
power supply is lower than the current of the electroplating of
copper from the bath onto the substrate.
13. The process of claim 12 wherein the initial current is
maintained for up to about 40 seconds.
14. The process of claim 1 wherein the electroplating is carried
out at a current density of about 10 to about 50 mA/cm.sup.2.
15. The process of claim 13 wherein the initial current is about
1-5 mA/Cm.sup.2.
16. The process of claim 1 which further comprises depositing a
barrier layer on sidewalls and bottom surfaces of the lines or
vias, and depositing a metal seed layer prior to electroplating the
copper.
17. The process of claim 16 wherein the metal seed layer is
copper.
18. The method of claim 1 wherein the vias or lines have dimensions
of about 0.275 .mu.m or less and aspect ratios of at least about
3.
19. The method of claim 1 which further comprises planarizing or
chemical-mechanical polishing after the electroplating.
20. A copper damascene structure having an aspect ratio of greater
than about 3 and a width of less than about 0.275 .mu.m which
comprises: a substrate having a dielectric layer having a via
and/or line opening therein; the via and/or line opening having a
liner or barrier layer on sidewalls and bottom surfaces of the via
opening; a metal seed layer on the liner or barrier layer; and
wherein the via and/or line opening is filled with electroplated
copper that forms a continuous interface with the liner or barrier
layer and being substantially free of internal seams or voids.
21. An interconnect structure obtained by the process of claim
1.
22. An electroplating copper bath comprising dissolved cupric salt
at a concentration of at least about 0.4 molar, up to about 0.5
molar concentration of an acid and having an acidic pH.
23. The bath of claim 22 being free of complexing agent.
24. The bath of claim 23 wherein the cupric salt concentration is
at least about 0.8 molar.
Description
TECHNICAL FIELD
[0001] The present invention relates to interconnection wiring on
electronic devices such as on integrated circuit (IC) chips and
more particularly to substantially void-free and seamless submicron
structures fabricated by copper electroplating from novel plating
baths.
BACKGROUND OF INVENTION
[0002] AlCu and its related alloys are preferred alloys for forming
interconnections on electronic devices such as integrated circuit
chips. The amount of Cu in AlCu is typically in the range from 0.3
to 4 percent.
[0003] Replacement of AlCu by Cu and Cu alloys as chip
interconnection material results in advantages of performance.
Performance is improved because the resistivity of Cu and certain
copper alloys is less than the resistivity of AlCu; thus narrower
lines can be used and higher wiring densities will be realized.
[0004] The advantages of Cu metallization have been recognized by
the semiconductor industry. In fact, the semiconductor industry is
rapidly moving away from aluminum and is adopting copper as the
material of choice for chip interconnects because of its high
conductivity and improved reliability.
[0005] MAnufacturing of chip interconnects involves many process
steps that are interrelated. In particular, copper interconnects
are manufactured using electroplating in a process called "Dual
Damascene" in which a via and a line are fabricated together in a
single step. The electroplating process, typically, employs a
plating solution composed of cupric sulfate salt, sulfuric acid,
inorganic and organic additives that control the process such that
the rate of copper electrodeposition is differentially inhibited
along the sidewall of a small feature, resulting in preferential
deposition at the bottom wall of the feature. This phenomenon is
called superfilling.
[0006] A few of the important integration challenges that need to
be overcome to successfully fabricate Dual Damascene copper
interconnects are assuring the continuity of the barrier and seed
layer films and providing a copper electroplating process capable
of producing seamless and void-free deposits at the feature
sidewalls and bottom wall of the feature and along the center of
the wiring. Furthermore, the International Technology Roadmap for
Semiconductors, 1999 Edition, calls for smaller via diameters and
higher aspect ratios in future interconnect metallizations.
[0007] With the shrinking dimensions there is a continuing
challenge to fill these features with copper without a seam or
void. In Dual Damascene fabrication of features with linewidths of
0.25 .mu.m or smaller, typically a via and a line have to be filled
in one process step employing copper electroplating. The applied
current is carried through a thin seed copper layer. Often, the
seed layer is extremely thin, possibly discontinuous and oxidized
and thus it is not capable of carrying the electroplating current
reliably within small features of high aspect ratios. In sub-micron
vias, which are typically more difficult to fill than lines, the
rate of diffusion of the cupric ions dissolved in the plating
solution is too low to keep up with the rate of reduction of cupric
ions at the metal surface. As a result, the cupric ion
concentration within a via becomes much lower than the cupric ion
bulk concentration and the concentration overpotential becomes
large. The superfilling capability of the plating solution provided
by the organic additives cannot overcome the large concentration
overpotential caused by the depletion of the cupric ion. These
phenomena manifest themselves as voids along the sidewall of the
features, two types of defects, caused by missing copper seed
layer, and voids or seams along the feature centerline, caused by
the depletion of the cupric ion within the via.
[0008] Accordingly, there exists a need to provide a copper
electroplating process that can accomplish Dual Damascene plating
at small features without internal seams or voids.
SUMMARY OF INVENTION
[0009] The present invention relates to providing a highly reliable
copper interconnect structure suitable for wiring in integrated
circuit chips with at least substantially, if not entirely,
void-free seamless conductors.
[0010] In particular, an aspect of the present invention relates to
a process for fabricating an interconnect structure on an
electronic device with copper conductor substantially free of
internal seams or voids.
[0011] The process of the present invention comprises:
[0012] forming an insulating material on a substrate,
[0013] lithographically defining and etching recesses for lines
and/or vias in the insulating material in which interconnection
conductor material will be deposited,
[0014] depositing a barrier layer against copper diffusion onto the
insulating materials, and into the etched recesses, depositing a
copper seed layer for conducting electrical current during
electroplating, and
[0015] depositing the copper conductor by electroplating from an
electroplating bath.
[0016] The electroplating bath comprises a high copper
concentration wherein the concentration of the cupric salt is at
least about 0.4 molar and up to the saturation concentration of the
cupric salt in solution. In addition, the bath contains an acid and
can contain other common components of acid copper plating baths,
such as inorganic and organic addition agents.
[0017] The copper conductor is deposited by electroplating using an
electroplating process in the above electroplating bath wherein the
substrate to be plated is introduced into the plating bath with the
power supply enabled such that a plating current is imposed at the
instant of contact of the substrate with the plating bath. The
initially imposed plating current with the power supply engaged is
from 1 to 20 mA/cm.sup.2 and the time at this lower current density
is from 0 to 40 seconds, subsequently the power supply is switched
to a higher current density of 10 to about 50 mA/cm.sup.2. The
initial and final current densities may also be the same so that
the substrate is introduced into the plating bath with the same
imposed current as the copper plating current.
[0018] The present invention also relates to interconnect
structures obtained by the above disclosed process.
[0019] Another aspect of the present invention relates to a copper
electroplating bath that comprises a high concentration of a
dissolved cupric salt of at least about 0.4 molar and a low
sulfuric acid concentration of at most 0.5 molar and as low as 0.01
molar. In addition, the bath can contain other common components of
acid copper plating baths such as inorganic and organic addition
agents.
[0020] The present invention further relates to a copper damascene
structure having an aspect ratio of greater than 3 and a width or
diameter of less than 0.275 .mu.m which comprises:
[0021] a substrate having a dielectric layer having a via and line
opening therein;
[0022] the via and/or line opening having a barrier layer on
sidewalls and bottom surfaces of the via and/or line opening;
[0023] a metal seed layer on the barrier layer; and
[0024] wherein the via and/or line opening are filled with
electroplated copper forming a continuous interface with the liner
or barrier layer and being substantially free of internal seams or
voids.
[0025] Still other objects and advantages of the present invention
will become readily apparent by those skilled in the art from the
following detailed description, wherein are shown and described
preferred embodiments of the invention, simply by way of
illustration of the best mode contemplated of carrying out the
invention. As will be realized the invention is capable of other
and different embodiments, and its several details are capable of
modifications in various obvious respects, without departing from
the invention. Accordingly, the description is to be regarded as
illustrative in nature and not as restrictive.
BRIEF DESCRIPTION OF FIGURES
[0026] FIG. 1 is a SEM cross section of vias filled with
electroplated copper according to prior art method.
[0027] FIG. 2 is a SEM cross section of vias filled with
electroplated copper according to prior art method.
[0028] FIG. 3 is a SEM cross section of vias filled with
electroplated copper according to prior art.
[0029] FIGS. 4A and 4B are SEM cross sections of vias filled with
electroplated copper according to the present invention.
[0030] FIGS. 5A and 5B are SEM cross sections of vias filled with
electroplated copper according to the present invention.
[0031] FIG. 6 is a SEM cross section of vias filled with
electroplated copper according to the present invention.
BEST AND VARIOUS MODES FOR CARRYING OUT INVENTION
[0032] The present invention relates to a process for fabricating
an interconnect structure on an electronic device with copper
conductors that are substantially, if not entirely, free of
internal seams or voids. The fabrication process comprises forming
an insulating material such as silicon dioxide on a substrate (e.g.
a semiconductor wafer substrate).
[0033] Lines and/or vias openings are lithographically defined and
formed in the insulating material by well known techniques.
According to preferred aspects of the present invention, the lines
and/or vias have a width of less than about 0.275 .mu.m, and more
preferably about 0.2 .mu.m or less, including widths of about 0.1
.mu.m.
[0034] In addition, according to the present invention the lines
and/or vias have aspect ratios of greater than about 3.
[0035] According to the present invention, copper is deposited in
the lines and/or vias by electroplating from a bath containing a
dissolved cupric salt wherein the concentration of the cupric salt
is at least about 0.4 molar and preferably at least about 0.8
molar. The maximum amount is up to the solubility limit of the
salt. The preferred salt is CuSO.sub.4. The cupric ion may also be
added as sulfamate, hydroxide, carbonate, or other salt that is
compatible with the plating bath chemistry and the addition agents.
The concentration of the cupric salt is typically about two to four
times higher than the concentrations normally used in prior art
baths.
[0036] The electroplating bath of the present invention can include
up to about 0.5 molar of an inorganic acid. The electroplating bath
more typically contains an amount up to about 0.5 molar, and
preferably about 0.1 to about 0.25 molar concentration of an
inorganic acid. The preferred acid is H.sub.2SO.sub.4.
Alternatively sulfonic acid, methane sulfonic acid, hydrochloric
acid or other acids with comparable bath function can be added. The
concentration of the acid is typically at least about three to four
times lower than the concentration normally used in prior art
electroplating baths.
[0037] The electroplating bath typically has an acidic pH up to
about 5 and preferably about 0.6.
[0038] Employing electroplating baths according to the present
invention makes possible seamless void-free Dual Damascene copper
electrofill that is extendible to 0.10 micron dimensions. Also,
such baths provide a wide and robust process window.
[0039] The electroplating baths employed according to the present
invention preferably are free of complexing agents that are often
used in electroplating baths with low acid concentrations.
[0040] In addition, the plating baths of the present invention can
optionally contain auxiliary additives for achieving superfilling
and controlling such properties of the electroplated copper as
grain structure, ductility and internal stress. Typical additives
and their relative amounts are disclosed in PCT/US96/19592,
disclosure of which is incorporated herein by reference.
[0041] One suitable system of additives is marketed by Enthone-OMI,
Inc. and is known as the Sabre Copper MAke-up. The composition
includes two additives one referred to as Sabre B and the other
Sabre-L. Two other suitable systems of additives are marketed by
ShipleyRonal, Inc. One of them is known as the Copper Gleam 2001
system. The additives are referred to by the manufacturer as Copper
Gleam 2001 Leveller and Copper Gleam 2001 Carrier. The other system
of additives also marketed by ShipleyRonal Inc. is known as
Nanoplate 2001 system, which is a two-additive configuration. One
of the additives is referred to as C-2001 Suppressor Solution and
the other is referred to as B-2001 Additive Solution. Another
suitable system of additives is marketed by Atotech USA, Inc. and
is known as the Cupracid HS system. The additives in this system
are referred to by the manufacturer as Cupracid Brightener and
Cupracid HS Basic Leveller.
[0042] Examples of specific additives which may be added to a bath
in the instant invention are described in several patents. U.S.
Pat. No. 4,110,176 issued Aug. 29, 1978 to H-G Creutz, deceased, et
al., entitled "Electrodeposition of Copper" describes the use of
additives in a plating bath such as poly alkanol
quaternary-ammonium salt to give bright, highly ductile, low stress
and good leveling copper deposits from an aqueous acidic copper
plating bath, which patent is incorporated herein by reference.
[0043] U.S. Pat. No. 4,376,685 issued MArch 15, 1983 to A. Watson,
entitled "Acid Copper Electroplating Baths Containing Brightening
and Leveling Additives", describes additives to a plating bath such
as alkylated polyalkyleneimine to provide bright and leveled copper
electrodeposits from an aqueous acidic bath, which patent is
incorporated herein by reference.
[0044] U.S. Pat. No. 4,975,159 issued Dec. 4, 1990 to W. Dahms,
entitled "Aqueous Acidic Bath for Electrochemical Deposition of a
Shiny and Tear-Free Copper Coating and Method of Using Same",
describes adding to an aqueous acidic bath combinations of organic
additives including at least one substituted alkoxylated lactam as
an amide-group-containing compound in an amount to optimize the
brightness and ductility of the deposited copper, which patent is
incorporated herein by reference. In U.S. Pat. No. 4,975,159, Table
I lists a number of alkoxylated lactams which may be added to a
bath in the instant invention. Table II lists a number of
sulfur-containing compounds with water-solubilizing groups such as
3-mercaptopropane-1-sulfonic acid, which may be added to a bath in
the instant invention. Table II lists organic compounds such as
polyethylene glycol which may be added to a bath as surfactants in
the instant invention.
[0045] U.S. Pat. No. 3,770,598 issued Nov. 6, 1973 to H-G Creutz,
entitled "Electrodeposition of Copper from Acid Baths", describes
baths for obtaining ductile, lustrous copper containing therein
dissolved a brightening amount of the reaction product of
polyethylene imine and an alkylating agent to produce a quaternary
nitrogen, organic sulfides carrying at least one sulfonic group,
and a polyether compound such as polypropylene glycol, which patent
is incorporated herein by reference.
[0046] U.S. Pat. No. 3,328,273 issued Jun. 27, 1967 to H-G Creutz
et al., entitled "Electrodeposition of Copper from Acidic Baths",
describes copper sulfate and fluoborate baths for obtaining bright,
low-stress deposits with good leveling properties that contain
organic sulfide compounds of the formula
XR1-(Sn)-R.sub.2--SO.sub.3H, where R.sub.1 and R.sub.2 are the same
or different and are polymethylene groups or alkyne groups
containing 1-6 carbon atoms, X is hydrogen or a sulfonic group, and
n is an integer of 2-5 inclusive, which patent is incorporated
herein by reference. Additionally, these baths may contain
polyether compounds, organic sulfides with vicinal sulphur atoms,
and phenazine dyes. In U.S. Pat. No. 3,328,273, Table I lists a
number of polysulfide compounds which may be added to a bath in the
instant invention. Table II lists a number of polyethers which may
be added to a bath in the instant invention.
[0047] Additives may be added to the bath for accomplishing various
objectives. Additives may be included for inducing in the conductor
specific film microstructures including large grain size relative
to film thickness or randomly oriented grains.
[0048] In addition, prior to the electroplating, a liner or barrier
layer is provided on the sidewalls and bottom surfaces of the lines
and/or vias. Typical liner or barrier layers include Ti, Ta, W and
nitrides thereof. The total thickness of the liner or barrier
layer(s) is typically about 0.025 .mu.m to about 0.1 .mu.m.
[0049] Located on the surfaces of the liner or barrier layer is
typically a metal seed layer such as copper. The seed layer is
typically about 0.01 .mu.m to about 0.25 .mu.m thick.
[0050] The plating process is preferably carried out by introducing
the substrate (e.g. the wafer) into the plating bath with the
current on so that the thin and possibly oxidized seed layer is
cathodically protected. If the seed layer is oxidized it can be
reduced back to copper and repair itself during the hot immersion
process.
[0051] According to preferred processing of the present invention,
the current upon initial immersion of the wafer is lower than that
employed in the electroplating such as about 1-5 mA/cm.sup.2. The
initial current is typically maintained for up to about 40 seconds.
If the initial current density employed is lower than the desired
electroplating current density, the current density can be
increased at this time (after the initial period) to a current
density typical of the prior art processes such as between 10
mA/cm.sup.2 and 50 mA/cm.sup.2. The current can be maintained at
the electroplating current density until the desired thickness is
achieved.
[0052] The lower acid concentration in the bath tends to provide
for improved seed layer integrity because the lower acid strength
does not have as high tendency to attack or dissolve the copper or
oxidized copper seed layer. In addition, the lower acid
concentration makes it possible to dissolve the necessary increased
concentration of cupric salt in the bath.
[0053] The increased cupric ion concentration makes it possible to
avoid a large concentration overpotential in high aspect ratio
features. In the absence of a large concentration overpotential,
the additives can produce superfilling at the center-line of the
features and voids will not occur. The high cupric ion
concentration in the plating bath also expands the process window
of copper electrofill down to 0.1 micron dimensions because it
minimizes depletion of the cupric ion within the vias. In essence,
a high copper-low acid bath can fill very small width or diameter
and high aspect ratio Dual Damascene structures.
[0054] The plating is usually carried out at about normal room
temperature.
[0055] In a typical process, after the electroplating planarizing
or chemical-mechanical polishing of the resulting structure is
carried out to accomplish electrical isolation of individual lines
and/or vias.
[0056] The following non-limiting examples are presented to further
illustrate the present invention.
EXAMPLE 1
[0057] A wafer having 0.25 .mu.m vias with an aspect ratio of about
7 in a silicon dioxide insulating layer having a barrier layer
about 0.05 .mu.m thick and a copper seed layer about 0.15 .mu.m
thick is immersed in a plating bath containing 124 g/l
CuSO.sub.4.5H.sub.2O, 49 g/l H.sub.2SO.sub.4, about 2 mM HCl, and
about 10 ml/l of Sabre-B and about 1.8 ml/l of Sabre-L,
commercially available additives from Enthone OMI. A current
density of about 3.5 mA/cm.sup.2 is applied and the wafer is
immersed into the plating bath for about 10 seconds, after which
the current is switched to 15 mA/cm.sup.2 and the plating continues
for about 180 seconds. The wafer is rotated at about 120 rpm.
[0058] FIGS. 4A and 4B show SEM cross sections achieved by this
example. As shown therein, filling of vias was excellent except for
one via where a void in the center of the via appeared.
EXAMPLE 2
[0059] A wafer having 0.25 .mu.m vias with an aspect ratio of about
7 in a silicon dioxide insulating layer having a barrier layer
about 0.05 .mu.m thick and a copper seed layer about 0.15 .mu.m
thick is immersed in a plating bath containing about 248 g/l
CuSO.sub.4.5H.sub.2O, about 24 g/l H.sub.2SO.sub.4, about 2 mM HCl,
and about 10 ml/l of Sabre-B and about 1.8 ml/l of Sabre-30 L,
commercially available additives from Enthone OMI. Upon immersing
the wafer into the bath, the current is switched on to 15
mA/cm.sup.2 and plating continues for about 180 seconds. The wafer
is rotated at about 120 rpm.
[0060] FIGS. 5A and 5B show SEM cross sections achieved by this
example. As shown therein, filling of vias was excellent.
EXAMPLE 3
[0061] A wafer having 0.25 .mu.m vias with an aspect ratio of about
7 in a silicon dioxide insulating layer having a barrier layer
about 0.05 .mu.m thick and a copper seed layer about 0.15 .mu.m
thick is immersed in a plating bath containing about 248 g/l
CuSO.sub.4.5H.sub.2O, about 24 g/l H.sub.2SO.sub.4, about 2 mM HCl,
and about 10 ml/l of Sabre-B and about 1.8 ml/l of Sabre-L,
commercially available additives from Enthone OMI. A current
density of about 3.5 mA/cm.sup.2 is applied and the wafer is
immersed into the plating for about 10 seconds, after which the
current is switched to 15 mA/cm.sup.2 and the plating continues for
about 180 seconds. The wafer is rotated at about 120 rpm.
[0062] FIG. 6 shows a SEM cross section achieved by this example.
As shown therein, filling of vias was excellent.
[0063] The process of turning the current on before closing the
electrical circuit between cathode and anode, prevents the seed
layer from dissolving in the acidic plating bath and reduces any
oxidized copper formed back to elemental copper. The current
density applied can be either the same as the electroplating
current density or lower by as much as 15 times. A lower current
density than the electroplating current density can be used for
cathodic protection of the seed layer and to repair an oxidized
seed layer.
[0064] The initial current is typically up to about 40 seconds
employing a current density of about 1 to about 5 mA/cm.sup.2.
COMPARISON EXAMPLE A
[0065] A wafer having 0.25 .mu.m diameter vias with an aspect ratio
of 4.8 is immersed in a plating bath containing 159 g/l sulfuric
acid and 60 g/l copper sulfate pentahydrate and the same
commercially available additives used in Example 3. The wafer is
rotated at 60 rpm and the current is off for 3 seconds while the
wafer is in contact with the electroplating solution. A current
density of 15 mA/cm.sup.2 is applied for 180 seconds to
electroplate copper.
[0066] FIG. 1 shows SEM cross section of vias filled according to
this example. There are two kinds of voids observed: voids along
the via sidewall and voids along the via centerline. The sidewall
voids occur because the copper seed layer at this point on the
sidewall was initially thin and was oxidized, the oxide layer then
dissolving in the electroplating solution during the 3 second-dwell
time. Oxidation of the copper seed layer can occur upon exposure to
atmospheric oxygen or moisture.
[0067] The other kind of void observed in FIG. 1 is a void along
the centerline of the copper deposit. Such voids are attributed to
mass transport limitations of the cupric ion within the via and to
the resulting large concentration overpotential. Typically
additives in the plating solution yield a surface overpotential
higher than the cupric ion concentration overpotential, but in high
aspect ratio vias or high aspect ratio Dual Damascene structures
the cupric ion may be depleted from its bulk value by as much as
85% and the concentration overpotential may become higher than the
surface overpotential that produces superfilling.
COMPARISON EXAMPLE B
[0068] A wafer having 0.25 .mu.m diameter vias with an aspect ratio
of 7 is immersed in a plating bath containing 159 g/l sulfuric acid
and 60 g/l copper sulfate pentahydrate and the same commercially
available additives used in Example 3. The wafer is rotated at 120
rpm and the current is off for 3 seconds while the wafer is in
contact with the electroplating solution. A current density of 15
mA/cm.sup.2 is applied for 180 seconds to electroplate copper.
[0069] FIG. 2 shows SEM cross sections of vias filled according to
this example. The same kinds of voids as present in Comparison
Example A are evident in FIG. 2 as well.
COMPARISON EXAMPLE C
[0070] A wafer having 0.25 .mu.m vias with an aspect ratio of about
7 in a silicon dioxide insulating layer having a barrier layer of
about 0.05 .mu.m thick and a copper seed layer about 0.15 .mu.m
thick is immersed in a plating bath containing about 60 .mu.l
CuSO.sub.4.5H.sub.2O, about 160 g/l H.sub.2SO.sub.4 and the same
commercially available additives and amounts used in examples 3-5.
A current density of about 3.5 mA/cm.sup.2 is applied and the wafer
is immersed into the plating bath for about 10 seconds, after which
the current is switched to 15 mA/cm.sup.2 and the plating continues
for about 180 seconds. The wafer is rotated at about 120 rpm.
[0071] FIGS. 3A and 3B show SEM cross sections achieved by this
example. As shown therein, large voids occurred in at least one via
and smaller voids in other vias.
[0072] Furthermore, the copper deposited in the present invention
has properties equivalent to copper deposited from prior art baths.
The data in Table 1 below confirm that the resistivity of the
copper metal deposited from baths with high cupric sulfate
concentration and low sulfuric acid concentration is equivalent to
the resistivity of copper deposited from prior art baths.
1TABLE 1 Final Resistivity of Plated Films 60/160 126/47.6 223/46
223/26.6 (.mu..OMEGA. .multidot. CuSO.sub.4.5H.sub.2O/
CuSO.sub.4.5H.sub.2O/ CuSO.sub.4.5H.sub.2O/ CuSO.sub.4.5H.sub.2O/
cm) H.sub.2SO.sub.4 (g/l) H.sub.2SO.sub.4 (g/l) H.sub.2SO.sub.4
(g/l) H.sub.2SO.sub.4 (g/l) .rho. 1.79 1.82 1.81 1.88
[0073] Additionally, there is no dependence of plating efficiency
on cupric ion and acid concentrations.
[0074] The foregoing description of the invention illustrates and
describes the present invention. Additionally, the disclosure shows
and describes only the preferred embodiments of the invention but,
as mentioned above, it is to be understood that the invention is
capable of use in various other combinations, modifications, and
environments and is capable of changes or modifications within the
scope of the inventive concept as expressed herein, commensurate
with the above teachings and/or the skill or knowledge of the
relevant art. The embodiments described hereinabove are further
intended to explain best modes known of practicing the invention
and to enable others skilled in the art to utilize the invention in
such, or other, embodiments and with the various modifications
required by the particular applications or uses of the invention.
Accordingly, the description is not intended to limit the invention
to the form disclosed herein. Also, it is intended that the
appended claims be construed to include alternative
embodiments.
* * * * *