U.S. patent application number 09/105775 was filed with the patent office on 2002-01-10 for method for reducing stress-induced voids for 0.25u and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby.
Invention is credited to BESSER, PAUL R., BUYNOSKI, MATTHEW, CAFFALL, JOHN, HUANG, RICHARD J., MACCRAE, NICK, NGO, MINH VAN, TRAN, KHANH.
Application Number | 20020003306 09/105775 |
Document ID | / |
Family ID | 22307709 |
Filed Date | 2002-01-10 |
United States Patent
Application |
20020003306 |
Kind Code |
A1 |
NGO, MINH VAN ; et
al. |
January 10, 2002 |
METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25U AND SMALLER
SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND
USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION
RATE AND SEMICONDUCTOR CHIP MADE THEREBY
Abstract
A method for making 0.25 micron semiconductor chips includes
annealing the metal interconnect lines prior to depositing an
inter-layer dielectric (ILD) between the lines. During annealing,
an alloy of aluminum and titanium forms, which subsequently
volumetrically contracts, with the contraction being absorbed by
the aluminum. Because the alloy is reacted prior to ILD deposition,
however, the aluminum is not constrained by the ILD when it
attempts to absorb the contraction of the alloy. Consequently, the
likelihood of undesirable void formation in the interconnect lines
is reduced. The likelihood of undesirable void formation is still
further reduced during the subsequent ILD gapfill deposition
process by using relatively low bias power to reduce vapor
deposition temperature, and by using relatively low source gas
deposition flow rates to reduce flow-induced compressive stress on
the interconnect lines during ILD formation.
Inventors: |
NGO, MINH VAN; (UNION CITY,
CA) ; BESSER, PAUL R.; (SUNNYVALE, CA) ;
BUYNOSKI, MATTHEW; (PALO ALTO, CA) ; CAFFALL,
JOHN; (SAN CARLOS, CA) ; MACCRAE, NICK; (SAN
JOSE, CA) ; HUANG, RICHARD J.; (CUPERTINO, CA)
; TRAN, KHANH; (SAN JOSE, CA) |
Correspondence
Address: |
LARIVIERE, GRUBMAN & PAYNE, LLP
1 LOWER RAGSDALE, BLDG. 1, SUITE 130
P.O. BOX 3140
MONTEREY
CA
93942
US
|
Family ID: |
22307709 |
Appl. No.: |
09/105775 |
Filed: |
June 26, 1998 |
Current U.S.
Class: |
257/765 ;
257/E21.576; 257/E21.589; 257/E23.16 |
Current CPC
Class: |
H01L 2924/00 20130101;
H01L 21/7685 20130101; H01L 21/76837 20130101; H01L 2924/0002
20130101; H01L 21/76858 20130101; H01L 21/76885 20130101; H01L
2221/1078 20130101; H01L 2924/0002 20130101; H01L 23/53223
20130101 |
Class at
Publication: |
257/765 |
International
Class: |
H01L 029/40; H01L
023/52; H01L 023/48; H01L 023/02 |
Claims
What is claimed is:
1. A method for making a semiconductor chip having electrically
conductive lines, comprising: providing at least one substrate;
establishing at least one predetermined pattern of electrically
conductive lines on the substrate; annealing the electrically
conductive lines; then depositing an inter-layer dielectric (ILD)
between the lines using a source gas at a flow rate no more than
sixty five standard cubic centimeters per minute (65 SCCM).
2. The method of claim 1, further comprising disposing the
substrate on a support and applying a bias power of less than three
thousand four hundred (3400) watts to the support.
3. The method of claim 2, wherein the flow rate is no more than
sixty standard cubic centimeters per minute (60 SCCM).
4. The method of claim 3, wherein the flow rate is between forty
(40) SCCM and 60 SCCM, and the bias power is no more than 3000
watts.
5. The method of claim 1, wherein each line establishes a stack
including at least one layer having aluminum therein, and wherein
an alloy of titanium and aluminum is formed during the annealing
step.
6. The method of claim 5, wherein the annealing step is undertaken
by heating the electrically conductive lines to a temperature of
between three hundred fifty degrees Celsius and four hundred fifty
degrees Celsius (350.degree. C.-450.degree. C.) for a period of
between ten minutes and ninety minutes.
7. The method of claim 1, wherein the ILD is TEOS, and the TEOS is
deposited by directing TEOS onto the lines while simultaneously
removing excess TEOS by sputtering.
8. A chip made according to the method of claim 1.
9. A computing device incorporating the chip of claim 8.
10. A semiconductor chip, comprising: at least one substrate; at
least one predetermined pattern of aluminum lines supported by the
substrate, adjacent lines being separated by distances equal to or
less than about three-eighths of a micron; and an alloy of aluminum
and titanium on the lines, the alloy being reacted prior to
insulating the lines from each other, the lines being insulated
from each other by vapor deposition of an inter layer dielectric
(ILD) therebetween using a source gas at a rate of no more than
sixty standard cubic centimeters per minute (60 SCCM).
11. A method for making a semiconductor chip, comprising:
establishing plural electrically conductive lines on at least one
substrate, at least first lines being separated from second lines
by distances equal to or less than three-eighths of a micron; and
depositing a dielectric between at least two lines that are
adjacent each other using a source gas at a vapor deposition rate
of no more than sixty five standard cubic centimeters per minute
(65 SCCM).
12. The method of claim 11, further comprising: reacting a metal
alloy on the lines before the depositing step, such that the
dielectric substantially does not constrain the lines during the
deposition step.
13. The method of claim 12, wherein the reacting step is undertaken
by annealing the electrically conductive lines to a temperature of
between three hundred fifty degrees Celsius and four hundred fifty
degrees Celsius (350.degree. C.-450.degree. C.) for a period of
between ten minutes and ninety minutes.
14. The method of claim 13, wherein the electrically conductive
lines are exposed to one or more annealing gases during the
reacting step, the annealing gases including nitrogen and
hydrogen.
15. The method of claim 13, wherein the dielectric is TEOS, and the
TEOS is deposited by directing TEOS onto the lines while
simultaneously removing excess TEOS by sputtering.
16. The method of claim 11, further comprising disposing the
substrate on a support and applying a bias power of no more than
three thousand watts to the support.
17. The method of claim 16, wherein the flow rate is between 40
SCCM and 60 SCCM, and the bias power is no more than three thousand
watts.
18. A chip made according to the method of claim 11.
19. A computing device incorporating the chip of claim 18.
Description
TECHNICAL FIELD
[0001] The present invention relates generally to semiconductor
fabrication, and more particularly to methods for improving the
reliability of 0.25.mu. technology semiconductors by alleviating
stress in interconnect lines that might otherwise result in the
formation of voids in the interconnect lines.
BACKGROUND OF THE INVENTION
[0002] Semiconductor chips or wafers are used in many applications,
including as integrated circuits and as flash memory for hand held
computing devices, wireless telephones, and digital cameras.
Regardless of the application, it is desirable that a semiconductor
chip hold as many circuits or memory cells as possible per unit
area. In this way, the size, weight, and energy consumption of
devices that use semiconductor chips advantageously is minimized,
while nevertheless improving the memory capacity and computing
power of the devices.
[0003] In chips that hold integrated circuits, the individual
circuit components are interconnected by conductive elements
referred to as "interconnect lines". These interconnect lines are
typically arranged in a multi-layered pattern that is deposited on
a semiconductive substrate such as silicon. To insulate the
interconnect lines from each other, insulative material is
deposited between adjacent interconnect line layers.
[0004] With the above in mind, so-called 0.25 micron technology has
been developed, in which the distance between adjacent layers of
interconnect lines in an integrated circuit on a semiconductor chip
is equal to or less than about three-eighths of a micron. With such
a small spacing between interconnect lines, which have heights of
about 1.1 microns, the size of the circuits on the chip can be
reduced to result in the above-noted advantages.
[0005] Typically, each electrically conductive interconnect line is
made of a "stack" of metal layers that typically includes a layer
made of aluminum or aluminum alloy, and one or more other metal
layers. The aluminum is deposited as a film over the substrate and
is then lithographically patterned and chemically etched to form a
desired pattern for the circuit's connector lines. Then, a process
referred to as high density plasma (HDP) inter-layer dielectric
(ILD) formation is used to fill the gaps between adjacent metal
stacks with an electrically non-conductive material. Ordinarily,
the ILD deposition step is undertaken at relatively high
temperature, incidentally precipitating the formation of an
intermetallic structure. In current applications, titanium is
commonly used as an underlayer for the aluminum, and the
intermetallic structure that forms in such a device is TiAl.sub.3.
Also, an overlayer that includes TiN anti-reflective coating (ARC)
is disposed over the stacks, for lithography purposes.
[0006] As understood herein, however, voids caused by hydrostatic
stresses undesirably can form in the aluminum, and the voiding of
the aluminum can be accelerated by the formation of the
intermetallic structure. This is undesirable, because when a void
forms in a thin aluminum line, the current path through the line
unfortunately is diverted, thereby adversely affecting the
reliability of the chip.
[0007] The present invention understands that the above-mentioned
hydrostatic stresses arise because the thermal expansion
coefficient of the aluminum layer is different from the thermal
expansion coefficient of the encapsulating ILD and the silicon
substrate, both of which mechanically constrain the aluminum.
Furthermore, when an intermetallic structure such as TiAl.sub.3 is
formed, the intermetallic structure can volumetrically contract (by
5.9%, in the case of TiAl.sub.3), and the aluminum in the
intermetallic structure, which is the most compliant metal in the
stack, will consequently absorb the contraction-induced strain and
thus have an even higher stress state as a result. Additionally, we
have discovered that the undesirable voiding can be accelerated by
relatively high compressive stress caused by high silane flow rates
of sixty six standard cubic meters per minute (66 SCCM) and higher
and relatively high temperatures (caused by applying relatively
high bias power of 3500 watts and higher) during ILD
deposition.
[0008] Fortunately, the present invention recognizes that contrary
to previous methods based on larger-geometry chips, in which
pre-annealing interconnect lines prior to ILD deposition would have
undesirably formed hillocks, i.e., extrusions of metal, in the chip
structure, it is possible to anneal the metal stacks prior to ILD
deposition in 0.25.mu. semiconductors, when only the substrate, and
not the ILD, constrains the aluminum in the stacks. As recognized
by the present invention, the consequence is that the likelihood of
void formation in the interconnect lines is reduced, thereby
improving 0.25.mu. chip reliability. The present invention moreover
understands that relatively low temperatures and silane flow rates
during ILD deposition can be used to further reduce the likelihood
of void formation in the interconnect lines.
BRIEF SUMMARY OF THE INVENTION
[0009] A method is disclosed for making a semiconductor chip having
electrically conductive interconnect lines. The method includes
providing at least one substrate, and establishing at least one
predetermined pattern of electrically conductive interconnect lines
on the substrate. In accordance with the present invention, prior
to depositing a dielectric layer between the interconnect lines,
the lines are annealed, and then the dielectric layer (ILD) is
deposited from a source gas with a flow rate of no more than sixty
five standard cubic centimeters per minute (65 SCCM).
[0010] In a preferred embodiment, the substrate is disposed on a
support, and a bias power of no more than three thousand four
hundred (3400) watts is applied to the support. More preferably,
the bias power is no more than 3000 watts. Further, when the source
gas is silane, the particularly preferred flow rate of the source
gas used to deposit the ILD is less than sixty standard cubic
centimeters per minute (60 SCCM), and can be between forty (40)
SCCM and 60 SCCM.
[0011] As intended by the present invention, each line establishes
a stack including at least one layer having aluminum, and an alloy
of titanium and aluminum is formed during the annealing step. As
disclosed in detail below, the annealing step is undertaken by
heating the electrically conductive lines to a temperature of
between three hundred fifty degrees Celsius and four hundred fifty
degrees Celsius (350.degree. C.-450.degree. C.) for a period of
between ten minutes and ninety minutes. If desired, the ILD can be
silane or TEOS, and the ILD is deposited by directing ILD onto the
lines while simultaneously removing excess ILD by sputtering. A
chip made according to the method, and a computing device
incorporating the chip, are also disclosed.
[0012] In another aspect, a semiconductor chip includes at least
one substrate and at least one predetermined pattern of aluminum
lines supported by the substrate. Adjacent lines are separated by
distances equal to or less than about three-eighths of a micron. An
alloy of aluminum and titanium is formed on the lines, with the
alloy being reacted prior to insulating the lines from each other.
In accordance with the present invention, the lines are insulated
from each other by vapor deposition of an inter layer dielectric
(ILD) from a source gas at a rate of no more than sixty standard
cubic centimeters per minute (60 SCCM).
[0013] In still another aspect, a method for making a semiconductor
chip includes establishing plural electrically conductive lines on
at least one substrate. The lines are spaced from each other by
distances equal to or less than three-eighths of a micron. The
method further includes depositing a dielectric between at least
two lines that are adjacent each other using a source gas at a flow
rate of no more than sixty five standard cubic centimeters per
minute (65 SCCM).
[0014] Other features of the present invention are disclosed or
apparent in the section entitled: "DETAILED DESCRIPTION OF THE
INVENTION."
BRIEF DESCRIPTION OF DRAWINGS
[0015] For fuller understanding of the present invention, reference
is made to the accompanying drawing in the following detailed
description of the Best Mode of Carrying Out the Present Invention.
In the drawings:
[0016] FIG. 1 is a flow chart of the present process for making a
0.25.mu. technology semiconductor chip;
[0017] FIG. 2 is a schematic diagram of the substrate showing the
chip after conductor line stack formation;
[0018] FIG. 3 is a schematic cross-sectional diagram of the
substrate showing the chip after ILD deposition/etching,
schematically showing a computing device that incorporates the
chip; and
[0019] FIG. 4 is a schematic diagram of a high density plasma gap
fill deposition chamber.
[0020] Reference numbers refer to the same or equivalent parts of
the present invention throughout the several figures of the
drawing. In the description, the terms "vertical" and "horizontal"
refer to the orientations of the figures shown, for purposes of
disclosure, and do not necessarily refer to the orientation of the
present wafer once the wafer is embodied in a computing device.
DETAILED DESCRIPTION OF THE INVENTION
[0021] Referring initially to FIGS. 1 and 2, the process of the
present invention in producing 0.25.mu. technology computer chips
can be understood. Commencing at block 10 in FIG. 1 and as shown in
FIG. 2, plural stacks 12 are formed on a substrate 14. Each stack
12 is a metallic, electrically-conductive stack that defines a
respective interconnect line for an integrated circuit chip,
generally designated 16. The chip 16 can establish an integrated
circuit such as a microprocessor or a flash memory chip (e.g., an
electrically programmable memory (EPROM)) for use in the computer
arts. Although only two stacks 12 are shown for clarity of
disclosure, it is to be understood that more than two stacks
typically are formed on the substrate 14.
[0022] Preferably, the substrate 14 includes a semiconductor such
as silicon. Also, the substrate 14 can include a number of devices,
such as metal oxide silicon field effect transistor (MOSFET)
devices, that are electrically connected to one or more of the
stacks 12 via connector plugs.
[0023] In the preferred embodiment, each stack 12 includes a
respective lower titanium layer 18 abutting the substrate 14, an
upper titanium layer 20 parallel to and spaced from the lower
titanium layer 18, and an aluminum layer 22 sandwiched
therebetween. The titanium layers can be titanium or a titanium
alloy such as titanium nitride. It is to be understood that greater
or fewer layers can be provided. In a preferred embodiment, the
aluminum layer 22 is made of aluminum or an aluminum alloy
including aluminum and from 0.1% to about 10% by weight of one or
more of copper, nickel, zinc, gold, titanium, indium, chromium,
silver, palladium, silicon, and platinum.
[0024] The stacks are patterned on the wafer substrate 14 in
accordance with means known in the art, e.g., by depositing the
various metallic layers as films, covering the films with a mask,
and then directing ultraviolet light against the exposed portions
of the films. After lithographic patterning, chemical etching is
used to remove portions of metal not in the pattern to establish
the predetermined pattern of aluminum conductive lines of the chip
16, as shown in FIG. 2.
[0025] As can be appreciated in reference to FIG. 2, the chip 16 a
so-called "quarter micron chip", in that the distance 6 between
adjacent stacks 12 is about equal to or less than three-eighths of
a micron (0.375.mu.).
[0026] Moving to block 24 in FIG. 1, after forming the stacks 12,
the stacks 12 are annealed to form an intermetallic the stacks 12,
with an alloy structure 25 being formed at the interface between
each layer of aluminum and a layer of titanium (only a single alloy
structure 25 shown for clarity of disclosure). In the preferred
embodiment, the metal alloy is an alloy of aluminum and titanium,
and more specifically is TiAl.sub.3. Preferably, the annealing at
block 24 is undertaken by heating the stacks 12 to a temperature of
between three hundred fifty degrees Celsius and four hundred fifty
degrees Celsius (350.degree. C.-450.degree. C.) for a period of
between ten minutes and ninety minutes. Also, during the annealing
step the stacks 12 are exposed to one or more annealing gases,
preferably nitrogen at a flow rate of between eleven standard
liters per minute and fourteen standard liters per minute (11.0
slm-14.0 slm) and hydrogen at a flow rate of between one standard
liter per minute and two standard liters per minute (1.0 slm-2.0
slm).
[0027] After annealing, the chip 16 is cooled. Accordingly, as
provided by the present invention the TiAl.sub.3, which would
otherwise form during ILD deposition and contract during the
subsequent cool down when the stacks 12 are constrained by the ILD,
is instead formed prior to ILD deposition, thus permitting the
aluminum in the stacks 12 to absorb contraction from the TiAl.sub.3
before the stacks 12 are constrained by the ILD. This reduces the
likelihood that voids will undesirably form in the interconnect
lines of the chip 16.
[0028] Moving to block 26 of FIG. 1 and referring to FIG. 3, an
interlayer dielectric (ILD) 28 is deposited between the stacks 12
to insulate the stacks 12. While the present invention envisions
using any appropriate high density plasma (HDP) ILD such as silane
((SiH.sub.4), tetraethoxy silane (TEOS) can also be used to avoid
the production of free hydrogen that could otherwise embrittle the
aluminum.
[0029] To understand the preferred embodiment cross-reference is
made to FIGS. 3 and 4. A high density plasma (HDP) chamber 30 (FIG.
4) is enclosed by a wall 32. A support 34 is disposed in the
chamber 30, and the support 34 may include an e-chuck 36. One or
more wafers or substrates 22 are in turn disposed on the e-chuck
36.
[0030] To provide for depositing ILD on the wafer 22, a source gas
inlet 38 and an oxygen inlet 40 are associated with the chamber
wall 32 to respectively direct a source gas (such as silane) and
oxygen into the chamber 30, and a source power lead 42 is likewise
associated with the chamber 30. In the preferred embodiment, a
source gas such as silane is directed into the chamber 30 at a rate
ranging from 40 standard cubic centimeters per minute (SCCM) to
sixty five standard cubic centimeters per minute (65 SCCM), and
more preferably at a rate of no more than 60 SCCM. In contrast,
oxygen is directed into the chamber 30 at a rate ranging from one
hundred ten standard cubic centimeters per minute to one hundred
thirty standard cubic centimeters per minute (110 SCCM-130 SCCM).
The pressure within the chamber 30 is maintained between one
milliTorr and six milliTorr (1 mTorr-6 mTorr), and the source power
applied to the chamber 30 is between two thousand watts and five
thousand watts (2000 w-5000 w). In accordance with the present
invention, the solid ILD is subsequently established from the
source gas that is deposited by vapor deposition as described.
[0031] To provide for simultaneous sputtering of the ILD while it
is being deposited, an etchant inlet 44 is associated with the wall
32 to port a gaseous sputtering agent, preferably argon, into the
chamber 30. Also, a bias power lead 46 is connected to the e-chuck
36, and bias power is maintained at no more than three thousand
four hundred watts (3400 w), and more preferably at no more than
3000 watts.
[0032] If desired, both the annealing step and the subsequent ILD
deposition step can be undertaken in the chamber 30. If the
annealing step is to be undertaken in the chamber 30, nitrogen and
hydrogen inlets (not shown) are provided in the chamber 30.
[0033] The completion of the chip 16 may proceed in any such manner
as is required by its design. The resulting chip 16 can be
incorporated into a computing device 50 (FIG. 3), e.g., a computer,
digital camera, wireless telephone, or hand held computer, for use
by the computing device 50.
[0034] The principles of the present invention are equally
applicable to a wide range of semiconductor and integrated circuit
design and manufacture regimens, including but not necessarily
limited to the production of non-volatile memory devices. All such
implementations are specifically contemplated by the principles of
the present intention.
[0035] The present invention has been particularly shown and
described with respect to certain preferred embodiments and
features thereof. However, it should be readily apparent to those
of ordinary skill in the art that various changes and modifications
in form and detail may be made without departing from the spirit
and scope of the inventions as set forth in the appended claims, in
which reference to an element in the singular is not intended to
mean "one and only one" unless explicitly so stated, but rather
"one or more". The inventions illustratively disclosed herein may
be practiced without any element which is not specifically
disclosed herein.
* * * * *