Huang; Richard J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Huang; Richard J..The latest application filed is for "mask for forming integrated circuit".

Company Profile

0.53.10

Huang; Richard J. - Cupertino CA US
Huang, Richard J. - Cupertion CA
Huang; Richard J. - Milpitas CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Mask for forming integrated circuit Grant 8,629,535 - Huang , et al. January 14, 2	2014-01-14
Mask For Forming Integrated Circuit App 20120007221 - Huang; Richard J. ; et al.	2012-01-12
Method for forming integrated circuit Grant 7,521,304 - Huang , et al. April 21, 2	2009-04-21
Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes Grant 7,183,198 - Gao , et al. February 27, 2	2007-02-27
Method of using carbon spacers for critical dimension (CD) reduction Grant 7,169,711 - Lyons , et al. January 30, 2	2007-01-30
Slurry-less polishing for removal of excess interconnect material during fabrication of a silicon integrated circuit Grant 7,141,502 - Xie , et al. November 28, 2	2006-11-28
Method of forming an interlevel dielectric layer employing dielectric etch-back process without extra mask set Grant 7,132,306 - Rhee , et al. November 7, 2	2006-11-07
Use of multilayer amorphous carbon ARC stack to eliminate line warpage phenomenon Grant 7,084,071 - Dakshina-Murthy , et al. August 1, 2	2006-08-01
Use of amorphous carbon for gate patterning Grant 7,015,124 - Fisher , et al. March 21, 2	2006-03-21
Semiconductor component and method of manufacture Grant 6,927,113 - Sahota , et al. August 9, 2	2005-08-09
Formation of amorphous carbon ARC stack having graded transition between amorphous carbon and ARC material Grant 6,875,664 - Huang , et al. April 5, 2	2005-04-05
EUV reflective mask having a carbon film and a method of making such a mask Grant 6,869,734 - Lyons , et al. March 22, 2	2005-03-22
CVD organic polymer film for advanced gate patterning Grant 6,864,556 - You , et al. March 8, 2	2005-03-08
Hardmask employing multiple layers of silicon oxynitride App 20050048771 - Gao, Pei-Yuan ; et al.	2005-03-03
Method of using amorphous carbon to prevent resist poisoning Grant 6,855,627 - Dakshina-Murthy , et al. February 15, 2	2005-02-15
Continuous barrier for interconnect structure formed in porous dielectric material with minimized electromigration Grant 6,831,003 - Huang , et al. December 14, 2	2004-12-14
Method for forming a hardmask employing multiple independently formed layers of a pecvd material to reduce pinholes Grant 6,803,313 - Gao , et al. October 12, 2	2004-10-12
Method For Manufacturing A Semiconductor Component Having A Barrier-lined Opening App 20040175926 - Wang, Pin-Chin Connie ; et al.	2004-09-09
Cu damascene interconnections using barrier/capping layer Grant 6,689,684 - You , et al. February 10, 2	2004-02-10
Use of diamond as a hard mask material Grant 6,673,684 - Huang , et al. January 6, 2	2004-01-06
Method of shallow trench isolation (STI) formation using amorphous carbon Grant 6,653,202 - Fisher , et al. November 25, 2	2003-11-25
Method and system for reducing charge gain and charge loss in interlayer dielectric formation Grant 6,635,943 - Hui , et al. October 21, 2	2003-10-21
Method of forming copper interconnect capping layers with improved interface and adhesion Grant 6,596,631 - Ngo , et al. July 22, 2	2003-07-22
Method of using amorphous carbon as spacer material in a disposable spacer process Grant 6,559,017 - Brown , et al. May 6, 2	2003-05-06
Semiconductor device with variable composition low-k inter-layer dielectric and method of making Grant 6,518,646 - Hopper , et al. February 11, 2	2003-02-11
Method of re-working copper damascene wafers Grant 6,495,443 - Lopatin , et al. December 17, 2	2002-12-17
Tungsten gate MOS transistor and memory cell and method of making same App 20020137284 - Chang, Chi ; et al.	2002-09-26
Surface treatment of low-K SiOF to prevent metal interaction Grant 6,444,593 - Ngo , et al. September 3, 2	2002-09-03
Method for removing copper from a wafer edge App 20020106905 - Tran, Minh Q. ; et al.	2002-08-08
Method of fabricating dual damascene with silicon carbide via mask/ARC Grant 6,429,121 - Hopper , et al. August 6, 2	2002-08-06
Non-volatile memory device with encapsulated tungsten gate and method of making same Grant 6,429,108 - Chang , et al. August 6, 2	2002-08-06
Methods of manufacture of uniform spin-on films Grant 6,407,009 - You , et al. June 18, 2	2002-06-18
Integration of low-k SiOF for damascene structure Grant 6,400,023 - Huang June 4, 2	2002-06-04
Solution flow-in for uniform deposition of spin-on films Grant 6,387,825 - You , et al. May 14, 2	2002-05-14
Method of making tungsten gate MOS transistor and memory cell by encapsulating Grant 6,346,467 - Chang , et al. February 12, 2	2002-02-12
Method For Reducing Stress-induced Voids For 0.25u And Smaller Semiconductor Chip Technology By Annealing Interconnect Lines And Using Low Bias Voltage And Low Interlayer Dielectric Deposition Rate And Semiconductor Chip Made Thereby App 20020003306 - NGO, MINH VAN ; et al.	2002-01-10
Methods for characterizing and reducing adverse effects of texture of semiconductor films App 20010053600 - Morales, Guarionex ; et al.	2001-12-20
Method for reducing stress-induced voids for 0.25m.mu. and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby Grant 6,329,718 - Van Ngo , et al. December 11, 2	2001-12-11
Surface Treatment Of Low-k Siof To Prevent Metal Interaction App 20010044203 - HUANG, RICHARD J. ; et al.	2001-11-22
Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces Grant 6,281,584 - Ngo , et al. August 28, 2	2001-08-28
Integration of low-k SiOF for damascene structure App 20010016419 - Huang, Richard J.	2001-08-23
Apparatus For Manufacturing Planar Spin-on Films App 20010001407 - YOU, LU ; et al.	2001-05-24
Low-k photoresist removal process Grant 6,235,453 - You , et al. May 22, 2	2001-05-22
Methods and arrangements for reducing stress and preventing cracking in a silicide layer Grant 6,211,074 - Huang , et al. April 3, 2	2001-04-03
Apparatus and method for manufacturing semiconductors using low dielectric constant materials Grant 6,197,703 - You , et al. March 6, 2	2001-03-06
Integration of low-K SiOF for damascene structure Grant 6,177,364 - Huang January 23, 2	2001-01-23
Integration of low-K SiOF as inter-layer dielectric for AL-gapfill application Grant 6,166,427 - Huang , et al. December 26, 2	2000-12-26
Reduction of silicon oxynitride film delamination in integrated circuit inter-level dielectrics Grant 6,133,619 - Sahota , et al. October 17, 2	2000-10-17
Scalable and reliable integrated circuit inter-level dielectric Grant 6,124,640 - Sahota , et al. September 26, 2	2000-09-26
Semiconductor device containing P-HDP interdielectric layer Grant 6,080,639 - Huang , et al. June 27, 2	2000-06-27
Stacked gate structure for flash memory application Grant 6,060,741 - Huang May 9, 2	2000-05-09
Vacuum baked HSQ gap fill layer for high integrity borderless vias Grant 6,030,891 - Tran , et al. February 29, 2	2000-02-29
Photoresist stripping without degrading low dielectric constant materials Grant 6,030,901 - Hopper , et al. February 29, 2	2000-02-29
Surface treatment of low-k SiOF to prevent metal interaction Grant 5,994,778 - Huang , et al. November 30, 1	1999-11-30
HSQ processing for reduced dielectric constant Grant 5,888,911 - Ngo , et al. March 30, 1	1999-03-30
Low RC interconnection Grant 5,861,677 - You , et al. January 19, 1	1999-01-19
Low RC interconnection Grant 5,760,480 - You , et al. June 2, 1	1998-06-02
Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology Grant 5,686,761 - Huang , et al. November 11, 1	1997-11-11
Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC application Grant 5,674,781 - Huang , et al. October 7, 1	1997-10-07
Tunneling technology for reducing intra-conductive layer capacitance Grant 5,670,828 - Cheung , et al. September 23, 1	1997-09-23
Landing pad technology doubled up as local interconnect and borderless contact for deep sub-half micrometer IC application Grant 5,654,589 - Huang , et al. August 5, 1	1997-08-05
Simplified dual damascene process for multi-level metallization and interconnection structure Grant 5,635,423 - Huang , et al. June 3, 1	1997-06-03

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