Buynoski; Matthew

Patent Applications and Registrations

Patent applications and USPTO patent grants for Buynoski; Matthew.The latest application filed is for "method of forming controllably conductive oxide".

Company Profile

1.26.11

Buynoski; Matthew - Palo Alto CA
Buynoski, Matthew . - Palo Alto CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of forming controllably conductive oxide Grant 10,147,877 - Buynoski , et al. De	2018-12-04
Method of forming controllably conductive oxide App 20160380195 - BUYNOSKI; Matthew ; et al.	2016-12-29
Method of forming controllably conductive oxide Grant 9,461,247 - Buynoski , et al. October 4, 2	2016-10-04
Method Of Forming Controllably Conductive Oxide App 20150144857 - BUYNOSKI; Matthew ; et al.	2015-05-28
Method of forming controllably conductive oxide Grant 8,946,020 - Buynoski , et al. February 3, 2	2015-02-03
Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device Grant 8,093,698 - Rathor , et al. January 10, 2	2012-01-10
Test structures for development of metal-insulator-metal (MIM) devices Grant 8,084,770 - Avanzino , et al. December 27, 2	2011-12-27
Test Stuctures for development of metal-insulator-metal (MIM) devices App 20090072234 - Avanzino; Steven ; et al.	2009-03-19
Method of forming controllably conductive oxide App 20090067213 - Buynoski; Matthew ; et al.	2009-03-12
Ta-lined tungsten plugs for transistor-local hydrogen gathering App 20090065842 - Buynoski; Matthew	2009-03-12
Thin film germanium diode with low reverse breakdown Grant 7,468,296 - Adem , et al. December 23, 2	2008-12-23
Test structures for development of metal-insulator-metal (MIM) devices Grant 7,468,525 - Avanzino , et al. December 23, 2	2008-12-23
Test structures for development of metal-insulator-metal (MIM) devices App 20080128691 - Avanzino; Steven ; et al.	2008-06-05
Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device App 20080130195 - Rathor; Manuj ; et al.	2008-06-05
Diode Array Architecture For Addressing Nanoscale Resistive Memory Arrays App 20060104111 - Tripsas; Nicholas H. ; et al.	2006-05-18
Diode array architecture for addressing nanoscale resistive memory arrays Grant 7,035,141 - Tripsas , et al. April 25, 2	2006-04-25
Methods for fabricating CMOS-compatible lateral bipolar junction transistors Grant 6,861,325 - Pan , et al. March 1, 2	2005-03-01
Self-aligned triple gate silicon-on-insulator (SOI) device Grant 6,727,546 - Krivokapic , et al. April 27, 2	2004-04-27
Method of making a self-aligned triple gate silicon-on-insulator device Grant 6,716,684 - Krivokapic , et al. April 6, 2	2004-04-06
Method for manufacturing CMOS device having low gate resistivity using aluminum implant Grant 6,660,608 - Buynoski December 9, 2	2003-12-09
Metal silicide gate transistors Grant 6,602,781 - Xiang , et al. August 5, 2	2003-08-05
Self-aligned triple gate silicon-on-insulator (SOI) device App 20030136963 - Krivokapic, Zoran ; et al.	2003-07-24
Method of copper-polysilicon T-gate formation Grant 6,500,743 - Lopatin , et al. December 31, 2	2002-12-31
Selectively thin silicon film for creating fully and partially depleted SOI on same wafer Grant 6,492,209 - Krishnan , et al. December 10, 2	2002-12-10
Silicide gate transistors Grant 6,465,309 - Xiang , et al. October 15, 2	2002-10-15
Tantalum anodization for in-laid copper metallization capacitor Grant 6,433,379 - Lopatin , et al. August 13, 2	2002-08-13
Damascene nisi metal gate high-k transistor App 20020102848 - Xiang, Qi ; et al.	2002-08-01
Self-aligned double gate silicon-on-insulator (SOI) device Grant 6,396,108 - Krivokapic , et al. May 28, 2	2002-05-28
Method For Reducing Stress-induced Voids For 0.25u And Smaller Semiconductor Chip Technology By Annealing Interconnect Lines And Using Low Bias Voltage And Low Interlayer Dielectric Deposition Rate And Semiconductor Chip Made Thereby App 20020003306 - NGO, MINH VAN ; et al.	2002-01-10
Method for reducing stress-induced voids for 0.25m.mu. and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby Grant 6,329,718 - Van Ngo , et al. December 11, 2	2001-12-11
Practical way to remove heat from SOI devices Grant 6,190,985 - Buynoski February 20, 2	2001-02-20
Heat removal from SOI devices by using metal substrates Grant 6,166,411 - Buynoski December 26, 2	2000-12-26
Semiconductor device having enhanced gate capacitance by using both high and low dielectric materials Grant 6,100,558 - Krivokapic , et al. August 8, 2	2000-08-08
Method for increasing gate capacitance by using both high and low dielectric gate material Grant 6,087,208 - Krivokapic , et al. July 11, 2	2000-07-11
Method providing, an enriched source side extension and a lightly doped extension Grant 5,756,381 - Buynoski May 26, 1	1998-05-26
Self-aligned masking for ultra-high energy implants with application to localized buried implants and insolation structures Grant 5,043,292 - Aronowitz , et al. August 27, 1	1991-08-27

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