U.S. patent application number 10/990706 was filed with the patent office on 2006-05-18 for diode array architecture for addressing nanoscale resistive memory arrays.
This patent application is currently assigned to Spansion LLC. Invention is credited to Steven Avanzino, Colin S. Bill, Matthew Buynoski, Wei Daisy Cai, Tzu-Ning Fang, Suzette Pangrle, Nicholas H. Tripsas, Michael A. VanBuskirk.
Application Number | 20060104111 10/990706 |
Document ID | / |
Family ID | 36021799 |
Filed Date | 2006-05-18 |
United States Patent
Application |
20060104111 |
Kind Code |
A1 |
Tripsas; Nicholas H. ; et
al. |
May 18, 2006 |
DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY
ARRAYS
Abstract
The present memory structure includes thereof a first conductor,
a second conductor, a resistive memory cell connected to the second
conductor, a first diode connected to the resistive memory cell and
the first conductor, and oriented in the forward direction from the
resistive memory cell to the first conductor, and a second diode
connected to the resistive memory cell and the first conductor, in
parallel with the first diode, and oriented in the reverse
direction from the resistive memory cell to the first conductor.
The first and second diodes have different threshold voltages
Inventors: |
Tripsas; Nicholas H.; (San
Jose, CA) ; Bill; Colin S.; (Cupertino, CA) ;
VanBuskirk; Michael A.; (Saratoga, CA) ; Buynoski;
Matthew; (Palo Alto, CA) ; Fang; Tzu-Ning;
(Palo Alto, CA) ; Cai; Wei Daisy; (Fremont,
CA) ; Pangrle; Suzette; (Cupertino, CA) ;
Avanzino; Steven; (Cupertino, CA) |
Correspondence
Address: |
Paul J. Winters
307 Cypress Point Drive
Mountain View
CA
94043
US
|
Assignee: |
Spansion LLC
|
Family ID: |
36021799 |
Appl. No.: |
10/990706 |
Filed: |
November 17, 2004 |
Current U.S.
Class: |
365/175 ;
257/E27.071; 257/E27.073 |
Current CPC
Class: |
H01L 27/101 20130101;
H01L 27/1021 20130101; G11C 13/0007 20130101; G11C 2213/72
20130101; G11C 2213/56 20130101; G11C 2213/76 20130101; G11C 13/003
20130101; G11C 13/0002 20130101; G11C 2213/74 20130101 |
Class at
Publication: |
365/175 |
International
Class: |
G11C 11/36 20060101
G11C011/36 |
Claims
1. (canceled)
2. A memory structure comprising: a first conductor; a second
conductor; a resistive memory cell connected to the second
conductor; a first diode connected to the resistive memory cell and
the first conductor, and oriented in the forward direction from the
resistive memory cell to the first conductor; and a second diode
connected to the resistive memory cell and the first conductor, in
parallel with the first diode, and oriented in the reverse
direction from the resistive memory cell to the first conductor;
wherein the first and second diodes have different threshold
voltages.
3. (canceled)
4. A memory structure comprising: a first conductor; a second
conductor; a memory cell connected to the second conductor; a first
diode connected to the memory cell and the first conductor; and a
second diode connected to the memory cell and the first conductor,
in parallel with the first diode; wherein the first and second
diodes have different threshold voltages.
5. The memory structure of claim 4 wherein the first diode is
oriented in the forward direction from the memory cell to the first
conductor, and the second diode is oriented in the reverse
direction from the memory cell to the first conductor.
6. The memory structure of claim 4 wherein the memory cell is a
resistive memory cell.
7. (canceled)
8. A memory array comprising; a first plurality of conductors; a
second plurality of conductors, and; a plurality of memory
structures, each connecting a conductor of the first plurality
thereof with a conductor of the second plurality thereof, each
memory structure comprising; a resistive memory cell connected to a
conductor of the second plurality thereof; a first diode connected
to the resistive memory cell and a conductor of the first plurality
thereof, and oriented in the forward direction from the resistive
memory cell to the conductor of the first plurality thereof; and a
second diode connected to the resistive memory cell and the
conductor of the first plurality thereof, in parallel with the
first diode, and oriented in the reverse direction from the
resistive memory cell to the conductor of the first plurality
thereof; wherein the first and second diodes have different
threshold voltages.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Technical Field
[0002] This invention relates generally to memory devices, and more
particularly, to a memory array incorporating resistive memory
cells.
[0003] 2. Background Art
[0004] Generally, memory devices associated with computers and
other electronic devices are employed to store and maintain
information for the operation thereof. Typically, such a memory
device includes an array of memory cells, wherein each memory cell
can be accessed for programming, erasing, and reading thereof. Each
memory cell maintains information in an "off" state or an "on"
state, also referred to as "0" and "1" respectively, which can be
read during the reading step of that memory cell.
[0005] As such electronic devices continue to be developed and
improved, the amount of information required to be stored and
maintained continues to increase. FIG. 1 illustrates a type of
memory cell known as a nanoscale resistive memory cell 30, which
includes advantageous characteristics for meeting these needs. The
memory cell 30 includes, for example, a Cu electrode 32, a
superionic layer 34 such as Cu.sub.2S on the electrode 32, an
active layer 36 such as Cu.sub.2O or various polymers on the
Cu.sub.2S layer 34, and a Ti electrode 38 on the active layer 36.
Initially, assuming that the memory cell 30 is unprogrammed, in
order to program the memory cell 30, a negative voltage is applied
to the electrode 38, while the electrode 32 is held at ground, so
that an electrical potential V.sub.pg (the "programming" electrical
potential) is applied across the memory cell 30 from a higher to a
lower potential in the direction from electrode 32 to electrode 38
(see FIG. 2, a plot of memory cell current vs. electrical potential
applied across the memory cell 30). This potential is sufficient to
cause copper ions to be attracted from the superionic layer 34
toward the electrode 38 and into the active layer 36, causing the
active layer 36 (and the overall memory cell 30) to be in a
low-resistance or conductive state (A). Upon removal of such
potential (B), the copper ions drawn into the active layer 36
during the programming step remain therein, so that the active
layer 36 (and memory cell 30) remain in a conductive or
low-resistance state.
[0006] In order to erase the memory cell (FIG. 2), a positive
voltage is applied to the electrode 38, while the electrode 32 is
held at ground, so that an electrical potential V.sub.er (the
"erase" electrical potential) is applied across the memory cell 30
from a higher to a lower electrical potential in the reverse
direction. This potential causes current to flow through the memory
cell in the reverse direction (C), and is sufficient to cause
copper ions to be repelled from the active layer 36 toward the
electrode 32 and into the superionic layer 34, in turn causing the
active layer 36 (and the overall memory cell 30) to be in a
high-resistance or substantially non-conductive state. This state
remains upon removal of such potential from the memory cell 30.
[0007] FIG. 2 also illustrates the read step of the memory cell 30
in its programmed (conductive) state and in its erased
(nonconductive) state. An electrical potential V.sub.r (the "read"
electrical potential) is applied across the memory cell 30 from a
higher to a lower electrical potential in the same direction as the
electrical potential V.sub.pg. This electrical potential is less
than the electrical potential V.sub.pg applied across the memory
cell 30 for programming (see above). In this situation, if the
memory cell 30 is programmed, the memory cell 30 will readily
conduct current (level L1), indicating that the memory cell 30 is
in its programmed state. If the memory cell 30 is erased, the
memory cell 30 will not conduct current (level L2), indicating that
the memory cell 30 is in its erased state.
[0008] FIGS. 3, 4 and 5 illustrate a memory cell array 40 which
incorporates memory cells 30 of the type described above. As
illustrated in FIG. 3, the memory cell array 40 includes a first
plurality 42 of parallel conductors (bit lines) BL.sub.0, BL.sub.1,
. . . BL.sub.n, and a second plurality 44 of parallel conductors
(word lines) WL.sub.0, WL.sub.1, . . . WL.sub.n overlying and
spaced from, orthogonal to, and crossing the first plurality of
conductors 42. A plurality of memory cells 30 of the type described
above are included, each associated with a select diode 50 having a
(forward) threshold V.sub.t and a (reverse) breakdown voltage
V.sub.b, to form a memory cell-diode structure. Each memory cell 30
is connected in series with a select diode 50 between a conductor
BL of the first plurality 42 thereof and a conductor WL of the
second plurality 44 thereof at the intersection of those
conductors, with the diode 50 oriented in a forward direction from
the conductor BL of the first plurality 42 thereof to the conductor
WL of the second plurality 44 thereof. For example, as shown in
FIG. 3, memory cell 30.sub.00 and diode 50.sub.00 in series connect
conductor BL.sub.0 of the first plurality of conductors 42 with
conductor WL.sub.0 of the second plurality of conductors 44 at the
intersection of those conductors BL.sub.0, WL.sub.0, memory cell
30.sub.10 and diode 50.sub.10 in series connect conductor BL.sub.1
of the first plurality of conductors 42 with conductor WL.sub.0 of
the second plurality of conductors 44 at the intersection of those
conductors BL.sub.1, WL.sub.0, etc.
[0009] In order to program a selected memory cell (FIG. 3), for
example selected memory cell 30.sub.00, the voltage applied to the
conductor BL.sub.0 is selected as (V.sub.pg+V.sub.t) greater than
the voltage (0) applied to the conductor WL.sub.0, where V.sub.pg
is as defined above and V.sub.t=(forward) threshold voltage of
diode 50.sub.00. Additionally, this same voltage V.sub.pg+V.sub.t
is applied to each of the conductors WL1, . . . WL.sub.n, and zero
voltage is applied to each of the conductors BL1, . . . BL.sub.n.
This results in zero potential being applied across each of the
memory cell-diode structures (other than the selected memory cell
30.sub.00 and diode 50.sub.00 structure) connected to the conductor
BL.sub.0 and the conductor WL.sub.0. Each of the other memory
cell-diode structures has applied thereacross, from higher to lower
potential in the reverse direction of the diode 50, an electrical
potential which is equal to V.sub.pg+V.sub.t. This electrical
potential is less than the breakdown voltage V.sub.b of the diode
50, and thus no current flows through the associated memory cell.
Thus, the incorporation of the diodes 50 allows one to properly
select and program a memory cell, without disturbing any of the
other memory cells in the array.
[0010] In order to erase a selected memory cell (FIG. 4), for
example selected memory cell 30.sub.00, the voltage applied to the
conductor WL.sub.0 is (V.sub.er+V.sub.b) greater than the voltage
(0) applied to the conductor BL.sub.0, where V.sub.er is as defined
above and V.sub.b=(reverse) breakdown voltage of diode 50.sub.00.
Additionally, a voltage of for example 0.5(V.sub.pg+V.sub.t) is
applied to each of the conductors WL1, . . . WL.sub.n, and each of
the conductors BL1, . . . BL.sub.n. This results a potential of
0.5(V.sub.pg+V.sub.t) being applied across each of the diode-memory
cell structures (other than the selected memory cell 30.sub.00 and
diode 50.sub.00 structure) connected to the conductor BL.sub.0 and
the conductor WL.sub.0, from higher to lower potential in the
reverse direction of the diode 50. This electrical potential
0.5(V.sub.pg+V.sub.t) is less than the breakdown voltage V.sub.b of
the diode 50, and thus no current will flow through the associated
memory cell. Each of the other memory cell-diode structures has
applied thereacross an electrical potential of zero. Similar to the
above, the incorporation of the diodes 50 allows one to properly
select and erase a memory cell, without disturbing any of the other
memory cells in the array.
[0011] In order to read a selected memory cell (FIG. 5), for
example selected memory cell 30.sub.00, the voltage applied to the
conductor BL.sub.0 is (V.sub.r+V.sub.t) greater than the voltage
(0) applied to the conductor WL.sub.0, where V.sub.r is as defined
above and V.sub.t=threshold voltage of diode 50.sub.00).
Additionally, a voltage of V.sub.r+V.sub.t is applied to each of
the conductors WL1, . . . WL.sub.n, and zero voltage is applied to
each of the conductors BL1, . . . BL.sub.n. This results in zero
potential applied across each of the memory cell-diode structures
(other than the selected memory cell 30.sub.00 and diode 50.sub.00
structure) connected to the conductor BL.sub.1 and WL.sub.0. Each
of the other memory cell-diode structures has applied thereacross,
from higher to lower potential in the reverse direction of the
diode 50, an electrical potential which is equal to
V.sub.r+V.sub.t. This potential V.sub.r+V.sub.t is less than the
breakdown voltage of the diode 50, so that no current passes
through the associated memory cell. Thus, the incorporation of the
diodes 50 allows one to properly select and read a memory cell,
without disturbing or otherwise influencing any of the other memory
cells in the array.
[0012] FIG. 6 illustrates ideal (G) and actual (H) voltage-current
characteristics for a diode of the type incorporated in the memory
array of FIGS. 3-5. It is to be noted that in order to achieve
erasing of a selected memory cell, current must be conducted
through the selected memory cell, and in order to achieve this
conduction of current, the diode associated therewith must be in
breakdown. Ideally, such a diode would have a low threshold voltage
(forward direction of the diode) on the order of 0.6 volts, and a
low breakdown voltage (reverse direction of the diode) on the order
of 2.0 volts, as these voltages would readily allow rapid and
effective programming, reading, erasing of a selected cell with
relatively low electrical potentials applied thereto, so that a low
potential power supply can be used.
[0013] However, in reality, while a typical diode may indeed have a
threshold voltage on then order of 0.6 volts, the breakdown voltage
is substantially greater than 2.0 volts (illustrated at in FIG. 6),
i.e., for example, 4.5 volts or substantially more. This leads to
problems in achieving breakdown of the diode, which is essential in
erasing the associated memory cell as described above.
[0014] Therefore, what is needed is an approach wherein the ideal
characteristics described above are achieved.
DISCLOSURE OF THE INVENTION
[0015] Broadly stated, the present memory structure comprises a
first conductor, a second conductor, a resistive memory cell
connected to the second conductor, a first diode connected to the
resistive memory cell and the first conductor, and oriented in the
forward direction from the resistive memory cell to the first
conductor, and a second diode connected to the resistive memory
cell and the first conductor, in parallel with the first diode, and
oriented in the reverse direction from the resistive memory cell to
the first conductor.
[0016] The present invention is better understood upon
consideration of the detailed description below, in conjunction
with the accompanying drawings. As will become readily apparent to
those skilled in the art from the following description, there is
shown and described an embodiment of this invention simply by way
of the illustration of the best mode to carry out the invention. As
will be realized, the invention is capable of other embodiments and
its several details are capable of modifications and various
obvious aspects, all without departing from the scope of the
invention. Accordingly, the drawings and detailed description will
be regarded as illustrative in nature and not as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The novel features believed characteristic of the invention
are set forth in the appended claims. The invention itself,
however, as well as said preferred mode of use, and further objects
and advantages thereof, will best be understood by reference to the
following detailed description of an illustrative embodiment when
read in conjunction with the accompanying drawings, wherein:
[0018] FIG. 1 is a cross-sectional view of a typical resistive
memory cell;
[0019] FIG. 2 is a plot of current vs. voltage in the programming,
reading and erasing of the memory cell of FIG. 1;
[0020] FIG. 3 is a schematic illustration of a memory array which
includes memory cells in accordance with FIG. 1, illustrating
programming of a selected memory cell;
[0021] FIG. 4 is a schematic illustration of a memory array which
includes memory cells in accordance with FIG. 1, illustrating
erasing of a selected memory cell;
[0022] FIG. 5 is a schematic illustration of a memory array which
includes memory cells in accordance with FIG. 1, illustrating
reading of a selected memory cell;
[0023] FIG. 6 is a plot of current vs. voltage illustrating diode
characteristics;
[0024] FIG. 7 is a schematic illustration of the first embodiment
of the invention;
[0025] FIG. 8 is a plot of current vs. voltage for the invention of
FIG. 7 and the invention of FIG. 10;
[0026] FIG. 9 is a schematic illustration of a memory array
incorporating the invention of FIG. 7, illustrating programming of
a selected memory cell;
[0027] FIG. 10 is a schematic illustration of a memory array
incorporating the invention of FIG. 7, illustrating erasing of a
selected memory cell; and
[0028] FIG. 11 is a schematic illustration of a memory array
incorporating the invention of FIG. 7, illustrating reading of a
selected memory cell.
BEST MODE(S) FOR CARRYING OUT THE INVENTION
[0029] Reference is now made in detail to a specific embodiment of
the present invention which illustrates the best mode presently
contemplated by the inventors for practicing the invention.
[0030] FIG. 7 illustrates an embodiment of the present invention. A
conductor BL is shown therein, and a conductor WL overlies, crosses
and is spaced from the conductor BL. A structure 60 interconnects
the conductor BL and the conductor WL at the intersection thereof.
The structure 60 includes a resistive memory cell 130, similar to
the resistive memory cell 30 above, connected to the conductor WL,
a first diode 132 connected to the resistive memory cell 130 and
the conductor BL, and a second diode 134 also connected to the
resistive memory cell 130 and the conductor BL, in parallel with
the first diode 132. The first diode 132 is oriented in the forward
direction from the resistive memory cell 130 to the conductor BL,
and the second diode 134 is oriented in the reverse direction from
the resistive memory cell 130 to the conductor BL. The diodes
132,134 are selected to have different (forward) threshold
voltages, for example, diode 132 has threshold voltage V.sub.t1=0.6
volts, while diode 134 has threshold voltage V.sub.t2=2.0 volts.
Both diodes 132 and 134 have (reverse) breakdown voltages of
V.sub.b=4.5 volts as previously described. When considered as a
unit, the two diodes in parallel making up the parallel diode
structure 62 connected between the resistive memory cell 130 and
the conductor BL have the current-voltage characteristic shown in
FIG. 8. In the direction from the conductor BL to the resistive
memory cell 130, the diode 132 will begin to conduct at its
threshold voltage of 0.6 volts, well below the breakdown voltage
(4.5 volts) of the diode 134. In the direction from the memory cell
130 to the conductor BL, the diode 134 will begin to conduct at its
threshold voltage of 2.0 volts, well below the breakdown voltage
(4.5 volts) of the diode 132. The net result is that the parallel
diode structure 62 including diodes 132,134 in parallel is
substantially the equivalent of a single diode having the
characteristics shown in FIG. 8, close to the ideal diode (FIG. 6)
as discussed above.
[0031] FIGS. 9, 10 and 11 illustrate a memory cell array 140 which
incorporates memory cells 130 of the type described above. As
illustrated in FIG. 9, the memory cell array 140 includes a first
plurality 142 of parallel conductors (bit lines) BL.sub.0,
BL.sub.1, . . . BL.sub.n, and a second plurality 144 of parallel
conductors (word lines) WL.sub.0, WL.sub.1, . . . WL.sub.n
overlying and spaced from, orthogonal to, and crossing the first
plurality of conductors 142. A plurality of structures 60 as set
forth above are included, each connecting a conductor BL with a
conductor WL at the intersection thereof. Each structure includes a
resistive memory cell 130 and a parallel diode structure 62,
connected and configured as described above. For example, as shown
in FIG. 9, memory cell 130.sub.00 and parallel diode structure
62.sub.00 in series connect conductor BL.sub.0 of the first
plurality of conductors 142 with conductor WL.sub.0 of the second
plurality of conductors 144 at the intersection of those conductors
BL.sub.0, WL.sub.0, memory cell 130.sub.10 and parallel diode
structure 62.sub.10 in series connect conductor BL.sub.1 of the
first plurality of conductors 142 with conductor WL.sub.0 of the
second plurality of conductors 144 at the intersection of those
conductors BL.sub.1, WL.sub.0, etc.
[0032] In order to program a selected memory cell (FIG. 9), for
example selected memory cell 130.sub.00, the voltage applied to the
conductor BL.sub.0 is selected as (V.sub.pg+V.sub.t1) greater than
the voltage (0) applied to the conductor WL.sub.0, where V.sub.pg,
as defined above, is in this embodiment 1.0 volts, and V.sub.t1,
(forward) threshold voltage of diode=0.6 volts, so that
V.sub.pg+V.sub.t1=1.6 volts. Additionally, this same voltage
V.sub.pg+V.sub.t1 of 1.6 volts is applied to each of the conductors
WL.sub.1, . . . WL.sub.n, and zero voltage is applied to each of
the conductors BL.sub.1, . . . BL.sub.n. This results in zero
potential being applied across each of the structures 60 (other
than the structure 60.sub.00) connected to the conductor BL.sub.0
and the conductor WL.sub.0. Each of the other structures 60 in the
array 140 has applied thereacross, from higher to lower potential
in the direction from conductor WL to conductor BL, an electrical
potential which is equal to V.sub.pg+V.sub.t1=1.6 volts. This
electrical potential is less than the threshold voltage V.sub.t2 (2
volts) of the diode 134 (and less than the breakdown voltage
V.sub.b, 4.5 volts, of the diode 132), and thus no current flows
through the associated memory cells 130. Thus, the incorporation of
the diode structure 60 allows one to properly select and program a
memory cell, without disturbing or otherwise influencing any of the
other memory cells in the array.
[0033] In order to erase a selected memory cell (FIG. 10), for
example selected memory cell 130.sub.00, the voltage applied to the
conductor WL.sub.0 is (V.sub.er+V.sub.t2) greater than the voltage
(0) applied to the conductor BL.sub.0, where V.sub.er is as defined
above and is in this embodiment 1.0 volts, and V.sub.t2, the
threshold voltage of the diode, is 2.0 volts, so that
V.sub.er+V.sub.t2=3.0 volts. Additionally, a voltage of for example
0.5(V.sub.pg+V.sub.t2)=1.5 volts is applied to each of the
conductors WL.sub.1, . . . WL.sub.n, and each of the conductors
BL.sub.1, . . . . BL.sub.n. This results in a potential of 1.5
volts being applied across each of the structures 60 (other than
the structure 60.sub.00) connected to the conductor BL.sub.0 and
the conductor WL.sub.0, from higher to lower potential in the
direction from conductor WL to conductor BL. This electrical
potential of 1.5 volts is less than the threshold voltage V.sub.t2
(2.0 volts) of the diode 134 (and less than the breakdown voltage
V.sub.b, 4.5 volts, of the diode 132), and thus no current will
flow through the other memory cells 130 associated with conductor
BL.sub.0 and conductor WL.sub.0. Each of the other structures 60 in
the array 140 has applied thereacross an electrical potential of
zero. Similar to the above, the incorporation of the diode
structure 62 allows one to properly select and erase a memory cell,
without disturbing any of the other memory cells in the array.
[0034] In order to read a selected memory cell (FIG. 11), for
example selected memory cell 130.sub.00, the voltage applied to the
conductor BL.sub.0 is (V.sub.r+V.sub.t1) greater than the voltage
(0) applied to the conductor WL.sub.0, where V.sub.r is as defined
above and in this example equals 0.5 volts and V.sub.t1=threshold
voltage of diode 132.sub.00, i.e., 0.6 volts, so that
V.sub.r+V.sub.t1=1.1 volts. Additionally, a voltage of
V.sub.r+V.sub.t1=1.1 volts is applied to each of the conductors
WL1, . . . WL.sub.n, and zero voltage is applied to each of the
conductors BL1, . . . BL.sub.n. This results in zero potential
applied across each of the structures 60 (other than the structure
60.sub.00) connected to the conductor BL.sub.1 and WL.sub.0. Each
of the other structures 60 of the array has applied thereacross,
from higher to lower potential in the direction from conductor WL
to conductor BL, an electrical potential which is equal to
V.sub.r+V.sub.t1. This potential V.sub.r+V.sub.t1=1.1 volts is less
than the threshold voltage Vt2 (2.0 volts) of the diode 134 (and is
less than the breakdown voltage of the diode 132, 4.5 volts), so
that no current passes through the associated memory cell 130.
Thus, the incorporation of the diode structure 62 allows one to
properly select and read a memory cell, without disturbing any of
the other memory cells in the array.
[0035] It will be seen that a highly efficient and effective
approach for programming, erasing and reading resistive memory
cells is provided. Of particular importance is the achievement of a
diode structure which incorporates an ideal characteristic for
threshold voltage and breakdown voltage thereof.
[0036] The foregoing description of the embodiment of the invention
has been presented for purposes of illustration and description. It
is not intended to be exhaustive or to limit the invention to the
precise form disclosed. Other modifications or variations are
possible in light of the above teachings.
[0037] The embodiment was chosen and described to provide the best
illustration of the principles of the invention and its practical
application to thereby enable one of ordinary skill of the art to
utilize the invention in various embodiments and with various
modifications as are suited to the particular use contemplated. All
such modifications and variations are within the scope of the
invention as determined by the appended claims when interpreted in
accordance with the breadth to which they are fairly, legally and
equitably entitled.
* * * * *