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Patent applications and USPTO patent grants for Caffall; John.The latest application filed is for "method for reducing stress-induced voids for 0.25u and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby".
Patent | Date |
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Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processing Grant 7,118,967 - Ngo , et al. October 10, 2 | 2006-10-10 |
Reflowable-doped HDP film Grant 6,809,402 - Hopper , et al. October 26, 2 | 2004-10-26 |
Method For Reducing Stress-induced Voids For 0.25u And Smaller Semiconductor Chip Technology By Annealing Interconnect Lines And Using Low Bias Voltage And Low Interlayer Dielectric Deposition Rate And Semiconductor Chip Made Thereby App 20020003306 - NGO, MINH VAN ;   et al. | 2002-01-10 |
Method for reducing stress-induced voids for 0.25m.mu. and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby Grant 6,329,718 - Van Ngo , et al. December 11, 2 | 2001-12-11 |
In-situ deposition of stop layer and dielectric layer during formation of local interconnects Grant 6,060,404 - Ngo , et al. May 9, 2 | 2000-05-09 |
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