MACCRAE, NICK
Patent Applications and Registrations
Patent applications and USPTO patent grants for MACCRAE, NICK.The latest application filed is for "method for reducing stress-induced voids for 0.25u and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby".
- MACCRAE, NICK - SAN JOSE CA
| Patent | Date |
|---|---|
| Method For Reducing Stress-induced Voids For 0.25u And Smaller Semiconductor Chip Technology By Annealing Interconnect Lines And Using Low Bias Voltage And Low Interlayer Dielectric Deposition Rate And Semiconductor Chip Made Thereby App 20020003306 - NGO, MINH VAN ; et al. | 2002-01-10 |
| Method for reducing stress-induced voids for 0.25m.mu. and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby Grant 6,329,718 - Van Ngo , et al. December 11, 2 | 2001-12-11 |
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